arch/arm/boot/dts/sun8i-h3.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "skeleton.dtsi"
  44
  45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/sun4i-a10.h>
  48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
  49
  50 / {
  51         interrupt-parent = <&gic>;
  52
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 cpu@0 {
  58                         compatible = "arm,cortex-a7";
  59                         device_type = "cpu";
  60                         reg = <0>;
  61                 };
  62
  63                 cpu@1 {
  64                         compatible = "arm,cortex-a7";
  65                         device_type = "cpu";
  66                         reg = <1>;
  67                 };
  68
  69                 cpu@2 {
  70                         compatible = "arm,cortex-a7";
  71                         device_type = "cpu";
  72                         reg = <2>;
  73                 };
  74
  75                 cpu@3 {
  76                         compatible = "arm,cortex-a7";
  77                         device_type = "cpu";
  78                         reg = <3>;
  79                 };
  80         };
  81
  82         timer {
  83                 compatible = "arm,armv7-timer";
  84                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  85                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  86                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  87                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  88         };
  89
  90         clocks {
  91                 #address-cells = <1>;
  92                 #size-cells = <1>;
  93                 ranges;
  94
  95                 osc24M: osc24M_clk {
  96                         #clock-cells = <0>;
  97                         compatible = "fixed-clock";
  98                         clock-frequency = <24000000>;
  99                         clock-output-names = "osc24M";
 100                 };
 101
 102                 osc32k: osc32k_clk {
 103                         #clock-cells = <0>;
 104                         compatible = "fixed-clock";
 105                         clock-frequency = <32768>;
 106                         clock-output-names = "osc32k";
 107                 };
 108
 109                 apb0: apb0_clk {
 110                         compatible = "fixed-factor-clock";
 111                         #clock-cells = <0>;
 112                         clock-div = <1>;
 113                         clock-mult = <1>;
 114                         clocks = <&osc24M>;
 115                         clock-output-names = "apb0";
 116                 };
 117
 118                 apb0_gates: clk@01f01428 {
 119                         compatible = "allwinner,sun8i-h3-apb0-gates-clk",
 120                                      "allwinner,sun4i-a10-gates-clk";
 121                         reg = <0x01f01428 0x4>;
 122                         #clock-cells = <1>;
 123                         clocks = <&apb0>;
 124                         clock-indices = <0>, <1>;
 125                         clock-output-names = "apb0_pio", "apb0_ir";
 126                 };
 127
 128                 ir_clk: ir_clk@01f01454 {
 129                         compatible = "allwinner,sun4i-a10-mod0-clk";
 130                         reg = <0x01f01454 0x4>;
 131                         #clock-cells = <0>;
 132                         clocks = <&osc32k>, <&osc24M>;
 133                         clock-output-names = "ir";
 134                 };
 135         };
 136
 137         soc {
 138                 compatible = "simple-bus";
 139                 #address-cells = <1>;
 140                 #size-cells = <1>;
 141                 ranges;
 142
 143                 dma: dma-controller@01c02000 {
 144                         compatible = "allwinner,sun8i-h3-dma";
 145                         reg = <0x01c02000 0x1000>;
 146                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 147                         clocks = <&ccu CLK_BUS_DMA>;
 148                         resets = <&ccu RST_BUS_DMA>;
 149                         #dma-cells = <1>;
 150                 };
 151
 152                 mmc0: mmc@01c0f000 {
 153                         compatible = "allwinner,sun5i-a13-mmc";
 154                         reg = <0x01c0f000 0x1000>;
 155                         clocks = <&ccu CLK_BUS_MMC0>,
 156                                  <&ccu CLK_MMC0>,
 157                                  <&ccu CLK_MMC0_OUTPUT>,
 158                                  <&ccu CLK_MMC0_SAMPLE>;
 159                         clock-names = "ahb",
 160                                       "mmc",
 161                                       "output",
 162                                       "sample";
 163                         resets = <&ccu RST_BUS_MMC0>;
 164                         reset-names = "ahb";
 165                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 166                         status = "disabled";
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169                 };
 170
 171                 mmc1: mmc@01c10000 {
 172                         compatible = "allwinner,sun5i-a13-mmc";
 173                         reg = <0x01c10000 0x1000>;
 174                         clocks = <&ccu CLK_BUS_MMC1>,
 175                                  <&ccu CLK_MMC1>,
 176                                  <&ccu CLK_MMC1_OUTPUT>,
 177                                  <&ccu CLK_MMC1_SAMPLE>;
 178                         clock-names = "ahb",
 179                                       "mmc",
 180                                       "output",
 181                                       "sample";
 182                         resets = <&ccu RST_BUS_MMC1>;
 183                         reset-names = "ahb";
 184                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 185                         status = "disabled";
 186                         #address-cells = <1>;
 187                         #size-cells = <0>;
 188                 };
 189
 190                 mmc2: mmc@01c11000 {
 191                         compatible = "allwinner,sun5i-a13-mmc";
 192                         reg = <0x01c11000 0x1000>;
 193                         clocks = <&ccu CLK_BUS_MMC2>,
 194                                  <&ccu CLK_MMC2>,
 195                                  <&ccu CLK_MMC2_OUTPUT>,
 196                                  <&ccu CLK_MMC2_SAMPLE>;
 197                         clock-names = "ahb",
 198                                       "mmc",
 199                                       "output",
 200                                       "sample";
 201                         resets = <&ccu RST_BUS_MMC2>;
 202                         reset-names = "ahb";
 203                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 204                         status = "disabled";
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                 };
 208
 209                 usbphy: phy@01c19400 {
 210                         compatible = "allwinner,sun8i-h3-usb-phy";
 211                         reg = <0x01c19400 0x2c>,
 212                               <0x01c1a800 0x4>,
 213                               <0x01c1b800 0x4>,
 214                               <0x01c1c800 0x4>,
 215                               <0x01c1d800 0x4>;
 216                         reg-names = "phy_ctrl",
 217                                     "pmu0",
 218                                     "pmu1",
 219                                     "pmu2",
 220                                     "pmu3";
 221                         clocks = <&ccu CLK_USB_PHY0>,
 222                                  <&ccu CLK_USB_PHY1>,
 223                                  <&ccu CLK_USB_PHY2>,
 224                                  <&ccu CLK_USB_PHY3>;
 225                         clock-names = "usb0_phy",
 226                                       "usb1_phy",
 227                                       "usb2_phy",
 228                                       "usb3_phy";
 229                         resets = <&ccu RST_USB_PHY0>,
 230                                  <&ccu RST_USB_PHY1>,
 231                                  <&ccu RST_USB_PHY2>,
 232                                  <&ccu RST_USB_PHY3>;
 233                         reset-names = "usb0_reset",
 234                                       "usb1_reset",
 235                                       "usb2_reset",
 236                                       "usb3_reset";
 237                         status = "disabled";
 238                         #phy-cells = <1>;
 239                 };
 240
 241                 ehci1: usb@01c1b000 {
 242                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 243                         reg = <0x01c1b000 0x100>;
 244                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 245                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
 246                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 247                         phys = <&usbphy 1>;
 248                         phy-names = "usb";
 249                         status = "disabled";
 250                 };
 251
 252                 ohci1: usb@01c1b400 {
 253                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 254                         reg = <0x01c1b400 0x100>;
 255                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 256                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
 257                                  <&ccu CLK_USB_OHCI1>;
 258                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 259                         phys = <&usbphy 1>;
 260                         phy-names = "usb";
 261                         status = "disabled";
 262                 };
 263
 264                 ehci2: usb@01c1c000 {
 265                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 266                         reg = <0x01c1c000 0x100>;
 267                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 268                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
 269                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 270                         phys = <&usbphy 2>;
 271                         phy-names = "usb";
 272                         status = "disabled";
 273                 };
 274
 275                 ohci2: usb@01c1c400 {
 276                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 277                         reg = <0x01c1c400 0x100>;
 278                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
 280                                  <&ccu CLK_USB_OHCI2>;
 281                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 282                         phys = <&usbphy 2>;
 283                         phy-names = "usb";
 284                         status = "disabled";
 285                 };
 286
 287                 ehci3: usb@01c1d000 {
 288                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 289                         reg = <0x01c1d000 0x100>;
 290                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 291                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
 292                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 293                         phys = <&usbphy 3>;
 294                         phy-names = "usb";
 295                         status = "disabled";
 296                 };
 297
 298                 ohci3: usb@01c1d400 {
 299                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 300                         reg = <0x01c1d400 0x100>;
 301                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 302                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
 303                                  <&ccu CLK_USB_OHCI3>;
 304                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 305                         phys = <&usbphy 3>;
 306                         phy-names = "usb";
 307                         status = "disabled";
 308                 };
 309
 310                 ccu: clock@01c20000 {
 311                         compatible = "allwinner,sun8i-h3-ccu";
 312                         reg = <0x01c20000 0x400>;
 313                         clocks = <&osc24M>, <&osc32k>;
 314                         clock-names = "hosc", "losc";
 315                         #clock-cells = <1>;
 316                         #reset-cells = <1>;
 317                 };
 318
 319                 pio: pinctrl@01c20800 {
 320                         compatible = "allwinner,sun8i-h3-pinctrl";
 321                         reg = <0x01c20800 0x400>;
 322                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 323                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 324                         clocks = <&ccu CLK_BUS_PIO>;
 325                         gpio-controller;
 326                         #gpio-cells = <3>;
 327                         interrupt-controller;
 328                         #interrupt-cells = <3>;
 329
 330                         mmc0_pins_a: mmc0@0 {
 331                                 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
 332                                                  "PF4", "PF5";
 333                                 allwinner,function = "mmc0";
 334                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 335                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 336                         };
 337
 338                         mmc0_cd_pin: mmc0_cd_pin@0 {
 339                                 allwinner,pins = "PF6";
 340                                 allwinner,function = "gpio_in";
 341                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 342                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 343                         };
 344
 345                         mmc1_pins_a: mmc1@0 {
 346                                 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
 347                                                  "PG4", "PG5";
 348                                 allwinner,function = "mmc1";
 349                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 350                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 351                         };
 352
 353                         mmc2_8bit_pins: mmc2_8bit {
 354                                 allwinner,pins = "PC5", "PC6", "PC8",
 355                                                  "PC9", "PC10", "PC11",
 356                                                  "PC12", "PC13", "PC14",
 357                                                  "PC15", "PC16";
 358                                 allwinner,function = "mmc2";
 359                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 360                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 361                         };
 362
 363                         uart0_pins_a: uart0@0 {
 364                                 allwinner,pins = "PA4", "PA5";
 365                                 allwinner,function = "uart0";
 366                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 367                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 368                         };
 369
 370                         uart1_pins: uart1 {
 371                                 allwinner,pins = "PG6", "PG7";
 372                                 allwinner,function = "uart1";
 373                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 374                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 375                         };
 376
 377                         uart1_rts_cts_pins: uart1_rts_cts {
 378                                 allwinner,pins = "PG8", "PG9";
 379                                 allwinner,function = "uart1";
 380                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 381                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 382                         };
 383
 384                         uart2_pins: uart2 {
 385                                 allwinner,pins = "PA0", "PA1";
 386                                 allwinner,function = "uart2";
 387                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 388                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 389                         };
 390
 391                         uart3_pins: uart3 {
 392                                 allwinner,pins = "PG13", "PG14";
 393                                 allwinner,function = "uart3";
 394                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 395                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 396                         };
 397                 };
 398
 399                 timer@01c20c00 {
 400                         compatible = "allwinner,sun4i-a10-timer";
 401                         reg = <0x01c20c00 0xa0>;
 402                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 403                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 404                         clocks = <&osc24M>;
 405                 };
 406
 407                 wdt0: watchdog@01c20ca0 {
 408                         compatible = "allwinner,sun6i-a31-wdt";
 409                         reg = <0x01c20ca0 0x20>;
 410                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 411                 };
 412
 413                 pwm: pwm@01c21400 {
 414                         compatible = "allwinner,sun8i-h3-pwm";
 415                         reg = <0x01c21400 0x8>;
 416                         clocks = <&osc24M>;
 417                         #pwm-cells = <3>;
 418                         status = "disabled";
 419                 };
 420
 421                 uart0: serial@01c28000 {
 422                         compatible = "snps,dw-apb-uart";
 423                         reg = <0x01c28000 0x400>;
 424                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 425                         reg-shift = <2>;
 426                         reg-io-width = <4>;
 427                         clocks = <&ccu CLK_BUS_UART0>;
 428                         resets = <&ccu RST_BUS_UART0>;
 429                         dmas = <&dma 6>, <&dma 6>;
 430                         dma-names = "rx", "tx";
 431                         status = "disabled";
 432                 };
 433
 434                 uart1: serial@01c28400 {
 435                         compatible = "snps,dw-apb-uart";
 436                         reg = <0x01c28400 0x400>;
 437                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 438                         reg-shift = <2>;
 439                         reg-io-width = <4>;
 440                         clocks = <&ccu CLK_BUS_UART1>;
 441                         resets = <&ccu RST_BUS_UART1>;
 442                         dmas = <&dma 7>, <&dma 7>;
 443                         dma-names = "rx", "tx";
 444                         status = "disabled";
 445                 };
 446
 447                 uart2: serial@01c28800 {
 448                         compatible = "snps,dw-apb-uart";
 449                         reg = <0x01c28800 0x400>;
 450                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 451                         reg-shift = <2>;
 452                         reg-io-width = <4>;
 453                         clocks = <&ccu CLK_BUS_UART2>;
 454                         resets = <&ccu RST_BUS_UART2>;
 455                         dmas = <&dma 8>, <&dma 8>;
 456                         dma-names = "rx", "tx";
 457                         status = "disabled";
 458                 };
 459
 460                 uart3: serial@01c28c00 {
 461                         compatible = "snps,dw-apb-uart";
 462                         reg = <0x01c28c00 0x400>;
 463                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 464                         reg-shift = <2>;
 465                         reg-io-width = <4>;
 466                         clocks = <&ccu CLK_BUS_UART3>;
 467                         resets = <&ccu RST_BUS_UART3>;
 468                         dmas = <&dma 9>, <&dma 9>;
 469                         dma-names = "rx", "tx";
 470                         status = "disabled";
 471                 };
 472
 473                 gic: interrupt-controller@01c81000 {
 474                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 475                         reg = <0x01c81000 0x1000>,
 476                               <0x01c82000 0x1000>,
 477                               <0x01c84000 0x2000>,
 478                               <0x01c86000 0x2000>;
 479                         interrupt-controller;
 480                         #interrupt-cells = <3>;
 481                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 482                 };
 483
 484                 rtc: rtc@01f00000 {
 485                         compatible = "allwinner,sun6i-a31-rtc";
 486                         reg = <0x01f00000 0x54>;
 487                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 488                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 489                 };
 490
 491                 apb0_reset: reset@01f014b0 {
 492                         reg = <0x01f014b0 0x4>;
 493                         compatible = "allwinner,sun6i-a31-clock-reset";
 494                         #reset-cells = <1>;
 495                 };
 496
 497                 ir: ir@01f02000 {
 498                         compatible = "allwinner,sun5i-a13-ir";
 499                         clocks = <&apb0_gates 1>, <&ir_clk>;
 500                         clock-names = "apb", "ir";
 501                         resets = <&apb0_reset 1>;
 502                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 503                         reg = <0x01f02000 0x40>;
 504                         status = "disabled";
 505                 };
 506
 507                 r_pio: pinctrl@01f02c00 {
 508                         compatible = "allwinner,sun8i-h3-r-pinctrl";
 509                         reg = <0x01f02c00 0x400>;
 510                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 511                         clocks = <&apb0_gates 0>;
 512                         resets = <&apb0_reset 0>;
 513                         gpio-controller;
 514                         #gpio-cells = <3>;
 515                         interrupt-controller;
 516                         #interrupt-cells = <3>;
 517
 518                         ir_pins_a: ir@0 {
 519                                 allwinner,pins = "PL11";
 520                                 allwinner,function = "s_cir_rx";
 521                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 522                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 523                         };
 524                 };
 525         };
 526 };