arch/arm/boot/dts/tegra114.dtsi

   1 #include <dt-bindings/clock/tegra114-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra114";
  10         interrupt-parent = <&gic>;
  11
  12         aliases {
  13                 serial0 = &uarta;
  14                 serial1 = &uartb;
  15                 serial2 = &uartc;
  16                 serial3 = &uartd;
  17         };
  18
  19         host1x@50000000 {
  20                 compatible = "nvidia,tegra114-host1x", "simple-bus";
  21                 reg = <0x50000000 0x00028000>;
  22                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  23                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  24                 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
  25                 resets = <&tegra_car 28>;
  26                 reset-names = "host1x";
  27
  28                 #address-cells = <1>;
  29                 #size-cells = <1>;
  30
  31                 ranges = <0x54000000 0x54000000 0x01000000>;
  32
  33                 gr2d@54140000 {
  34                         compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
  35                         reg = <0x54140000 0x00040000>;
  36                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  37                         clocks = <&tegra_car TEGRA114_CLK_GR2D>;
  38                         resets = <&tegra_car 21>;
  39                         reset-names = "2d";
  40                 };
  41
  42                 gr3d@54180000 {
  43                         compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
  44                         reg = <0x54180000 0x00040000>;
  45                         clocks = <&tegra_car TEGRA114_CLK_GR3D>;
  46                         resets = <&tegra_car 24>;
  47                         reset-names = "3d";
  48                 };
  49
  50                 dc@54200000 {
  51                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  52                         reg = <0x54200000 0x00040000>;
  53                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  54                         clocks = <&tegra_car TEGRA114_CLK_DISP1>,
  55                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  56                         clock-names = "dc", "parent";
  57                         resets = <&tegra_car 27>;
  58                         reset-names = "dc";
  59
  60                         nvidia,head = <0>;
  61
  62                         rgb {
  63                                 status = "disabled";
  64                         };
  65                 };
  66
  67                 dc@54240000 {
  68                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  69                         reg = <0x54240000 0x00040000>;
  70                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  71                         clocks = <&tegra_car TEGRA114_CLK_DISP2>,
  72                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  73                         clock-names = "dc", "parent";
  74                         resets = <&tegra_car 26>;
  75                         reset-names = "dc";
  76
  77                         nvidia,head = <1>;
  78
  79                         rgb {
  80                                 status = "disabled";
  81                         };
  82                 };
  83
  84                 hdmi@54280000 {
  85                         compatible = "nvidia,tegra114-hdmi";
  86                         reg = <0x54280000 0x00040000>;
  87                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  88                         clocks = <&tegra_car TEGRA114_CLK_HDMI>,
  89                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
  90                         clock-names = "hdmi", "parent";
  91                         resets = <&tegra_car 51>;
  92                         reset-names = "hdmi";
  93                         status = "disabled";
  94                 };
  95
  96                 dsi@54300000 {
  97                         compatible = "nvidia,tegra114-dsi";
  98                         reg = <0x54300000 0x00040000>;
  99                         clocks = <&tegra_car TEGRA114_CLK_DSIA>,
 100                                  <&tegra_car TEGRA114_CLK_DSIALP>,
 101                                  <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
 102                         clock-names = "dsi", "lp", "parent";
 103                         resets = <&tegra_car 48>;
 104                         reset-names = "dsi";
 105                         nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
 106                         status = "disabled";
 107
 108                         #address-cells = <1>;
 109                         #size-cells = <0>;
 110                 };
 111
 112                 dsi@54400000 {
 113                         compatible = "nvidia,tegra114-dsi";
 114                         reg = <0x54400000 0x00040000>;
 115                         clocks = <&tegra_car TEGRA114_CLK_DSIB>,
 116                                  <&tegra_car TEGRA114_CLK_DSIBLP>,
 117                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
 118                         clock-names = "dsi", "lp", "parent";
 119                         resets = <&tegra_car 82>;
 120                         reset-names = "dsi";
 121                         nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
 122                         status = "disabled";
 123
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                 };
 127         };
 128
 129         gic: interrupt-controller@50041000 {
 130                 compatible = "arm,cortex-a15-gic";
 131                 #interrupt-cells = <3>;
 132                 interrupt-controller;
 133                 reg = <0x50041000 0x1000>,
 134                       <0x50042000 0x1000>,
 135                       <0x50044000 0x2000>,
 136                       <0x50046000 0x2000>;
 137                 interrupts = <GIC_PPI 9
 138                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 139         };
 140
 141         timer@60005000 {
 142                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
 143                 reg = <0x60005000 0x400>;
 144                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 150                 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
 151         };
 152
 153         tegra_car: clock@60006000 {
 154                 compatible = "nvidia,tegra114-car";
 155                 reg = <0x60006000 0x1000>;
 156                 #clock-cells = <1>;
 157                 #reset-cells = <1>;
 158         };
 159
 160         apbdma: dma@6000a000 {
 161                 compatible = "nvidia,tegra114-apbdma";
 162                 reg = <0x6000a000 0x1400>;
 163                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 164                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 181                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 195                 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
 196                 resets = <&tegra_car 34>;
 197                 reset-names = "dma";
 198                 #dma-cells = <1>;
 199         };
 200
 201         ahb: ahb@6000c004 {
 202                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
 203                 reg = <0x6000c004 0x14c>;
 204         };
 205
 206         gpio: gpio@6000d000 {
 207                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 208                 reg = <0x6000d000 0x1000>;
 209                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 217                 #gpio-cells = <2>;
 218                 gpio-controller;
 219                 #interrupt-cells = <2>;
 220                 interrupt-controller;
 221         };
 222
 223         apbmisc@70000800 {
 224                 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
 225                 reg = <0x70000800 0x64   /* Chip revision */
 226                        0x70000008 0x04>; /* Strapping options */
 227         };
 228
 229         pinmux: pinmux@70000868 {
 230                 compatible = "nvidia,tegra114-pinmux";
 231                 reg = <0x70000868 0x148         /* Pad control registers */
 232                        0x70003000 0x40c>;       /* Mux registers */
 233         };
 234
 235         /*
 236          * There are two serial driver i.e. 8250 based simple serial
 237          * driver and APB DMA based serial driver for higher baudrate
 238          * and performace. To enable the 8250 based driver, the compatible
 239          * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
 240          * the APB DMA based serial driver, the comptible is
 241          * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
 242          */
 243         uarta: serial@70006000 {
 244                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 245                 reg = <0x70006000 0x40>;
 246                 reg-shift = <2>;
 247                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 248                 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 249                 resets = <&tegra_car 6>;
 250                 reset-names = "serial";
 251                 dmas = <&apbdma 8>, <&apbdma 8>;
 252                 dma-names = "rx", "tx";
 253                 status = "disabled";
 254         };
 255
 256         uartb: serial@70006040 {
 257                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 258                 reg = <0x70006040 0x40>;
 259                 reg-shift = <2>;
 260                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 261                 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 262                 resets = <&tegra_car 7>;
 263                 reset-names = "serial";
 264                 dmas = <&apbdma 9>, <&apbdma 9>;
 265                 dma-names = "rx", "tx";
 266                 status = "disabled";
 267         };
 268
 269         uartc: serial@70006200 {
 270                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 271                 reg = <0x70006200 0x100>;
 272                 reg-shift = <2>;
 273                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 274                 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 275                 resets = <&tegra_car 55>;
 276                 reset-names = "serial";
 277                 dmas = <&apbdma 10>, <&apbdma 10>;
 278                 dma-names = "rx", "tx";
 279                 status = "disabled";
 280         };
 281
 282         uartd: serial@70006300 {
 283                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 284                 reg = <0x70006300 0x100>;
 285                 reg-shift = <2>;
 286                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 287                 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 288                 resets = <&tegra_car 65>;
 289                 reset-names = "serial";
 290                 dmas = <&apbdma 19>, <&apbdma 19>;
 291                 dma-names = "rx", "tx";
 292                 status = "disabled";
 293         };
 294
 295         pwm: pwm@7000a000 {
 296                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
 297                 reg = <0x7000a000 0x100>;
 298                 #pwm-cells = <2>;
 299                 clocks = <&tegra_car TEGRA114_CLK_PWM>;
 300                 resets = <&tegra_car 17>;
 301                 reset-names = "pwm";
 302                 status = "disabled";
 303         };
 304
 305         i2c@7000c000 {
 306                 compatible = "nvidia,tegra114-i2c";
 307                 reg = <0x7000c000 0x100>;
 308                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 309                 #address-cells = <1>;
 310                 #size-cells = <0>;
 311                 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
 312                 clock-names = "div-clk";
 313                 resets = <&tegra_car 12>;
 314                 reset-names = "i2c";
 315                 dmas = <&apbdma 21>, <&apbdma 21>;
 316                 dma-names = "rx", "tx";
 317                 status = "disabled";
 318         };
 319
 320         i2c@7000c400 {
 321                 compatible = "nvidia,tegra114-i2c";
 322                 reg = <0x7000c400 0x100>;
 323                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
 327                 clock-names = "div-clk";
 328                 resets = <&tegra_car 54>;
 329                 reset-names = "i2c";
 330                 dmas = <&apbdma 22>, <&apbdma 22>;
 331                 dma-names = "rx", "tx";
 332                 status = "disabled";
 333         };
 334
 335         i2c@7000c500 {
 336                 compatible = "nvidia,tegra114-i2c";
 337                 reg = <0x7000c500 0x100>;
 338                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 339                 #address-cells = <1>;
 340                 #size-cells = <0>;
 341                 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
 342                 clock-names = "div-clk";
 343                 resets = <&tegra_car 67>;
 344                 reset-names = "i2c";
 345                 dmas = <&apbdma 23>, <&apbdma 23>;
 346                 dma-names = "rx", "tx";
 347                 status = "disabled";
 348         };
 349
 350         i2c@7000c700 {
 351                 compatible = "nvidia,tegra114-i2c";
 352                 reg = <0x7000c700 0x100>;
 353                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356                 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
 357                 clock-names = "div-clk";
 358                 resets = <&tegra_car 103>;
 359                 reset-names = "i2c";
 360                 dmas = <&apbdma 26>, <&apbdma 26>;
 361                 dma-names = "rx", "tx";
 362                 status = "disabled";
 363         };
 364
 365         i2c@7000d000 {
 366                 compatible = "nvidia,tegra114-i2c";
 367                 reg = <0x7000d000 0x100>;
 368                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371                 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
 372                 clock-names = "div-clk";
 373                 resets = <&tegra_car 47>;
 374                 reset-names = "i2c";
 375                 dmas = <&apbdma 24>, <&apbdma 24>;
 376                 dma-names = "rx", "tx";
 377                 status = "disabled";
 378         };
 379
 380         spi@7000d400 {
 381                 compatible = "nvidia,tegra114-spi";
 382                 reg = <0x7000d400 0x200>;
 383                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
 387                 clock-names = "spi";
 388                 resets = <&tegra_car 41>;
 389                 reset-names = "spi";
 390                 dmas = <&apbdma 15>, <&apbdma 15>;
 391                 dma-names = "rx", "tx";
 392                 status = "disabled";
 393         };
 394
 395         spi@7000d600 {
 396                 compatible = "nvidia,tegra114-spi";
 397                 reg = <0x7000d600 0x200>;
 398                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 399                 #address-cells = <1>;
 400                 #size-cells = <0>;
 401                 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
 402                 clock-names = "spi";
 403                 resets = <&tegra_car 44>;
 404                 reset-names = "spi";
 405                 dmas = <&apbdma 16>, <&apbdma 16>;
 406                 dma-names = "rx", "tx";
 407                 status = "disabled";
 408         };
 409
 410         spi@7000d800 {
 411                 compatible = "nvidia,tegra114-spi";
 412                 reg = <0x7000d800 0x200>;
 413                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416                 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
 417                 clock-names = "spi";
 418                 resets = <&tegra_car 46>;
 419                 reset-names = "spi";
 420                 dmas = <&apbdma 17>, <&apbdma 17>;
 421                 dma-names = "rx", "tx";
 422                 status = "disabled";
 423         };
 424
 425         spi@7000da00 {
 426                 compatible = "nvidia,tegra114-spi";
 427                 reg = <0x7000da00 0x200>;
 428                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
 432                 clock-names = "spi";
 433                 resets = <&tegra_car 68>;
 434                 reset-names = "spi";
 435                 dmas = <&apbdma 18>, <&apbdma 18>;
 436                 dma-names = "rx", "tx";
 437                 status = "disabled";
 438         };
 439
 440         spi@7000dc00 {
 441                 compatible = "nvidia,tegra114-spi";
 442                 reg = <0x7000dc00 0x200>;
 443                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
 447                 clock-names = "spi";
 448                 resets = <&tegra_car 104>;
 449                 reset-names = "spi";
 450                 dmas = <&apbdma 27>, <&apbdma 27>;
 451                 dma-names = "rx", "tx";
 452                 status = "disabled";
 453         };
 454
 455         spi@7000de00 {
 456                 compatible = "nvidia,tegra114-spi";
 457                 reg = <0x7000de00 0x200>;
 458                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
 462                 clock-names = "spi";
 463                 resets = <&tegra_car 105>;
 464                 reset-names = "spi";
 465                 dmas = <&apbdma 28>, <&apbdma 28>;
 466                 dma-names = "rx", "tx";
 467                 status = "disabled";
 468         };
 469
 470         rtc@7000e000 {
 471                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
 472                 reg = <0x7000e000 0x100>;
 473                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 474                 clocks = <&tegra_car TEGRA114_CLK_RTC>;
 475         };
 476
 477         kbc@7000e200 {
 478                 compatible = "nvidia,tegra114-kbc";
 479                 reg = <0x7000e200 0x100>;
 480                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 481                 clocks = <&tegra_car TEGRA114_CLK_KBC>;
 482                 resets = <&tegra_car 36>;
 483                 reset-names = "kbc";
 484                 status = "disabled";
 485         };
 486
 487         pmc@7000e400 {
 488                 compatible = "nvidia,tegra114-pmc";
 489                 reg = <0x7000e400 0x400>;
 490                 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
 491                 clock-names = "pclk", "clk32k_in";
 492         };
 493
 494         fuse@7000f800 {
 495                 compatible = "nvidia,tegra114-efuse";
 496                 reg = <0x7000f800 0x400>;
 497                 clocks = <&tegra_car TEGRA114_CLK_FUSE>;
 498                 clock-names = "fuse";
 499                 resets = <&tegra_car 39>;
 500                 reset-names = "fuse";
 501         };
 502
 503         iommu@70019010 {
 504                 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
 505                 reg = <0x70019010 0x02c
 506                        0x700191f0 0x010
 507                        0x70019228 0x074>;
 508                 nvidia,#asids = <4>;
 509                 dma-window = <0 0x40000000>;
 510                 nvidia,swgroups = <0x18659fe>;
 511                 nvidia,ahb = <&ahb>;
 512         };
 513
 514         ahub@70080000 {
 515                 compatible = "nvidia,tegra114-ahub";
 516                 reg = <0x70080000 0x200>,
 517                       <0x70080200 0x100>,
 518                       <0x70081000 0x200>;
 519                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 520                 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
 521                          <&tegra_car TEGRA114_CLK_APBIF>;
 522                 clock-names = "d_audio", "apbif";
 523                 resets = <&tegra_car 106>, /* d_audio */
 524                          <&tegra_car 107>, /* apbif */
 525                          <&tegra_car 30>,  /* i2s0 */
 526                          <&tegra_car 11>,  /* i2s1 */
 527                          <&tegra_car 18>,  /* i2s2 */
 528                          <&tegra_car 101>, /* i2s3 */
 529                          <&tegra_car 102>, /* i2s4 */
 530                          <&tegra_car 108>, /* dam0 */
 531                          <&tegra_car 109>, /* dam1 */
 532                          <&tegra_car 110>, /* dam2 */
 533                          <&tegra_car 10>,  /* spdif */
 534                          <&tegra_car 153>, /* amx */
 535                          <&tegra_car 154>; /* adx */
 536                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 537                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 538                               "spdif", "amx", "adx";
 539                 dmas = <&apbdma 1>, <&apbdma 1>,
 540                        <&apbdma 2>, <&apbdma 2>,
 541                        <&apbdma 3>, <&apbdma 3>,
 542                        <&apbdma 4>, <&apbdma 4>,
 543                        <&apbdma 6>, <&apbdma 6>,
 544                        <&apbdma 7>, <&apbdma 7>,
 545                        <&apbdma 12>, <&apbdma 12>,
 546                        <&apbdma 13>, <&apbdma 13>,
 547                        <&apbdma 14>, <&apbdma 14>,
 548                        <&apbdma 29>, <&apbdma 29>;
 549                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 550                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 551                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 552                             "rx9", "tx9";
 553                 ranges;
 554                 #address-cells = <1>;
 555                 #size-cells = <1>;
 556
 557                 tegra_i2s0: i2s@70080300 {
 558                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 559                         reg = <0x70080300 0x100>;
 560                         nvidia,ahub-cif-ids = <4 4>;
 561                         clocks = <&tegra_car TEGRA114_CLK_I2S0>;
 562                         resets = <&tegra_car 30>;
 563                         reset-names = "i2s";
 564                         status = "disabled";
 565                 };
 566
 567                 tegra_i2s1: i2s@70080400 {
 568                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 569                         reg = <0x70080400 0x100>;
 570                         nvidia,ahub-cif-ids = <5 5>;
 571                         clocks = <&tegra_car TEGRA114_CLK_I2S1>;
 572                         resets = <&tegra_car 11>;
 573                         reset-names = "i2s";
 574                         status = "disabled";
 575                 };
 576
 577                 tegra_i2s2: i2s@70080500 {
 578                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 579                         reg = <0x70080500 0x100>;
 580                         nvidia,ahub-cif-ids = <6 6>;
 581                         clocks = <&tegra_car TEGRA114_CLK_I2S2>;
 582                         resets = <&tegra_car 18>;
 583                         reset-names = "i2s";
 584                         status = "disabled";
 585                 };
 586
 587                 tegra_i2s3: i2s@70080600 {
 588                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 589                         reg = <0x70080600 0x100>;
 590                         nvidia,ahub-cif-ids = <7 7>;
 591                         clocks = <&tegra_car TEGRA114_CLK_I2S3>;
 592                         resets = <&tegra_car 101>;
 593                         reset-names = "i2s";
 594                         status = "disabled";
 595                 };
 596
 597                 tegra_i2s4: i2s@70080700 {
 598                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 599                         reg = <0x70080700 0x100>;
 600                         nvidia,ahub-cif-ids = <8 8>;
 601                         clocks = <&tegra_car TEGRA114_CLK_I2S4>;
 602                         resets = <&tegra_car 102>;
 603                         reset-names = "i2s";
 604                         status = "disabled";
 605                 };
 606         };
 607
 608         mipi: mipi@700e3000 {
 609                 compatible = "nvidia,tegra114-mipi";
 610                 reg = <0x700e3000 0x100>;
 611                 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
 612                 #nvidia,mipi-calibrate-cells = <1>;
 613         };
 614
 615         sdhci@78000000 {
 616                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 617                 reg = <0x78000000 0x200>;
 618                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 619                 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
 620                 resets = <&tegra_car 14>;
 621                 reset-names = "sdhci";
 622                 status = "disabled";
 623         };
 624
 625         sdhci@78000200 {
 626                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 627                 reg = <0x78000200 0x200>;
 628                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 629                 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
 630                 resets = <&tegra_car 9>;
 631                 reset-names = "sdhci";
 632                 status = "disabled";
 633         };
 634
 635         sdhci@78000400 {
 636                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 637                 reg = <0x78000400 0x200>;
 638                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 639                 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
 640                 resets = <&tegra_car 69>;
 641                 reset-names = "sdhci";
 642                 status = "disabled";
 643         };
 644
 645         sdhci@78000600 {
 646                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 647                 reg = <0x78000600 0x200>;
 648                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 649                 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
 650                 resets = <&tegra_car 15>;
 651                 reset-names = "sdhci";
 652                 status = "disabled";
 653         };
 654
 655         usb@7d000000 {
 656                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 657                 reg = <0x7d000000 0x4000>;
 658                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 659                 phy_type = "utmi";
 660                 clocks = <&tegra_car TEGRA114_CLK_USBD>;
 661                 resets = <&tegra_car 22>;
 662                 reset-names = "usb";
 663                 nvidia,phy = <&phy1>;
 664                 status = "disabled";
 665         };
 666
 667         phy1: usb-phy@7d000000 {
 668                 compatible = "nvidia,tegra30-usb-phy";
 669                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 670                 phy_type = "utmi";
 671                 clocks = <&tegra_car TEGRA114_CLK_USBD>,
 672                          <&tegra_car TEGRA114_CLK_PLL_U>,
 673                          <&tegra_car TEGRA114_CLK_USBD>;
 674                 clock-names = "reg", "pll_u", "utmi-pads";
 675                 resets = <&tegra_car 22>, <&tegra_car 22>;
 676                 reset-names = "usb", "utmi-pads";
 677                 nvidia,hssync-start-delay = <0>;
 678                 nvidia,idle-wait-delay = <17>;
 679                 nvidia,elastic-limit = <16>;
 680                 nvidia,term-range-adj = <6>;
 681                 nvidia,xcvr-setup = <9>;
 682                 nvidia,xcvr-lsfslew = <0>;
 683                 nvidia,xcvr-lsrslew = <3>;
 684                 nvidia,hssquelch-level = <2>;
 685                 nvidia,hsdiscon-level = <5>;
 686                 nvidia,xcvr-hsslew = <12>;
 687                 nvidia,has-utmi-pad-registers;
 688                 status = "disabled";
 689         };
 690
 691         usb@7d008000 {
 692                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 693                 reg = <0x7d008000 0x4000>;
 694                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 695                 phy_type = "utmi";
 696                 clocks = <&tegra_car TEGRA114_CLK_USB3>;
 697                 resets = <&tegra_car 59>;
 698                 reset-names = "usb";
 699                 nvidia,phy = <&phy3>;
 700                 status = "disabled";
 701         };
 702
 703         phy3: usb-phy@7d008000 {
 704                 compatible = "nvidia,tegra30-usb-phy";
 705                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 706                 phy_type = "utmi";
 707                 clocks = <&tegra_car TEGRA114_CLK_USB3>,
 708                          <&tegra_car TEGRA114_CLK_PLL_U>,
 709                          <&tegra_car TEGRA114_CLK_USBD>;
 710                 clock-names = "reg", "pll_u", "utmi-pads";
 711                 resets = <&tegra_car 59>, <&tegra_car 22>;
 712                 reset-names = "usb", "utmi-pads";
 713                 nvidia,hssync-start-delay = <0>;
 714                 nvidia,idle-wait-delay = <17>;
 715                 nvidia,elastic-limit = <16>;
 716                 nvidia,term-range-adj = <6>;
 717                 nvidia,xcvr-setup = <9>;
 718                 nvidia,xcvr-lsfslew = <0>;
 719                 nvidia,xcvr-lsrslew = <3>;
 720                 nvidia,hssquelch-level = <2>;
 721                 nvidia,hsdiscon-level = <5>;
 722                 nvidia,xcvr-hsslew = <12>;
 723                 status = "disabled";
 724         };
 725
 726         cpus {
 727                 #address-cells = <1>;
 728                 #size-cells = <0>;
 729
 730                 cpu@0 {
 731                         device_type = "cpu";
 732                         compatible = "arm,cortex-a15";
 733                         reg = <0>;
 734                 };
 735
 736                 cpu@1 {
 737                         device_type = "cpu";
 738                         compatible = "arm,cortex-a15";
 739                         reg = <1>;
 740                 };
 741
 742                 cpu@2 {
 743                         device_type = "cpu";
 744                         compatible = "arm,cortex-a15";
 745                         reg = <2>;
 746                 };
 747
 748                 cpu@3 {
 749                         device_type = "cpu";
 750                         compatible = "arm,cortex-a15";
 751                         reg = <3>;
 752                 };
 753         };
 754
 755         timer {
 756                 compatible = "arm,armv7-timer";
 757                 interrupts =
 758                         <GIC_PPI 13
 759                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 760                         <GIC_PPI 14
 761                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 762                         <GIC_PPI 11
 763                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 764                         <GIC_PPI 10
 765                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 766         };
 767 };