arch/arm/boot/dts/tegra124-apalis.dtsi

   1 /*
   2  * Copyright 2016 Toradex AG
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include "tegra124.dtsi"
  43 #include "tegra124-apalis-emc.dtsi"
  44
  45 /*
  46  * Toradex Apalis TK1 Module Device Tree
  47  * Compatible for Revisions 2GB: V1.0A
  48  */
  49 / {
  50         model = "Toradex Apalis TK1";
  51         compatible = "toradex,apalis-tk1", "nvidia,tegra124";
  52
  53         memory {
  54                 reg = <0x0 0x80000000 0x0 0x80000000>;
  55         };
  56
  57         pcie-controller@01003000 {
  58                 status = "okay";
  59
  60                 avddio-pex-supply = <&vdd_1v05>;
  61                 avdd-pex-pll-supply = <&vdd_1v05>;
  62                 avdd-pll-erefe-supply = <&avdd_1v05>;
  63                 dvddio-pex-supply = <&vdd_1v05>;
  64                 hvdd-pex-pll-e-supply = <&reg_3v3>;
  65                 hvdd-pex-supply = <&reg_3v3>;
  66                 vddio-pex-ctl-supply = <&reg_3v3>;
  67
  68                 /* Apalis PCIe (additional lane Apalis type specific) */
  69                 pci@1,0 {
  70                         /* PCIE1_RX/TX and TS_DIFF1/2 */
  71                         phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
  72                                <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
  73                         phy-names = "pcie-0", "pcie-1";
  74                 };
  75
  76                 /* I210 Gigabit Ethernet Controller (On-module) */
  77                 pci@2,0 {
  78                         phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
  79                         phy-names = "pcie-0";
  80                         status = "okay";
  81                 };
  82         };
  83
  84         host1x@50000000 {
  85                 hdmi@54280000 {
  86                         pll-supply = <&reg_1v05_avdd_hdmi_pll>;
  87                         vdd-supply = <&reg_3v3_avdd_hdmi>;
  88
  89                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  90                         nvidia,hpd-gpio =
  91                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  92                 };
  93         };
  94
  95         gpu@0,57000000 {
  96                 /*
  97                  * Node left disabled on purpose - the bootloader will enable
  98                  * it after having set the VPR up
  99                  */
 100                 vdd-supply = <&vdd_gpu>;
 101         };
 102
 103         pinmux: pinmux@70000868 {
 104                 pinctrl-names = "default";
 105                 pinctrl-0 = <&state_default>;
 106
 107                 state_default: pinmux {
 108                         /* Analogue Audio (On-module) */
 109                         dap3_fs_pp0 {
 110                                 nvidia,pins = "dap3_fs_pp0";
 111                                 nvidia,function = "i2s2";
 112                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 113                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 114                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 115                         };
 116                         dap3_din_pp1 {
 117                                 nvidia,pins = "dap3_din_pp1";
 118                                 nvidia,function = "i2s2";
 119                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 120                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 121                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 122                         };
 123                         dap3_dout_pp2 {
 124                                 nvidia,pins = "dap3_dout_pp2";
 125                                 nvidia,function = "i2s2";
 126                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 127                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 128                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 129                         };
 130                         dap3_sclk_pp3 {
 131                                 nvidia,pins = "dap3_sclk_pp3";
 132                                 nvidia,function = "i2s2";
 133                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 134                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 135                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 136                         };
 137                         dap_mclk1_pw4 {
 138                                 nvidia,pins = "dap_mclk1_pw4";
 139                                 nvidia,function = "extperiph1";
 140                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 141                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 142                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 143                         };
 144
 145                         /* Apalis BKL1_ON */
 146                         pbb5 {
 147                                 nvidia,pins = "pbb5";
 148                                 nvidia,function = "vgp5";
 149                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 150                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 151                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 152                         };
 153
 154                         /* Apalis BKL1_PWM */
 155                         pu6 {
 156                                 nvidia,pins = "pu6";
 157                                 nvidia,function = "pwm3";
 158                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 159                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 160                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 161                         };
 162
 163                         /* Apalis CAM1_MCLK */
 164                         cam_mclk_pcc0 {
 165                                 nvidia,pins = "cam_mclk_pcc0";
 166                                 nvidia,function = "vi_alt3";
 167                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 168                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 169                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 170                         };
 171
 172                         /* Apalis Digital Audio */
 173                         dap2_fs_pa2 {
 174                                 nvidia,pins = "dap2_fs_pa2";
 175                                 nvidia,function = "hda";
 176                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 177                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 178                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 179                         };
 180                         dap2_sclk_pa3 {
 181                                 nvidia,pins = "dap2_sclk_pa3";
 182                                 nvidia,function = "hda";
 183                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 184                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 185                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 186                         };
 187                         dap2_din_pa4 {
 188                                 nvidia,pins = "dap2_din_pa4";
 189                                 nvidia,function = "hda";
 190                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 191                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 192                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 193                         };
 194                         dap2_dout_pa5 {
 195                                 nvidia,pins = "dap2_dout_pa5";
 196                                 nvidia,function = "hda";
 197                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 198                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 199                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 200                         };
 201                         pbb3 { /* DAP1_RESET */
 202                                 nvidia,pins = "pbb3";
 203                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 204                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 205                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 206                         };
 207                         clk3_out_pee0 {
 208                                 nvidia,pins = "clk3_out_pee0";
 209                                 nvidia,function = "extperiph3";
 210                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 211                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 212                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 213                         };
 214
 215                         /* Apalis GPIO */
 216                         ddc_scl_pv4 {
 217                                 nvidia,pins = "ddc_scl_pv4";
 218                                 nvidia,function = "rsvd2";
 219                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 220                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 221                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 222                         };
 223                         ddc_sda_pv5 {
 224                                 nvidia,pins = "ddc_sda_pv5";
 225                                 nvidia,function = "rsvd2";
 226                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 227                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 228                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 229                         };
 230                         pex_l0_rst_n_pdd1 {
 231                                 nvidia,pins = "pex_l0_rst_n_pdd1";
 232                                 nvidia,function = "rsvd2";
 233                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 234                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 235                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 236                         };
 237                         pex_l0_clkreq_n_pdd2 {
 238                                 nvidia,pins = "pex_l0_clkreq_n_pdd2";
 239                                 nvidia,function = "rsvd2";
 240                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 241                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 242                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 243                         };
 244                         pex_l1_rst_n_pdd5 {
 245                                 nvidia,pins = "pex_l1_rst_n_pdd5";
 246                                 nvidia,function = "rsvd2";
 247                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 248                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 249                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 250                         };
 251                         pex_l1_clkreq_n_pdd6 {
 252                                 nvidia,pins = "pex_l1_clkreq_n_pdd6";
 253                                 nvidia,function = "rsvd2";
 254                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 255                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 256                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 257                         };
 258                         dp_hpd_pff0 {
 259                                 nvidia,pins = "dp_hpd_pff0";
 260                                 nvidia,function = "rsvd2";
 261                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 262                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 263                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 264                         };
 265                         pff2 {
 266                                 nvidia,pins = "pff2";
 267                                 nvidia,function = "rsvd2";
 268                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 269                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 270                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 271                         };
 272                         owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
 273                                 nvidia,pins = "owr";
 274                                 nvidia,function = "rsvd2";
 275                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 276                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 277                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 278                                 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
 279                         };
 280
 281                         /* Apalis HDMI1_CEC */
 282                         hdmi_cec_pee3 {
 283                                 nvidia,pins = "hdmi_cec_pee3";
 284                                 nvidia,function = "cec";
 285                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 286                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 287                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 288                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 289                         };
 290
 291                         /* Apalis HDMI1_HPD */
 292                         hdmi_int_pn7 {
 293                                 nvidia,pins = "hdmi_int_pn7";
 294                                 nvidia,function = "rsvd1";
 295                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 296                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 297                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 298                                 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
 299                         };
 300
 301                         /* Apalis I2C1 */
 302                         gen1_i2c_scl_pc4 {
 303                                 nvidia,pins = "gen1_i2c_scl_pc4";
 304                                 nvidia,function = "i2c1";
 305                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 306                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 307                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 308                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 309                         };
 310                         gen1_i2c_sda_pc5 {
 311                                 nvidia,pins = "gen1_i2c_sda_pc5";
 312                                 nvidia,function = "i2c1";
 313                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 314                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 315                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 316                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 317                         };
 318
 319                         /* Apalis I2C2 (DDC) */
 320                         gen2_i2c_scl_pt5 {
 321                                 nvidia,pins = "gen2_i2c_scl_pt5";
 322                                 nvidia,function = "i2c2";
 323                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 324                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 325                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 326                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 327                         };
 328                         gen2_i2c_sda_pt6 {
 329                                 nvidia,pins = "gen2_i2c_sda_pt6";
 330                                 nvidia,function = "i2c2";
 331                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 332                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 333                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 334                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 335                         };
 336
 337                         /* Apalis I2C3 (CAM) */
 338                         cam_i2c_scl_pbb1 {
 339                                 nvidia,pins = "cam_i2c_scl_pbb1";
 340                                 nvidia,function = "i2c3";
 341                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 342                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 343                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 344                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 345                         };
 346                         cam_i2c_sda_pbb2 {
 347                                 nvidia,pins = "cam_i2c_sda_pbb2";
 348                                 nvidia,function = "i2c3";
 349                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 350                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 351                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 352                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 353                         };
 354
 355                         /* Apalis MMC1 */
 356                         sdmmc1_cd_n_pv3 { /* CD# GPIO */
 357                                 nvidia,pins = "sdmmc1_wp_n_pv3";
 358                                 nvidia,function = "sdmmc1";
 359                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 360                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 361                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 362                         };
 363                         clk2_out_pw5 { /* D5 GPIO */
 364                                 nvidia,pins = "clk2_out_pw5";
 365                                 nvidia,function = "rsvd2";
 366                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 367                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 368                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 369                         };
 370                         sdmmc1_dat3_py4 {
 371                                 nvidia,pins = "sdmmc1_dat3_py4";
 372                                 nvidia,function = "sdmmc1";
 373                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 374                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 375                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 376                         };
 377                         sdmmc1_dat2_py5 {
 378                                 nvidia,pins = "sdmmc1_dat2_py5";
 379                                 nvidia,function = "sdmmc1";
 380                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 381                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 382                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 383                         };
 384                         sdmmc1_dat1_py6 {
 385                                 nvidia,pins = "sdmmc1_dat1_py6";
 386                                 nvidia,function = "sdmmc1";
 387                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 388                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 389                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 390                         };
 391                         sdmmc1_dat0_py7 {
 392                                 nvidia,pins = "sdmmc1_dat0_py7";
 393                                 nvidia,function = "sdmmc1";
 394                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 395                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 396                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 397                         };
 398                         sdmmc1_clk_pz0 {
 399                                 nvidia,pins = "sdmmc1_clk_pz0";
 400                                 nvidia,function = "sdmmc1";
 401                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 402                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 403                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 404                         };
 405                         sdmmc1_cmd_pz1 {
 406                                 nvidia,pins = "sdmmc1_cmd_pz1";
 407                                 nvidia,function = "sdmmc1";
 408                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 409                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 410                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 411                         };
 412                         clk2_req_pcc5 { /* D4 GPIO */
 413                                 nvidia,pins = "clk2_req_pcc5";
 414                                 nvidia,function = "rsvd2";
 415                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 416                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 417                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 418                         };
 419                         /*
 420                          * Don't use MMC1_D6 aka SDMMC3_CLK_LB_IN for now as it
 421                          * features some magic properties even though the
 422                          * external loopback is disabled and the internal
 423                          * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
 424                          * register's SDMMC_SPARE1 bits being set to 0xfffd
 425                          * according to the TRM!
 426                          */
 427                         sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
 428                                 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
 429                                 nvidia,function = "sdmmc3";
 430                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 431                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 432                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 433                         };
 434                         usb_vbus_en2_pff1 { /* D7 GPIO */
 435                                 nvidia,pins = "usb_vbus_en2_pff1";
 436                                 nvidia,function = "rsvd2";
 437                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 438                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 439                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 440                         };
 441
 442                         /* Apalis PWM */
 443                         ph0 {
 444                                 nvidia,pins = "ph0";
 445                                 nvidia,function = "pwm0";
 446                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 447                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 448                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 449                         };
 450                         ph1 {
 451                                 nvidia,pins = "ph1";
 452                                 nvidia,function = "pwm1";
 453                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 454                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 455                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 456                         };
 457                         ph2 {
 458                                 nvidia,pins = "ph2";
 459                                 nvidia,function = "pwm2";
 460                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 461                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 462                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 463                         };
 464                         /* PWM3 active on pu6 being Apalis BKL1_PWM */
 465                         ph3 {
 466                                 nvidia,pins = "ph3";
 467                                 nvidia,function = "gmi";
 468                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 469                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 470                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 471                         };
 472
 473                         /* Apalis SATA1_ACT# */
 474                         dap1_dout_pn2 {
 475                                 nvidia,pins = "dap1_dout_pn2";
 476                                 nvidia,function = "gmi";
 477                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 478                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 479                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 480                         };
 481
 482                         /* Apalis SD1 */
 483                         sdmmc3_clk_pa6 {
 484                                 nvidia,pins = "sdmmc3_clk_pa6";
 485                                 nvidia,function = "sdmmc3";
 486                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 487                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 488                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 489                         };
 490                         sdmmc3_cmd_pa7 {
 491                                 nvidia,pins = "sdmmc3_cmd_pa7";
 492                                 nvidia,function = "sdmmc3";
 493                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 494                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 495                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 496                         };
 497                         sdmmc3_dat3_pb4 {
 498                                 nvidia,pins = "sdmmc3_dat3_pb4";
 499                                 nvidia,function = "sdmmc3";
 500                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 501                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 502                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 503                         };
 504                         sdmmc3_dat2_pb5 {
 505                                 nvidia,pins = "sdmmc3_dat2_pb5";
 506                                 nvidia,function = "sdmmc3";
 507                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 508                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 509                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 510                         };
 511                         sdmmc3_dat1_pb6 {
 512                                 nvidia,pins = "sdmmc3_dat1_pb6";
 513                                 nvidia,function = "sdmmc3";
 514                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 515                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 516                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 517                         };
 518                         sdmmc3_dat0_pb7 {
 519                                 nvidia,pins = "sdmmc3_dat0_pb7";
 520                                 nvidia,function = "sdmmc3";
 521                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 522                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 523                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 524                         };
 525                         /*
 526                          * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it
 527                          * features some magic properties even though the
 528                          * external loopback is disabled and the internal
 529                          * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
 530                          * register's SDMMC_SPARE1 bits being set to 0xfffd
 531                          * according to the TRM!
 532                          */
 533                         sdmmc3_clk_lb_out_pee4 { /* CD# GPIO */
 534                                 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
 535                                 nvidia,function = "rsvd2";
 536                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 537                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 538                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 539                         };
 540
 541                         /* Apalis SPDIF */
 542                         spdif_out_pk5 {
 543                                 nvidia,pins = "spdif_out_pk5";
 544                                 nvidia,function = "spdif";
 545                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 546                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 547                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 548                         };
 549                         spdif_in_pk6 {
 550                                 nvidia,pins = "spdif_in_pk6";
 551                                 nvidia,function = "spdif";
 552                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 553                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 554                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 555                         };
 556
 557                         /* Apalis SPI1 */
 558                         ulpi_clk_py0 {
 559                                 nvidia,pins = "ulpi_clk_py0";
 560                                 nvidia,function = "spi1";
 561                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 562                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 563                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 564                         };
 565                         ulpi_dir_py1 {
 566                                 nvidia,pins = "ulpi_dir_py1";
 567                                 nvidia,function = "spi1";
 568                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 569                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 570                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 571                         };
 572                         ulpi_nxt_py2 {
 573                                 nvidia,pins = "ulpi_nxt_py2";
 574                                 nvidia,function = "spi1";
 575                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 576                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 577                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 578                         };
 579                         ulpi_stp_py3 {
 580                                 nvidia,pins = "ulpi_stp_py3";
 581                                 nvidia,function = "spi1";
 582                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 583                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 584                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 585                         };
 586
 587                         /* Apalis SPI2 */
 588                         pg5 {
 589                                 nvidia,pins = "pg5";
 590                                 nvidia,function = "spi4";
 591                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 592                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 593                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 594                         };
 595                         pg6 {
 596                                 nvidia,pins = "pg6";
 597                                 nvidia,function = "spi4";
 598                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 599                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 600                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 601                         };
 602                         pg7 {
 603                                 nvidia,pins = "pg7";
 604                                 nvidia,function = "spi4";
 605                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 606                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 607                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 608                         };
 609                         pi3 {
 610                                 nvidia,pins = "pi3";
 611                                 nvidia,function = "spi4";
 612                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 613                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 614                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 615                         };
 616
 617                         /* Apalis UART1 */
 618                         pb1 { /* DCD GPIO */
 619                                 nvidia,pins = "pb1";
 620                                 nvidia,function = "rsvd2";
 621                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 622                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 623                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 624                         };
 625                         pk7 { /* RI GPIO */
 626                                 nvidia,pins = "pk7";
 627                                 nvidia,function = "rsvd2";
 628                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 629                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 630                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 631                         };
 632                         uart1_txd_pu0 {
 633                                 nvidia,pins = "pu0";
 634                                 nvidia,function = "uarta";
 635                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 636                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 637                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 638                         };
 639                         uart1_rxd_pu1 {
 640                                 nvidia,pins = "pu1";
 641                                 nvidia,function = "uarta";
 642                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 643                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 644                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 645                         };
 646                         uart1_cts_n_pu2 {
 647                                 nvidia,pins = "pu2";
 648                                 nvidia,function = "uarta";
 649                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 650                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 651                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 652                         };
 653                         uart1_rts_n_pu3 {
 654                                 nvidia,pins = "pu3";
 655                                 nvidia,function = "uarta";
 656                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 657                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 658                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 659                         };
 660                         uart3_cts_n_pa1 { /* DSR GPIO */
 661                                 nvidia,pins = "uart3_cts_n_pa1";
 662                                 nvidia,function = "gmi";
 663                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 664                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 665                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 666                         };
 667                         uart3_rts_n_pc0 { /* DTR GPIO */
 668                                 nvidia,pins = "uart3_rts_n_pc0";
 669                                 nvidia,function = "gmi";
 670                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 671                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 672                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 673                         };
 674
 675                         /* Apalis UART2 */
 676                         uart2_txd_pc2 {
 677                                 nvidia,pins = "uart2_txd_pc2";
 678                                 nvidia,function = "irda";
 679                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 680                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 681                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 682                         };
 683                         uart2_rxd_pc3 {
 684                                 nvidia,pins = "uart2_rxd_pc3";
 685                                 nvidia,function = "irda";
 686                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 687                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 688                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 689                         };
 690                         uart2_cts_n_pj5 {
 691                                 nvidia,pins = "uart2_cts_n_pj5";
 692                                 nvidia,function = "uartb";
 693                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 694                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 695                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 696                         };
 697                         uart2_rts_n_pj6 {
 698                                 nvidia,pins = "uart2_rts_n_pj6";
 699                                 nvidia,function = "uartb";
 700                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 701                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 702                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 703                         };
 704
 705                         /* Apalis UART3 */
 706                         uart3_txd_pw6 {
 707                                 nvidia,pins = "uart3_txd_pw6";
 708                                 nvidia,function = "uartc";
 709                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 710                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 711                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 712                         };
 713                         uart3_rxd_pw7 {
 714                                 nvidia,pins = "uart3_rxd_pw7";
 715                                 nvidia,function = "uartc";
 716                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 717                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 718                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 719                         };
 720
 721                         /* Apalis UART4 */
 722                         uart4_rxd_pb0 {
 723                                 nvidia,pins = "pb0";
 724                                 nvidia,function = "uartd";
 725                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 726                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 727                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 728                         };
 729                         uart4_txd_pj7 {
 730                                 nvidia,pins = "pj7";
 731                                 nvidia,function = "uartd";
 732                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 733                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 734                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 735                         };
 736
 737                         /* Apalis USBH_EN */
 738                         usb_vbus_en1_pn5 {
 739                                 nvidia,pins = "usb_vbus_en1_pn5";
 740                                 nvidia,function = "rsvd2";
 741                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 742                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 743                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 744                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 745                         };
 746
 747                         /* Apalis USBH_OC# */
 748                         pbb0 {
 749                                 nvidia,pins = "pbb0";
 750                                 nvidia,function = "vgp6";
 751                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 752                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 753                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 754                         };
 755
 756                         /* Apalis USBO1_EN */
 757                         usb_vbus_en0_pn4 {
 758                                 nvidia,pins = "usb_vbus_en0_pn4";
 759                                 nvidia,function = "rsvd2";
 760                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 761                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 762                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 763                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 764                         };
 765
 766                         /* Apalis USBO1_OC# */
 767                         pbb4 {
 768                                 nvidia,pins = "pbb4";
 769                                 nvidia,function = "vgp4";
 770                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 771                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 772                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 773                         };
 774
 775                         /* Apalis WAKE1_MICO */
 776                         pex_wake_n_pdd3 {
 777                                 nvidia,pins = "pex_wake_n_pdd3";
 778                                 nvidia,function = "rsvd2";
 779                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 780                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 781                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 782                         };
 783
 784                         /* CORE_PWR_REQ */
 785                         core_pwr_req {
 786                                 nvidia,pins = "core_pwr_req";
 787                                 nvidia,function = "pwron";
 788                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 789                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 790                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 791                         };
 792
 793                         /* CPU_PWR_REQ */
 794                         cpu_pwr_req {
 795                                 nvidia,pins = "cpu_pwr_req";
 796                                 nvidia,function = "cpu";
 797                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 798                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 799                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 800                         };
 801
 802                         /* DVFS */
 803                         dvfs_pwm_px0 {
 804                                 nvidia,pins = "dvfs_pwm_px0";
 805                                 nvidia,function = "cldvfs";
 806                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 807                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 808                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 809                         };
 810                         dvfs_clk_px2 {
 811                                 nvidia,pins = "dvfs_clk_px2";
 812                                 nvidia,function = "cldvfs";
 813                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 814                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 815                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 816                         };
 817
 818                         /* eMMC */
 819                         sdmmc4_dat0_paa0 {
 820                                 nvidia,pins = "sdmmc4_dat0_paa0";
 821                                 nvidia,function = "sdmmc4";
 822                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 823                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 824                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 825                         };
 826                         sdmmc4_dat1_paa1 {
 827                                 nvidia,pins = "sdmmc4_dat1_paa1";
 828                                 nvidia,function = "sdmmc4";
 829                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 830                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 831                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 832                         };
 833                         sdmmc4_dat2_paa2 {
 834                                 nvidia,pins = "sdmmc4_dat2_paa2";
 835                                 nvidia,function = "sdmmc4";
 836                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 837                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 838                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 839                         };
 840                         sdmmc4_dat3_paa3 {
 841                                 nvidia,pins = "sdmmc4_dat3_paa3";
 842                                 nvidia,function = "sdmmc4";
 843                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 844                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 845                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 846                         };
 847                         sdmmc4_dat4_paa4 {
 848                                 nvidia,pins = "sdmmc4_dat4_paa4";
 849                                 nvidia,function = "sdmmc4";
 850                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 851                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 852                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 853                         };
 854                         sdmmc4_dat5_paa5 {
 855                                 nvidia,pins = "sdmmc4_dat5_paa5";
 856                                 nvidia,function = "sdmmc4";
 857                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 858                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 859                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 860                         };
 861                         sdmmc4_dat6_paa6 {
 862                                 nvidia,pins = "sdmmc4_dat6_paa6";
 863                                 nvidia,function = "sdmmc4";
 864                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 865                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 866                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 867                         };
 868                         sdmmc4_dat7_paa7 {
 869                                 nvidia,pins = "sdmmc4_dat7_paa7";
 870                                 nvidia,function = "sdmmc4";
 871                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 872                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 873                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 874                         };
 875                         sdmmc4_clk_pcc4 {
 876                                 nvidia,pins = "sdmmc4_clk_pcc4";
 877                                 nvidia,function = "sdmmc4";
 878                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 879                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 880                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 881                         };
 882                         sdmmc4_cmd_pt7 {
 883                                 nvidia,pins = "sdmmc4_cmd_pt7";
 884                                 nvidia,function = "sdmmc4";
 885                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 886                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 887                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 888                         };
 889
 890                         /* JTAG_RTCK */
 891                         jtag_rtck {
 892                                 nvidia,pins = "jtag_rtck";
 893                                 nvidia,function = "rtck";
 894                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 895                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 896                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 897                         };
 898
 899                         /* LAN_DEV_OFF# */
 900                         ulpi_data5_po6 {
 901                                 nvidia,pins = "ulpi_data5_po6";
 902                                 nvidia,function = "ulpi";
 903                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 904                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 905                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 906                         };
 907
 908                         /* LAN_RESET# */
 909                         kb_row10_ps2 {
 910                                 nvidia,pins = "kb_row10_ps2";
 911                                 nvidia,function = "rsvd2";
 912                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 913                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 914                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 915                         };
 916
 917                         /* LAN_WAKE# */
 918                         ulpi_data4_po5 {
 919                                 nvidia,pins = "ulpi_data4_po5";
 920                                 nvidia,function = "ulpi";
 921                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 922                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 923                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 924                         };
 925
 926                         /* MCU_INT1# */
 927                         pk2 {
 928                                 nvidia,pins = "pk2";
 929                                 nvidia,function = "rsvd1";
 930                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 931                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 932                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 933                         };
 934
 935                         /* MCU_INT2# */
 936                         pj2 {
 937                                 nvidia,pins = "pj2";
 938                                 nvidia,function = "rsvd1";
 939                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 940                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 941                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 942                         };
 943
 944                         /* MCU_INT3# */
 945                         pi5 {
 946                                 nvidia,pins = "pi5";
 947                                 nvidia,function = "rsvd2";
 948                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 949                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 950                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 951                         };
 952
 953                         /* MCU_INT4# */
 954                         pj0 {
 955                                 nvidia,pins = "pj0";
 956                                 nvidia,function = "rsvd1";
 957                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 958                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 959                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 960                         };
 961
 962                         /* MCU_RESET */
 963                         pbb6 {
 964                                 nvidia,pins = "pbb6";
 965                                 nvidia,function = "rsvd2";
 966                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 967                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 968                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 969                         };
 970
 971                         /* MCU SPI */
 972                         gpio_x4_aud_px4 {
 973                                 nvidia,pins = "gpio_x4_aud_px4";
 974                                 nvidia,function = "spi2";
 975                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 976                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 977                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 978                         };
 979                         gpio_x5_aud_px5 {
 980                                 nvidia,pins = "gpio_x5_aud_px5";
 981                                 nvidia,function = "spi2";
 982                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 983                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 984                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 985                         };
 986                         gpio_x6_aud_px6 { /* MCU_CS */
 987                                 nvidia,pins = "gpio_x6_aud_px6";
 988                                 nvidia,function = "spi2";
 989                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 990                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 991                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 992                         };
 993                         gpio_x7_aud_px7 {
 994                                 nvidia,pins = "gpio_x7_aud_px7";
 995                                 nvidia,function = "spi2";
 996                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 997                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 998                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 999                         };
1000                         gpio_w2_aud_pw2 { /* MCU_CSEZP */
1001                                 nvidia,pins = "gpio_w2_aud_pw2";
1002                                 nvidia,function = "spi2";
1003                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1004                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1005                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1006                         };
1007
1008                         /* PMIC_CLK_32K */
1009                         clk_32k_in {
1010                                 nvidia,pins = "clk_32k_in";
1011                                 nvidia,function = "clk";
1012                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1013                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1014                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1015                         };
1016
1017                         /* PMIC_CPU_OC_INT */
1018                         clk_32k_out_pa0 {
1019                                 nvidia,pins = "clk_32k_out_pa0";
1020                                 nvidia,function = "soc";
1021                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1022                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1023                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1024                         };
1025
1026                         /* PWR_I2C */
1027                         pwr_i2c_scl_pz6 {
1028                                 nvidia,pins = "pwr_i2c_scl_pz6";
1029                                 nvidia,function = "i2cpwr";
1030                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1031                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1032                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1033                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1034                         };
1035                         pwr_i2c_sda_pz7 {
1036                                 nvidia,pins = "pwr_i2c_sda_pz7";
1037                                 nvidia,function = "i2cpwr";
1038                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1039                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1040                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1041                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1042                         };
1043
1044                         /* PWR_INT_N */
1045                         pwr_int_n {
1046                                 nvidia,pins = "pwr_int_n";
1047                                 nvidia,function = "pmi";
1048                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1049                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1050                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1051                         };
1052
1053                         /* RESET_MOCI_CTRL */
1054                         pu4 {
1055                                 nvidia,pins = "pu4";
1056                                 nvidia,function = "gmi";
1057                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1058                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1059                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1060                         };
1061
1062                         /* RESET_OUT_N */
1063                         reset_out_n {
1064                                 nvidia,pins = "reset_out_n";
1065                                 nvidia,function = "reset_out_n";
1066                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1067                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1068                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1069                         };
1070
1071                         /* SHIFT_CTRL_DIR_IN */
1072                         kb_row0_pr0 {
1073                                 nvidia,pins = "kb_row0_pr0";
1074                                 nvidia,function = "rsvd2";
1075                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1076                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1077                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1078                         };
1079                         kb_row1_pr1 {
1080                                 nvidia,pins = "kb_row1_pr1";
1081                                 nvidia,function = "rsvd2";
1082                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1083                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1084                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1085                         };
1086
1087                         /* Configure level-shifter as output for HDA */
1088                         kb_row11_ps3 {
1089                                 nvidia,pins = "kb_row11_ps3";
1090                                 nvidia,function = "rsvd2";
1091                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1092                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1093                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1094                         };
1095
1096                         /* SHIFT_CTRL_DIR_OUT */
1097                         kb_col5_pq5 {
1098                                 nvidia,pins = "kb_col5_pq5";
1099                                 nvidia,function = "rsvd2";
1100                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1101                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1102                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1103                         };
1104                         kb_col6_pq6 {
1105                                 nvidia,pins = "kb_col6_pq6";
1106                                 nvidia,function = "rsvd2";
1107                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1108                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1109                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1110                         };
1111                         kb_col7_pq7 {
1112                                 nvidia,pins = "kb_col7_pq7";
1113                                 nvidia,function = "rsvd2";
1114                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1115                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1116                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1117                         };
1118
1119                         /* SHIFT_CTRL_OE */
1120                         kb_col0_pq0 {
1121                                 nvidia,pins = "kb_col0_pq0";
1122                                 nvidia,function = "rsvd2";
1123                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1124                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1125                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1126                         };
1127                         kb_col1_pq1 {
1128                                 nvidia,pins = "kb_col1_pq1";
1129                                 nvidia,function = "rsvd2";
1130                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1131                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1132                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1133                         };
1134                         kb_col2_pq2 {
1135                                 nvidia,pins = "kb_col2_pq2";
1136                                 nvidia,function = "rsvd2";
1137                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1138                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1139                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1140                         };
1141                         kb_col4_pq4 {
1142                                 nvidia,pins = "kb_col4_pq4";
1143                                 nvidia,function = "kbc";
1144                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1145                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1146                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1147                         };
1148                         kb_row2_pr2 {
1149                                 nvidia,pins = "kb_row2_pr2";
1150                                 nvidia,function = "rsvd2";
1151                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1152                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1153                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1154                         };
1155
1156                         /* GPIO_PI6 aka TEMP_ALERT_L */
1157                         pi6 {
1158                                 nvidia,pins = "pi6";
1159                                 nvidia,function = "rsvd1";
1160                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1161                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1162                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1163                         };
1164
1165                         /* TOUCH_INT */
1166                         gpio_w3_aud_pw3 {
1167                                 nvidia,pins = "gpio_w3_aud_pw3";
1168                                 nvidia,function = "spi6";
1169                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1170                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1171                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1172                         };
1173
1174                         pc7 { /* NC */
1175                                 nvidia,pins = "pc7";
1176                                 nvidia,function = "rsvd1";
1177                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1178                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1179                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1180                         };
1181                         pg0 { /* NC */
1182                                 nvidia,pins = "pg0";
1183                                 nvidia,function = "rsvd1";
1184                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1185                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1186                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1187                         };
1188                         pg1 { /* NC */
1189                                 nvidia,pins = "pg1";
1190                                 nvidia,function = "rsvd1";
1191                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1192                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1193                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1194                         };
1195                         pg2 { /* NC */
1196                                 nvidia,pins = "pg2";
1197                                 nvidia,function = "rsvd1";
1198                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1199                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1200                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1201                         };
1202                         pg3 { /* NC */
1203                                 nvidia,pins = "pg3";
1204                                 nvidia,function = "rsvd1";
1205                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1206                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1207                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1208                         };
1209                         pg4 { /* NC */
1210                                 nvidia,pins = "pg4";
1211                                 nvidia,function = "rsvd1";
1212                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1213                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1214                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1215                         };
1216                         ph4 { /* NC */
1217                                 nvidia,pins = "ph4";
1218                                 nvidia,function = "rsvd2";
1219                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1220                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1221                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1222                         };
1223                         ph5 { /* NC */
1224                                 nvidia,pins = "ph5";
1225                                 nvidia,function = "rsvd2";
1226                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1227                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1228                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1229                         };
1230                         ph6 { /* NC */
1231                                 nvidia,pins = "ph6";
1232                                 nvidia,function = "gmi";
1233                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1234                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1235                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1236                         };
1237                         ph7 { /* NC */
1238                                 nvidia,pins = "ph7";
1239                                 nvidia,function = "gmi";
1240                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1241                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1242                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1243                         };
1244                         pi0 { /* NC */
1245                                 nvidia,pins = "pi0";
1246                                 nvidia,function = "rsvd1";
1247                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1248                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1249                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1250                         };
1251                         pi1 { /* NC */
1252                                 nvidia,pins = "pi1";
1253                                 nvidia,function = "rsvd1";
1254                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1255                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1256                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1257                         };
1258                         pi2 { /* NC */
1259                                 nvidia,pins = "pi2";
1260                                 nvidia,function = "rsvd4";
1261                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1262                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1263                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1264                         };
1265                         pi4 { /* NC */
1266                                 nvidia,pins = "pi4";
1267                                 nvidia,function = "gmi";
1268                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1269                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1270                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1271                         };
1272                         pi7 { /* NC */
1273                                 nvidia,pins = "pi7";
1274                                 nvidia,function = "rsvd1";
1275                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1276                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1277                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1278                         };
1279                         pk0 { /* NC */
1280                                 nvidia,pins = "pk0";
1281                                 nvidia,function = "rsvd1";
1282                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1283                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1284                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1285                         };
1286                         pk1 { /* NC */
1287                                 nvidia,pins = "pk1";
1288                                 nvidia,function = "rsvd4";
1289                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1290                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1291                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1292                         };
1293                         pk3 { /* NC */
1294                                 nvidia,pins = "pk3";
1295                                 nvidia,function = "gmi";
1296                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1297                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1298                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1299                         };
1300                         pk4 { /* NC */
1301                                 nvidia,pins = "pk4";
1302                                 nvidia,function = "rsvd2";
1303                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1304                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1305                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1306                         };
1307                         dap1_fs_pn0 { /* NC */
1308                                 nvidia,pins = "dap1_fs_pn0";
1309                                 nvidia,function = "rsvd4";
1310                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1311                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1312                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1313                         };
1314                         dap1_din_pn1 { /* NC */
1315                                 nvidia,pins = "dap1_din_pn1";
1316                                 nvidia,function = "rsvd4";
1317                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1318                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1319                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1320                         };
1321                         dap1_sclk_pn3 { /* NC */
1322                                 nvidia,pins = "dap1_sclk_pn3";
1323                                 nvidia,function = "rsvd4";
1324                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1325                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1326                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1327                         };
1328                         ulpi_data7_po0 { /* NC */
1329                                 nvidia,pins = "ulpi_data7_po0";
1330                                 nvidia,function = "ulpi";
1331                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1332                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1333                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1334                         };
1335                         ulpi_data0_po1 { /* NC */
1336                                 nvidia,pins = "ulpi_data0_po1";
1337                                 nvidia,function = "ulpi";
1338                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1339                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1340                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1341                         };
1342                         ulpi_data1_po2 { /* NC */
1343                                 nvidia,pins = "ulpi_data1_po2";
1344                                 nvidia,function = "ulpi";
1345                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1346                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1347                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1348                         };
1349                         ulpi_data2_po3 { /* NC */
1350                                 nvidia,pins = "ulpi_data2_po3";
1351                                 nvidia,function = "ulpi";
1352                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1353                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1354                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1355                         };
1356                         ulpi_data3_po4 { /* NC */
1357                                 nvidia,pins = "ulpi_data3_po4";
1358                                 nvidia,function = "ulpi";
1359                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1360                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1361                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1362                         };
1363                         ulpi_data6_po7 { /* NC */
1364                                 nvidia,pins = "ulpi_data6_po7";
1365                                 nvidia,function = "ulpi";
1366                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1367                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1368                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1369                         };
1370                         dap4_fs_pp4 { /* NC */
1371                                 nvidia,pins = "dap4_fs_pp4";
1372                                 nvidia,function = "rsvd4";
1373                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1374                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1375                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1376                         };
1377                         dap4_din_pp5 { /* NC */
1378                                 nvidia,pins = "dap4_din_pp5";
1379                                 nvidia,function = "rsvd3";
1380                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1381                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1382                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1383                         };
1384                         dap4_dout_pp6 { /* NC */
1385                                 nvidia,pins = "dap4_dout_pp6";
1386                                 nvidia,function = "rsvd4";
1387                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1388                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1389                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1390                         };
1391                         dap4_sclk_pp7 { /* NC */
1392                                 nvidia,pins = "dap4_sclk_pp7";
1393                                 nvidia,function = "rsvd3";
1394                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1395                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1396                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1397                         };
1398                         kb_col3_pq3 { /* NC */
1399                                 nvidia,pins = "kb_col3_pq3";
1400                                 nvidia,function = "kbc";
1401                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1402                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1403                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1404                         };
1405                         kb_row3_pr3 { /* NC */
1406                                 nvidia,pins = "kb_row3_pr3";
1407                                 nvidia,function = "kbc";
1408                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1409                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1410                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1411                         };
1412                         kb_row4_pr4 { /* NC */
1413                                 nvidia,pins = "kb_row4_pr4";
1414                                 nvidia,function = "rsvd3";
1415                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1416                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1417                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1418                         };
1419                         kb_row5_pr5 { /* NC */
1420                                 nvidia,pins = "kb_row5_pr5";
1421                                 nvidia,function = "rsvd3";
1422                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1423                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1424                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1425                         };
1426                         kb_row6_pr6 { /* NC */
1427                                 nvidia,pins = "kb_row6_pr6";
1428                                 nvidia,function = "kbc";
1429                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1430                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1431                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1432                         };
1433                         kb_row7_pr7 { /* NC */
1434                                 nvidia,pins = "kb_row7_pr7";
1435                                 nvidia,function = "rsvd2";
1436                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1437                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1438                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1439                         };
1440                         kb_row8_ps0 { /* NC */
1441                                 nvidia,pins = "kb_row8_ps0";
1442                                 nvidia,function = "rsvd2";
1443                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1444                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1445                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1446                         };
1447                         kb_row9_ps1 { /* NC */
1448                                 nvidia,pins = "kb_row9_ps1";
1449                                 nvidia,function = "rsvd2";
1450                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1451                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1452                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1453                         };
1454                         kb_row12_ps4 { /* NC */
1455                                 nvidia,pins = "kb_row12_ps4";
1456                                 nvidia,function = "rsvd2";
1457                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1458                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1459                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1460                         };
1461                         kb_row13_ps5 { /* NC */
1462                                 nvidia,pins = "kb_row13_ps5";
1463                                 nvidia,function = "rsvd2";
1464                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1465                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1466                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1467                         };
1468                         kb_row14_ps6 { /* NC */
1469                                 nvidia,pins = "kb_row14_ps6";
1470                                 nvidia,function = "rsvd2";
1471                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1472                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1473                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1474                         };
1475                         kb_row15_ps7 { /* NC */
1476                                 nvidia,pins = "kb_row15_ps7";
1477                                 nvidia,function = "rsvd3";
1478                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1479                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1480                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1481                         };
1482                         kb_row16_pt0 { /* NC */
1483                                 nvidia,pins = "kb_row16_pt0";
1484                                 nvidia,function = "rsvd2";
1485                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1486                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1487                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1488                         };
1489                         kb_row17_pt1 { /* NC */
1490                                 nvidia,pins = "kb_row17_pt1";
1491                                 nvidia,function = "rsvd2";
1492                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1493                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1494                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1495                         };
1496                         pu5 { /* NC */
1497                                 nvidia,pins = "pu5";
1498                                 nvidia,function = "gmi";
1499                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1500                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1501                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1502                         };
1503                         pv0 { /* NC */
1504                                 nvidia,pins = "pv0";
1505                                 nvidia,function = "rsvd1";
1506                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1507                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1508                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1509                         };
1510                         pv1 { /* NC */
1511                                 nvidia,pins = "pv1";
1512                                 nvidia,function = "rsvd1";
1513                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1514                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1515                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1516                         };
1517                         sdmmc3_cd_n_pv2 { /* NC */
1518                                 nvidia,pins = "sdmmc3_cd_n_pv2";
1519                                 nvidia,function = "rsvd3";
1520                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1521                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1522                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1523                         };
1524                         gpio_x1_aud_px1 { /* NC */
1525                                 nvidia,pins = "gpio_x1_aud_px1";
1526                                 nvidia,function = "rsvd2";
1527                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1528                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1529                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1530                         };
1531                         gpio_x3_aud_px3 { /* NC */
1532                                 nvidia,pins = "gpio_x3_aud_px3";
1533                                 nvidia,function = "rsvd4";
1534                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1535                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1536                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1537                         };
1538                         pbb7 { /* NC */
1539                                 nvidia,pins = "pbb7";
1540                                 nvidia,function = "rsvd2";
1541                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1542                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1543                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1544                         };
1545                         pcc1 { /* NC */
1546                                 nvidia,pins = "pcc1";
1547                                 nvidia,function = "rsvd2";
1548                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1549                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1550                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1551                         };
1552                         pcc2 { /* NC */
1553                                 nvidia,pins = "pcc2";
1554                                 nvidia,function = "rsvd2";
1555                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1556                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1557                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1558                         };
1559                         clk3_req_pee1 { /* NC */
1560                                 nvidia,pins = "clk3_req_pee1";
1561                                 nvidia,function = "rsvd2";
1562                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1563                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1564                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1565                         };
1566                         dap_mclk1_req_pee2 { /* NC */
1567                                 nvidia,pins = "dap_mclk1_req_pee2";
1568                                 nvidia,function = "rsvd4";
1569                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1570                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1571                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1572                         };
1573                 };
1574         };
1575
1576         serial@70006040 {
1577                 compatible = "nvidia,tegra124-hsuart";
1578         };
1579
1580         serial@70006200 {
1581                 compatible = "nvidia,tegra124-hsuart";
1582         };
1583
1584         serial@70006300 {
1585                 compatible = "nvidia,tegra124-hsuart";
1586         };
1587
1588         hdmi_ddc: i2c@7000c400 {
1589                 clock-frequency = <100000>;
1590         };
1591
1592         /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
1593         i2c@7000d000 {
1594                 status = "okay";
1595                 clock-frequency = <400000>;
1596
1597                 /* SGTL5000 audio codec */
1598                 sgtl5000: codec@0a {
1599                         compatible = "fsl,sgtl5000";
1600                         reg = <0x0a>;
1601                         VDDA-supply = <&reg_3v3>;
1602                         VDDIO-supply = <&vddio_1v8>;
1603                         clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
1604                 };
1605
1606                 pmic: pmic@40 {
1607                         compatible = "ams,as3722";
1608                         reg = <0x40>;
1609                         interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
1610
1611                         ams,system-power-controller;
1612
1613                         #interrupt-cells = <2>;
1614                         interrupt-controller;
1615
1616                         gpio-controller;
1617                         #gpio-cells = <2>;
1618
1619                         pinctrl-names = "default";
1620                         pinctrl-0 = <&as3722_default>;
1621
1622                         as3722_default: pinmux {
1623                                 gpio2_7 {
1624                                         pins = "gpio2", /* PWR_EN_+V3.3 */
1625                                                "gpio7"; /* +V1.6_LPO */
1626                                         function = "gpio";
1627                                         bias-pull-up;
1628                                 };
1629
1630                                 gpio1_3_4_5_6 {
1631                                         pins = "gpio1", "gpio3", "gpio4",
1632                                                "gpio5", "gpio6";
1633                                         bias-high-impedance;
1634                                 };
1635                         };
1636
1637                         regulators {
1638                                 vsup-sd2-supply = <&reg_3v3>;
1639                                 vsup-sd3-supply = <&reg_3v3>;
1640                                 vsup-sd4-supply = <&reg_3v3>;
1641                                 vsup-sd5-supply = <&reg_3v3>;
1642                                 vin-ldo0-supply = <&vddio_ddr_1v35>;
1643                                 vin-ldo1-6-supply = <&reg_3v3>;
1644                                 vin-ldo2-5-7-supply = <&vddio_1v8>;
1645                                 vin-ldo3-4-supply = <&reg_3v3>;
1646                                 vin-ldo9-10-supply = <&reg_3v3>;
1647                                 vin-ldo11-supply = <&reg_3v3>;
1648
1649                                 vdd_cpu: sd0 {
1650                                         regulator-name = "+VDD_CPU_AP";
1651                                         regulator-min-microvolt = <700000>;
1652                                         regulator-max-microvolt = <1400000>;
1653                                         regulator-min-microamp = <3500000>;
1654                                         regulator-max-microamp = <3500000>;
1655                                         regulator-always-on;
1656                                         regulator-boot-on;
1657                                         ams,ext-control = <2>;
1658                                 };
1659
1660                                 sd1 {
1661                                         regulator-name = "+VDD_CORE";
1662                                         regulator-min-microvolt = <700000>;
1663                                         regulator-max-microvolt = <1350000>;
1664                                         regulator-min-microamp = <2500000>;
1665                                         regulator-max-microamp = <4000000>;
1666                                         regulator-always-on;
1667                                         regulator-boot-on;
1668                                         ams,ext-control = <1>;
1669                                 };
1670
1671                                 vddio_ddr_1v35: sd2 {
1672                                         regulator-name =
1673                                                 "+V1.35_VDDIO_DDR(sd2)";
1674                                         regulator-min-microvolt = <1350000>;
1675                                         regulator-max-microvolt = <1350000>;
1676                                         regulator-always-on;
1677                                         regulator-boot-on;
1678                                 };
1679
1680                                 sd3 {
1681                                         regulator-name =
1682                                                 "+V1.35_VDDIO_DDR(sd3)";
1683                                         regulator-min-microvolt = <1350000>;
1684                                         regulator-max-microvolt = <1350000>;
1685                                         regulator-always-on;
1686                                         regulator-boot-on;
1687                                 };
1688
1689                                 vdd_1v05: sd4 {
1690                                         regulator-name = "+V1.05";
1691                                         regulator-min-microvolt = <1050000>;
1692                                         regulator-max-microvolt = <1050000>;
1693                                 };
1694
1695                                 vddio_1v8: sd5 {
1696                                         regulator-name = "+V1.8";
1697                                         regulator-min-microvolt = <1800000>;
1698                                         regulator-max-microvolt = <1800000>;
1699                                         regulator-boot-on;
1700                                         regulator-always-on;
1701                                 };
1702
1703                                 vdd_gpu: sd6 {
1704                                         regulator-name = "+VDD_GPU_AP";
1705                                         regulator-min-microvolt = <650000>;
1706                                         regulator-max-microvolt = <1200000>;
1707                                         regulator-min-microamp = <3500000>;
1708                                         regulator-max-microamp = <3500000>;
1709                                         regulator-boot-on;
1710                                         regulator-always-on;
1711                                 };
1712
1713                                 avdd_1v05: ldo0 {
1714                                         regulator-name = "+V1.05_AVDD";
1715                                         regulator-min-microvolt = <1050000>;
1716                                         regulator-max-microvolt = <1050000>;
1717                                         regulator-boot-on;
1718                                         regulator-always-on;
1719                                         ams,ext-control = <1>;
1720                                 };
1721
1722                                 vddio_sdmmc1: ldo1 {
1723                                         regulator-name = "VDDIO_SDMMC1";
1724                                         regulator-min-microvolt = <1800000>;
1725                                         regulator-max-microvolt = <3300000>;
1726                                 };
1727
1728                                 ldo2 {
1729                                         regulator-name = "+V1.2";
1730                                         regulator-min-microvolt = <1200000>;
1731                                         regulator-max-microvolt = <1200000>;
1732                                         regulator-boot-on;
1733                                         regulator-always-on;
1734                                 };
1735
1736                                 ldo3 {
1737                                         regulator-name = "+V1.05_RTC";
1738                                         regulator-min-microvolt = <1000000>;
1739                                         regulator-max-microvolt = <1000000>;
1740                                         regulator-boot-on;
1741                                         regulator-always-on;
1742                                         ams,enable-tracking;
1743                                 };
1744
1745                                 /* 1.8V for LVDS, 3.3V for eDP */
1746                                 ldo4 {
1747                                         regulator-name = "AVDD_LVDS0_PLL";
1748                                         regulator-min-microvolt = <1800000>;
1749                                         regulator-max-microvolt = <1800000>;
1750                                 };
1751
1752                                 /* LDO5 not used */
1753
1754                                 vddio_sdmmc3: ldo6 {
1755                                         regulator-name = "VDDIO_SDMMC3";
1756                                         regulator-min-microvolt = <1800000>;
1757                                         regulator-max-microvolt = <3300000>;
1758                                 };
1759
1760                                 /* LDO7 not used */
1761
1762                                 ldo9 {
1763                                         regulator-name = "+V3.3_ETH(ldo9)";
1764                                         regulator-min-microvolt = <3300000>;
1765                                         regulator-max-microvolt = <3300000>;
1766                                         regulator-always-on;
1767                                 };
1768
1769                                 ldo10 {
1770                                         regulator-name = "+V3.3_ETH(ldo10)";
1771                                         regulator-min-microvolt = <3300000>;
1772                                         regulator-max-microvolt = <3300000>;
1773                                         regulator-always-on;
1774                                 };
1775
1776                                 ldo11 {
1777                                         regulator-name = "+V1.8_VPP_FUSE";
1778                                         regulator-min-microvolt = <1800000>;
1779                                         regulator-max-microvolt = <1800000>;
1780                                 };
1781                         };
1782                 };
1783
1784                 /*
1785                  * TMP451 temperature sensor
1786                  * Note: THERM_N directly connected to AS3722 PMIC THERM
1787                  */
1788                 temperature-sensor@4c {
1789                         compatible = "ti,tmp451";
1790                         reg = <0x4c>;
1791                         interrupt-parent = <&gpio>;
1792                         interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1793
1794                         #thermal-sensor-cells = <1>;
1795                 };
1796         };
1797
1798         /* SPI2: MCU SPI */
1799         spi@7000d600 {
1800                 status = "okay";
1801                 spi-max-frequency = <25000000>;
1802         };
1803
1804         pmc@7000e400 {
1805                 nvidia,invert-interrupt;
1806                 nvidia,suspend-mode = <1>;
1807                 nvidia,cpu-pwr-good-time = <500>;
1808                 nvidia,cpu-pwr-off-time = <300>;
1809                 nvidia,core-pwr-good-time = <641 3845>;
1810                 nvidia,core-pwr-off-time = <61036>;
1811                 nvidia,core-power-req-active-high;
1812                 nvidia,sys-clock-req-active-high;
1813
1814                 /* Set power_off bit in ResetControl register of AS3722 PMIC */
1815                 i2c-thermtrip {
1816                         nvidia,i2c-controller-id = <4>;
1817                         nvidia,bus-addr = <0x40>;
1818                         nvidia,reg-addr = <0x36>;
1819                         nvidia,reg-data = <0x2>;
1820                 };
1821         };
1822
1823         sata@70020000 {
1824                 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
1825                 phy-names = "sata-0";
1826
1827                 avdd-supply = <&vdd_1v05>;
1828                 hvdd-supply = <&reg_3v3>;
1829                 vddio-supply = <&vdd_1v05>;
1830         };
1831
1832         usb@70090000 {
1833                 /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
1834                 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
1835                        <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
1836                        <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
1837                        <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
1838                        <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
1839                 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
1840
1841                 avddio-pex-supply = <&vdd_1v05>;
1842                 avdd-pll-erefe-supply = <&avdd_1v05>;
1843                 avdd-pll-utmip-supply = <&vddio_1v8>;
1844                 avdd-usb-ss-pll-supply = <&vdd_1v05>;
1845                 avdd-usb-supply = <&reg_3v3>;
1846                 dvddio-pex-supply = <&vdd_1v05>;
1847                 hvdd-usb-ss-pll-e-supply = <&reg_3v3>;
1848                 hvdd-usb-ss-supply = <&reg_3v3>;
1849         };
1850
1851         padctl@7009f000 {
1852                 pads {
1853                         usb2 {
1854                                 status = "okay";
1855
1856                                 lanes {
1857                                         usb2-0 {
1858                                                 nvidia,function = "xusb";
1859                                                 status = "okay";
1860                                         };
1861
1862                                         usb2-1 {
1863                                                 nvidia,function = "xusb";
1864                                                 status = "okay";
1865                                         };
1866
1867                                         usb2-2 {
1868                                                 nvidia,function = "xusb";
1869                                                 status = "okay";
1870                                         };
1871                                 };
1872                         };
1873
1874                         pcie {
1875                                 status = "okay";
1876
1877                                 lanes {
1878                                         pcie-0 {
1879                                                 nvidia,function = "usb3-ss";
1880                                                 status = "okay";
1881                                         };
1882
1883                                         pcie-1 {
1884                                                 nvidia,function = "usb3-ss";
1885                                                 status = "okay";
1886                                         };
1887
1888                                         pcie-2 {
1889                                                 nvidia,function = "pcie";
1890                                                 status = "okay";
1891                                         };
1892
1893                                         pcie-3 {
1894                                                 nvidia,function = "pcie";
1895                                                 status = "okay";
1896                                         };
1897
1898                                         pcie-4 {
1899                                                 nvidia,function = "pcie";
1900                                                 status = "okay";
1901                                         };
1902                                 };
1903                         };
1904
1905                         sata {
1906                                 status = "okay";
1907
1908                                 lanes {
1909                                         sata-0 {
1910                                                 nvidia,function = "sata";
1911                                                 status = "okay";
1912                                         };
1913                                 };
1914                         };
1915                 };
1916
1917                 ports {
1918                         /* USBO1 */
1919                         usb2-0 {
1920                                 status = "okay";
1921                                 mode = "otg";
1922
1923                                 vbus-supply = <&reg_usbo1_vbus>;
1924                         };
1925
1926                         /* USBH2 */
1927                         usb2-1 {
1928                                 status = "okay";
1929                                 mode = "host";
1930
1931                                 vbus-supply = <&reg_usbh_vbus>;
1932                         };
1933
1934                         /* USBH4 */
1935                         usb2-2 {
1936                                 status = "okay";
1937                                 mode = "host";
1938
1939                                 vbus-supply = <&reg_usbh_vbus>;
1940                         };
1941
1942                         usb3-0 {
1943                                 nvidia,usb2-companion = <2>;
1944                                 status = "okay";
1945                         };
1946
1947                         usb3-1 {
1948                                 nvidia,usb2-companion = <0>;
1949                                 status = "okay";
1950                         };
1951                 };
1952         };
1953
1954         /* eMMC */
1955         sdhci@700b0600 {
1956                 status = "okay";
1957                 bus-width = <8>;
1958                 non-removable;
1959         };
1960
1961         /* CPU DFLL clock */
1962         clock@70110000 {
1963                 status = "okay";
1964                 vdd-cpu-supply = <&vdd_cpu>;
1965                 nvidia,i2c-fs-rate = <400000>;
1966         };
1967
1968         ahub@70300000 {
1969                 i2s@70301200 {
1970                         status = "okay";
1971                 };
1972         };
1973
1974         clocks {
1975                 compatible = "simple-bus";
1976                 #address-cells = <1>;
1977                 #size-cells = <0>;
1978
1979                 clk32k_in: clock@0 {
1980                         compatible = "fixed-clock";
1981                         reg = <0>;
1982                         #clock-cells = <0>;
1983                         clock-frequency = <32768>;
1984                 };
1985         };
1986
1987         cpus {
1988                 cpu@0 {
1989                         vdd-cpu-supply = <&vdd_cpu>;
1990                 };
1991         };
1992
1993         reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
1994                 compatible = "regulator-fixed";
1995                 regulator-name = "+V1.05_AVDD_HDMI_PLL";
1996                 regulator-min-microvolt = <1050000>;
1997                 regulator-max-microvolt = <1050000>;
1998                 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1999                 vin-supply = <&vdd_1v05>;
2000         };
2001
2002         reg_3v3_mxm: regulator-3v3-mxm {
2003                 compatible = "regulator-fixed";
2004                 regulator-name = "+V3.3_MXM";
2005                 regulator-min-microvolt = <3300000>;
2006                 regulator-max-microvolt = <3300000>;
2007                 regulator-always-on;
2008                 regulator-boot-on;
2009         };
2010
2011         reg_3v3: regulator-3v3 {
2012                 compatible = "regulator-fixed";
2013                 regulator-name = "+V3.3";
2014                 regulator-min-microvolt = <3300000>;
2015                 regulator-max-microvolt = <3300000>;
2016                 regulator-always-on;
2017                 regulator-boot-on;
2018                 /* PWR_EN_+V3.3 */
2019                 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
2020                 enable-active-high;
2021                 vin-supply = <&reg_3v3_mxm>;
2022         };
2023
2024         reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
2025                 compatible = "regulator-fixed";
2026                 regulator-name = "+V3.3_AVDD_HDMI";
2027                 regulator-min-microvolt = <3300000>;
2028                 regulator-max-microvolt = <3300000>;
2029                 vin-supply = <&vdd_1v05>;
2030         };
2031
2032         sound {
2033                 compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
2034                              "nvidia,tegra-audio-sgtl5000";
2035                 nvidia,model = "Toradex Apalis TK1";
2036                 nvidia,audio-routing =
2037                         "Headphone Jack", "HP_OUT",
2038                         "LINE_IN", "Line In Jack",
2039                         "MIC_IN", "Mic Jack";
2040                 nvidia,i2s-controller = <&tegra_i2s2>;
2041                 nvidia,audio-codec = <&sgtl5000>;
2042                 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
2043                          <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
2044                          <&tegra_car TEGRA124_CLK_EXTERN1>;
2045                 clock-names = "pll_a", "pll_a_out0", "mclk";
2046         };
2047
2048         thermal-zones {
2049                 cpu {
2050                         trips {
2051                                 trip@0 {
2052                                         temperature = <101000>;
2053                                         hysteresis = <0>;
2054                                         type = "critical";
2055                                 };
2056                         };
2057
2058                         cooling-maps {
2059                                 /*
2060                                  * There are currently no cooling maps because
2061                                  * there are no cooling devices
2062                                  */
2063                         };
2064                 };
2065
2066                 mem {
2067                         trips {
2068                                 trip@0 {
2069                                         temperature = <101000>;
2070                                         hysteresis = <0>;
2071                                         type = "critical";
2072                                 };
2073                         };
2074
2075                         cooling-maps {
2076                                 /*
2077                                  * There are currently no cooling maps because
2078                                  * there are no cooling devices
2079                                  */
2080                         };
2081                 };
2082
2083                 gpu {
2084                         trips {
2085                                 trip@0 {
2086                                         temperature = <101000>;
2087                                         hysteresis = <0>;
2088                                         type = "critical";
2089                                 };
2090                         };
2091
2092                         cooling-maps {
2093                                 /*
2094                                  * There are currently no cooling maps because
2095                                  * there are no cooling devices
2096                                  */
2097                         };
2098                 };
2099         };
2100 };