arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/memory/tegra124-mc.h>
   4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/thermal/tegra124-soctherm.h>
   8
   9 #include "skeleton.dtsi"
  10
  11 / {
  12         compatible = "nvidia,tegra124";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         pcie-controller@0,01003000 {
  18                 compatible = "nvidia,tegra124-pcie";
  19                 device_type = "pci";
  20                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  21                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  22                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  23                 reg-names = "pads", "afi", "cs";
  24                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  25                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  26                 interrupt-names = "intr", "msi";
  27
  28                 #interrupt-cells = <1>;
  29                 interrupt-map-mask = <0 0 0 0>;
  30                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  31
  32                 bus-range = <0x00 0xff>;
  33                 #address-cells = <3>;
  34                 #size-cells = <2>;
  35
  36                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  37                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  38                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  39                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  40                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  41
  42                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  43                          <&tegra_car TEGRA124_CLK_AFI>,
  44                          <&tegra_car TEGRA124_CLK_PLL_E>,
  45                          <&tegra_car TEGRA124_CLK_CML0>;
  46                 clock-names = "pex", "afi", "pll_e", "cml";
  47                 resets = <&tegra_car 70>,
  48                          <&tegra_car 72>,
  49                          <&tegra_car 74>;
  50                 reset-names = "pex", "afi", "pcie_x";
  51                 status = "disabled";
  52
  53                 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
  54                 phy-names = "pcie";
  55
  56                 pci@1,0 {
  57                         device_type = "pci";
  58                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  59                         reg = <0x000800 0 0 0 0>;
  60                         status = "disabled";
  61
  62                         #address-cells = <3>;
  63                         #size-cells = <2>;
  64                         ranges;
  65
  66                         nvidia,num-lanes = <2>;
  67                 };
  68
  69                 pci@2,0 {
  70                         device_type = "pci";
  71                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  72                         reg = <0x001000 0 0 0 0>;
  73                         status = "disabled";
  74
  75                         #address-cells = <3>;
  76                         #size-cells = <2>;
  77                         ranges;
  78
  79                         nvidia,num-lanes = <1>;
  80                 };
  81         };
  82
  83         host1x@0,50000000 {
  84                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  85                 reg = <0x0 0x50000000 0x0 0x00034000>;
  86                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  87                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  88                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  89                 resets = <&tegra_car 28>;
  90                 reset-names = "host1x";
  91
  92                 #address-cells = <2>;
  93                 #size-cells = <2>;
  94
  95                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  96
  97                 dc@0,54200000 {
  98                         compatible = "nvidia,tegra124-dc";
  99                         reg = <0x0 0x54200000 0x0 0x00040000>;
 100                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 101                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
 102                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 103                         clock-names = "dc", "parent";
 104                         resets = <&tegra_car 27>;
 105                         reset-names = "dc";
 106
 107                         iommus = <&mc TEGRA_SWGROUP_DC>;
 108
 109                         nvidia,head = <0>;
 110                 };
 111
 112                 dc@0,54240000 {
 113                         compatible = "nvidia,tegra124-dc";
 114                         reg = <0x0 0x54240000 0x0 0x00040000>;
 115                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 116                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
 117                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 118                         clock-names = "dc", "parent";
 119                         resets = <&tegra_car 26>;
 120                         reset-names = "dc";
 121
 122                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 123
 124                         nvidia,head = <1>;
 125                 };
 126
 127                 hdmi@0,54280000 {
 128                         compatible = "nvidia,tegra124-hdmi";
 129                         reg = <0x0 0x54280000 0x0 0x00040000>;
 130                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 131                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
 132                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
 133                         clock-names = "hdmi", "parent";
 134                         resets = <&tegra_car 51>;
 135                         reset-names = "hdmi";
 136                         status = "disabled";
 137                 };
 138
 139                 sor@0,54540000 {
 140                         compatible = "nvidia,tegra124-sor";
 141                         reg = <0x0 0x54540000 0x0 0x00040000>;
 142                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 143                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
 144                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
 145                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
 146                                  <&tegra_car TEGRA124_CLK_CLK_M>;
 147                         clock-names = "sor", "parent", "dp", "safe";
 148                         resets = <&tegra_car 182>;
 149                         reset-names = "sor";
 150                         status = "disabled";
 151                 };
 152
 153                 dpaux: dpaux@0,545c0000 {
 154                         compatible = "nvidia,tegra124-dpaux";
 155                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 156                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 157                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
 158                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
 159                         clock-names = "dpaux", "parent";
 160                         resets = <&tegra_car 181>;
 161                         reset-names = "dpaux";
 162                         status = "disabled";
 163                 };
 164         };
 165
 166         gic: interrupt-controller@0,50041000 {
 167                 compatible = "arm,cortex-a15-gic";
 168                 #interrupt-cells = <3>;
 169                 interrupt-controller;
 170                 reg = <0x0 0x50041000 0x0 0x1000>,
 171                       <0x0 0x50042000 0x0 0x1000>,
 172                       <0x0 0x50044000 0x0 0x2000>,
 173                       <0x0 0x50046000 0x0 0x2000>;
 174                 interrupts = <GIC_PPI 9
 175                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 176         };
 177
 178         gpu@0,57000000 {
 179                 compatible = "nvidia,gk20a";
 180                 reg = <0x0 0x57000000 0x0 0x01000000>,
 181                       <0x0 0x58000000 0x0 0x01000000>;
 182                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 184                 interrupt-names = "stall", "nonstall";
 185                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 186                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 187                 clock-names = "gpu", "pwr";
 188                 resets = <&tegra_car 184>;
 189                 reset-names = "gpu";
 190                 status = "disabled";
 191         };
 192
 193         timer@0,60005000 {
 194                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 195                 reg = <0x0 0x60005000 0x0 0x400>;
 196                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 201                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 203         };
 204
 205         tegra_car: clock@0,60006000 {
 206                 compatible = "nvidia,tegra124-car";
 207                 reg = <0x0 0x60006000 0x0 0x1000>;
 208                 #clock-cells = <1>;
 209                 #reset-cells = <1>;
 210         };
 211
 212         flow-controller@0,60007000 {
 213                 compatible = "nvidia,tegra124-flowctrl";
 214                 reg = <0x0 0x60007000 0x0 0x1000>;
 215         };
 216
 217         gpio: gpio@0,6000d000 {
 218                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 219                 reg = <0x0 0x6000d000 0x0 0x1000>;
 220                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 223                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 224                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 225                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 226                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 227                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 228                 #gpio-cells = <2>;
 229                 gpio-controller;
 230                 #interrupt-cells = <2>;
 231                 interrupt-controller;
 232         };
 233
 234         apbdma: dma@0,60020000 {
 235                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 236                 reg = <0x0 0x60020000 0x0 0x1400>;
 237                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 241                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 243                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 244                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 245                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 246                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 247                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 248                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 249                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 250                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 251                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 252                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 253                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 270                 resets = <&tegra_car 34>;
 271                 reset-names = "dma";
 272                 #dma-cells = <1>;
 273         };
 274
 275         apbmisc@0,70000800 {
 276                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 277                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 278                       <0x0 0x7000E864 0x0 0x04>;   /* Strapping options */
 279         };
 280
 281         pinmux: pinmux@0,70000868 {
 282                 compatible = "nvidia,tegra124-pinmux";
 283                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 284                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
 285                       <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
 286         };
 287
 288         /*
 289          * There are two serial driver i.e. 8250 based simple serial
 290          * driver and APB DMA based serial driver for higher baudrate
 291          * and performace. To enable the 8250 based driver, the compatible
 292          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 293          * the APB DMA based serial driver, the comptible is
 294          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 295          */
 296         uarta: serial@0,70006000 {
 297                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 298                 reg = <0x0 0x70006000 0x0 0x40>;
 299                 reg-shift = <2>;
 300                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 301                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 302                 resets = <&tegra_car 6>;
 303                 reset-names = "serial";
 304                 dmas = <&apbdma 8>, <&apbdma 8>;
 305                 dma-names = "rx", "tx";
 306                 status = "disabled";
 307         };
 308
 309         uartb: serial@0,70006040 {
 310                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 311                 reg = <0x0 0x70006040 0x0 0x40>;
 312                 reg-shift = <2>;
 313                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 314                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 315                 resets = <&tegra_car 7>;
 316                 reset-names = "serial";
 317                 dmas = <&apbdma 9>, <&apbdma 9>;
 318                 dma-names = "rx", "tx";
 319                 status = "disabled";
 320         };
 321
 322         uartc: serial@0,70006200 {
 323                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 324                 reg = <0x0 0x70006200 0x0 0x40>;
 325                 reg-shift = <2>;
 326                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 327                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 328                 resets = <&tegra_car 55>;
 329                 reset-names = "serial";
 330                 dmas = <&apbdma 10>, <&apbdma 10>;
 331                 dma-names = "rx", "tx";
 332                 status = "disabled";
 333         };
 334
 335         uartd: serial@0,70006300 {
 336                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 337                 reg = <0x0 0x70006300 0x0 0x40>;
 338                 reg-shift = <2>;
 339                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 341                 resets = <&tegra_car 65>;
 342                 reset-names = "serial";
 343                 dmas = <&apbdma 19>, <&apbdma 19>;
 344                 dma-names = "rx", "tx";
 345                 status = "disabled";
 346         };
 347
 348         pwm: pwm@0,7000a000 {
 349                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 350                 reg = <0x0 0x7000a000 0x0 0x100>;
 351                 #pwm-cells = <2>;
 352                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 353                 resets = <&tegra_car 17>;
 354                 reset-names = "pwm";
 355                 status = "disabled";
 356         };
 357
 358         i2c@0,7000c000 {
 359                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 360                 reg = <0x0 0x7000c000 0x0 0x100>;
 361                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 365                 clock-names = "div-clk";
 366                 resets = <&tegra_car 12>;
 367                 reset-names = "i2c";
 368                 dmas = <&apbdma 21>, <&apbdma 21>;
 369                 dma-names = "rx", "tx";
 370                 status = "disabled";
 371         };
 372
 373         i2c@0,7000c400 {
 374                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 375                 reg = <0x0 0x7000c400 0x0 0x100>;
 376                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 377                 #address-cells = <1>;
 378                 #size-cells = <0>;
 379                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 380                 clock-names = "div-clk";
 381                 resets = <&tegra_car 54>;
 382                 reset-names = "i2c";
 383                 dmas = <&apbdma 22>, <&apbdma 22>;
 384                 dma-names = "rx", "tx";
 385                 status = "disabled";
 386         };
 387
 388         i2c@0,7000c500 {
 389                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 390                 reg = <0x0 0x7000c500 0x0 0x100>;
 391                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 395                 clock-names = "div-clk";
 396                 resets = <&tegra_car 67>;
 397                 reset-names = "i2c";
 398                 dmas = <&apbdma 23>, <&apbdma 23>;
 399                 dma-names = "rx", "tx";
 400                 status = "disabled";
 401         };
 402
 403         i2c@0,7000c700 {
 404                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 405                 reg = <0x0 0x7000c700 0x0 0x100>;
 406                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 410                 clock-names = "div-clk";
 411                 resets = <&tegra_car 103>;
 412                 reset-names = "i2c";
 413                 dmas = <&apbdma 26>, <&apbdma 26>;
 414                 dma-names = "rx", "tx";
 415                 status = "disabled";
 416         };
 417
 418         i2c@0,7000d000 {
 419                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 420                 reg = <0x0 0x7000d000 0x0 0x100>;
 421                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 422                 #address-cells = <1>;
 423                 #size-cells = <0>;
 424                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 425                 clock-names = "div-clk";
 426                 resets = <&tegra_car 47>;
 427                 reset-names = "i2c";
 428                 dmas = <&apbdma 24>, <&apbdma 24>;
 429                 dma-names = "rx", "tx";
 430                 status = "disabled";
 431         };
 432
 433         i2c@0,7000d100 {
 434                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 435                 reg = <0x0 0x7000d100 0x0 0x100>;
 436                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 440                 clock-names = "div-clk";
 441                 resets = <&tegra_car 166>;
 442                 reset-names = "i2c";
 443                 dmas = <&apbdma 30>, <&apbdma 30>;
 444                 dma-names = "rx", "tx";
 445                 status = "disabled";
 446         };
 447
 448         spi@0,7000d400 {
 449                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 450                 reg = <0x0 0x7000d400 0x0 0x200>;
 451                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 452                 #address-cells = <1>;
 453                 #size-cells = <0>;
 454                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 455                 clock-names = "spi";
 456                 resets = <&tegra_car 41>;
 457                 reset-names = "spi";
 458                 dmas = <&apbdma 15>, <&apbdma 15>;
 459                 dma-names = "rx", "tx";
 460                 status = "disabled";
 461         };
 462
 463         spi@0,7000d600 {
 464                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 465                 reg = <0x0 0x7000d600 0x0 0x200>;
 466                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 467                 #address-cells = <1>;
 468                 #size-cells = <0>;
 469                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 470                 clock-names = "spi";
 471                 resets = <&tegra_car 44>;
 472                 reset-names = "spi";
 473                 dmas = <&apbdma 16>, <&apbdma 16>;
 474                 dma-names = "rx", "tx";
 475                 status = "disabled";
 476         };
 477
 478         spi@0,7000d800 {
 479                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 480                 reg = <0x0 0x7000d800 0x0 0x200>;
 481                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 482                 #address-cells = <1>;
 483                 #size-cells = <0>;
 484                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 485                 clock-names = "spi";
 486                 resets = <&tegra_car 46>;
 487                 reset-names = "spi";
 488                 dmas = <&apbdma 17>, <&apbdma 17>;
 489                 dma-names = "rx", "tx";
 490                 status = "disabled";
 491         };
 492
 493         spi@0,7000da00 {
 494                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 495                 reg = <0x0 0x7000da00 0x0 0x200>;
 496                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 497                 #address-cells = <1>;
 498                 #size-cells = <0>;
 499                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 500                 clock-names = "spi";
 501                 resets = <&tegra_car 68>;
 502                 reset-names = "spi";
 503                 dmas = <&apbdma 18>, <&apbdma 18>;
 504                 dma-names = "rx", "tx";
 505                 status = "disabled";
 506         };
 507
 508         spi@0,7000dc00 {
 509                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 510                 reg = <0x0 0x7000dc00 0x0 0x200>;
 511                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 512                 #address-cells = <1>;
 513                 #size-cells = <0>;
 514                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 515                 clock-names = "spi";
 516                 resets = <&tegra_car 104>;
 517                 reset-names = "spi";
 518                 dmas = <&apbdma 27>, <&apbdma 27>;
 519                 dma-names = "rx", "tx";
 520                 status = "disabled";
 521         };
 522
 523         spi@0,7000de00 {
 524                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 525                 reg = <0x0 0x7000de00 0x0 0x200>;
 526                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 530                 clock-names = "spi";
 531                 resets = <&tegra_car 105>;
 532                 reset-names = "spi";
 533                 dmas = <&apbdma 28>, <&apbdma 28>;
 534                 dma-names = "rx", "tx";
 535                 status = "disabled";
 536         };
 537
 538         rtc@0,7000e000 {
 539                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 540                 reg = <0x0 0x7000e000 0x0 0x100>;
 541                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 542                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 543         };
 544
 545         pmc@0,7000e400 {
 546                 compatible = "nvidia,tegra124-pmc";
 547                 reg = <0x0 0x7000e400 0x0 0x400>;
 548                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 549                 clock-names = "pclk", "clk32k_in";
 550         };
 551
 552         fuse@0,7000f800 {
 553                 compatible = "nvidia,tegra124-efuse";
 554                 reg = <0x0 0x7000f800 0x0 0x400>;
 555                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 556                 clock-names = "fuse";
 557                 resets = <&tegra_car 39>;
 558                 reset-names = "fuse";
 559         };
 560
 561         mc: memory-controller@0,70019000 {
 562                 compatible = "nvidia,tegra124-mc";
 563                 reg = <0x0 0x70019000 0x0 0x1000>;
 564                 clocks = <&tegra_car TEGRA124_CLK_MC>;
 565                 clock-names = "mc";
 566
 567                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 568
 569                 #iommu-cells = <1>;
 570         };
 571
 572         sata@0,70020000 {
 573                 compatible = "nvidia,tegra124-ahci";
 574
 575                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 576                         <0x0 0x70020000 0x0 0x7000>; /* SATA */
 577
 578                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 579
 580                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 581                         <&tegra_car TEGRA124_CLK_SATA_OOB>,
 582                         <&tegra_car TEGRA124_CLK_CML1>,
 583                         <&tegra_car TEGRA124_CLK_PLL_E>;
 584                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 585
 586                 resets = <&tegra_car 124>,
 587                         <&tegra_car 123>,
 588                         <&tegra_car 129>;
 589                 reset-names = "sata", "sata-oob", "sata-cold";
 590
 591                 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
 592                 phy-names = "sata-phy";
 593
 594                 status = "disabled";
 595         };
 596
 597         hda@0,70030000 {
 598                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 599                 reg = <0x0 0x70030000 0x0 0x10000>;
 600                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 601                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 602                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 603                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 604                 clock-names = "hda", "hda2hdmi", "hdacodec_2x";
 605                 resets = <&tegra_car 125>, /* hda */
 606                          <&tegra_car 128>, /* hda2hdmi */
 607                          <&tegra_car 111>; /* hda2codec_2x */
 608                 reset-names = "hda", "hda2hdmi", "hdacodec_2x";
 609                 status = "disabled";
 610         };
 611
 612         padctl: padctl@0,7009f000 {
 613                 compatible = "nvidia,tegra124-xusb-padctl";
 614                 reg = <0x0 0x7009f000 0x0 0x1000>;
 615                 resets = <&tegra_car 142>;
 616                 reset-names = "padctl";
 617
 618                 #phy-cells = <1>;
 619         };
 620
 621         sdhci@0,700b0000 {
 622                 compatible = "nvidia,tegra124-sdhci";
 623                 reg = <0x0 0x700b0000 0x0 0x200>;
 624                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 625                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 626                 resets = <&tegra_car 14>;
 627                 reset-names = "sdhci";
 628                 status = "disabled";
 629         };
 630
 631         sdhci@0,700b0200 {
 632                 compatible = "nvidia,tegra124-sdhci";
 633                 reg = <0x0 0x700b0200 0x0 0x200>;
 634                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 635                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 636                 resets = <&tegra_car 9>;
 637                 reset-names = "sdhci";
 638                 status = "disabled";
 639         };
 640
 641         sdhci@0,700b0400 {
 642                 compatible = "nvidia,tegra124-sdhci";
 643                 reg = <0x0 0x700b0400 0x0 0x200>;
 644                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 645                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 646                 resets = <&tegra_car 69>;
 647                 reset-names = "sdhci";
 648                 status = "disabled";
 649         };
 650
 651         sdhci@0,700b0600 {
 652                 compatible = "nvidia,tegra124-sdhci";
 653                 reg = <0x0 0x700b0600 0x0 0x200>;
 654                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 655                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 656                 resets = <&tegra_car 15>;
 657                 reset-names = "sdhci";
 658                 status = "disabled";
 659         };
 660
 661         soctherm: thermal-sensor@0,700e2000 {
 662                 compatible = "nvidia,tegra124-soctherm";
 663                 reg = <0x0 0x700e2000 0x0 0x1000>;
 664                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 665                 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
 666                         <&tegra_car TEGRA124_CLK_SOC_THERM>;
 667                 clock-names = "tsensor", "soctherm";
 668                 resets = <&tegra_car 78>;
 669                 reset-names = "soctherm";
 670                 #thermal-sensor-cells = <1>;
 671         };
 672
 673         ahub@0,70300000 {
 674                 compatible = "nvidia,tegra124-ahub";
 675                 reg = <0x0 0x70300000 0x0 0x200>,
 676                       <0x0 0x70300800 0x0 0x800>,
 677                       <0x0 0x70300200 0x0 0x600>;
 678                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 679                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 680                          <&tegra_car TEGRA124_CLK_APBIF>;
 681                 clock-names = "d_audio", "apbif";
 682                 resets = <&tegra_car 106>, /* d_audio */
 683                          <&tegra_car 107>, /* apbif */
 684                          <&tegra_car 30>,  /* i2s0 */
 685                          <&tegra_car 11>,  /* i2s1 */
 686                          <&tegra_car 18>,  /* i2s2 */
 687                          <&tegra_car 101>, /* i2s3 */
 688                          <&tegra_car 102>, /* i2s4 */
 689                          <&tegra_car 108>, /* dam0 */
 690                          <&tegra_car 109>, /* dam1 */
 691                          <&tegra_car 110>, /* dam2 */
 692                          <&tegra_car 10>,  /* spdif */
 693                          <&tegra_car 153>, /* amx */
 694                          <&tegra_car 185>, /* amx1 */
 695                          <&tegra_car 154>, /* adx */
 696                          <&tegra_car 180>, /* adx1 */
 697                          <&tegra_car 186>, /* afc0 */
 698                          <&tegra_car 187>, /* afc1 */
 699                          <&tegra_car 188>, /* afc2 */
 700                          <&tegra_car 189>, /* afc3 */
 701                          <&tegra_car 190>, /* afc4 */
 702                          <&tegra_car 191>; /* afc5 */
 703                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 704                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 705                               "spdif", "amx", "amx1", "adx", "adx1",
 706                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 707                 dmas = <&apbdma 1>, <&apbdma 1>,
 708                        <&apbdma 2>, <&apbdma 2>,
 709                        <&apbdma 3>, <&apbdma 3>,
 710                        <&apbdma 4>, <&apbdma 4>,
 711                        <&apbdma 6>, <&apbdma 6>,
 712                        <&apbdma 7>, <&apbdma 7>,
 713                        <&apbdma 12>, <&apbdma 12>,
 714                        <&apbdma 13>, <&apbdma 13>,
 715                        <&apbdma 14>, <&apbdma 14>,
 716                        <&apbdma 29>, <&apbdma 29>;
 717                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 718                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 719                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 720                             "rx9", "tx9";
 721                 ranges;
 722                 #address-cells = <2>;
 723                 #size-cells = <2>;
 724
 725                 tegra_i2s0: i2s@0,70301000 {
 726                         compatible = "nvidia,tegra124-i2s";
 727                         reg = <0x0 0x70301000 0x0 0x100>;
 728                         nvidia,ahub-cif-ids = <4 4>;
 729                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 730                         resets = <&tegra_car 30>;
 731                         reset-names = "i2s";
 732                         status = "disabled";
 733                 };
 734
 735                 tegra_i2s1: i2s@0,70301100 {
 736                         compatible = "nvidia,tegra124-i2s";
 737                         reg = <0x0 0x70301100 0x0 0x100>;
 738                         nvidia,ahub-cif-ids = <5 5>;
 739                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 740                         resets = <&tegra_car 11>;
 741                         reset-names = "i2s";
 742                         status = "disabled";
 743                 };
 744
 745                 tegra_i2s2: i2s@0,70301200 {
 746                         compatible = "nvidia,tegra124-i2s";
 747                         reg = <0x0 0x70301200 0x0 0x100>;
 748                         nvidia,ahub-cif-ids = <6 6>;
 749                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 750                         resets = <&tegra_car 18>;
 751                         reset-names = "i2s";
 752                         status = "disabled";
 753                 };
 754
 755                 tegra_i2s3: i2s@0,70301300 {
 756                         compatible = "nvidia,tegra124-i2s";
 757                         reg = <0x0 0x70301300 0x0 0x100>;
 758                         nvidia,ahub-cif-ids = <7 7>;
 759                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 760                         resets = <&tegra_car 101>;
 761                         reset-names = "i2s";
 762                         status = "disabled";
 763                 };
 764
 765                 tegra_i2s4: i2s@0,70301400 {
 766                         compatible = "nvidia,tegra124-i2s";
 767                         reg = <0x0 0x70301400 0x0 0x100>;
 768                         nvidia,ahub-cif-ids = <8 8>;
 769                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 770                         resets = <&tegra_car 102>;
 771                         reset-names = "i2s";
 772                         status = "disabled";
 773                 };
 774         };
 775
 776         usb@0,7d000000 {
 777                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 778                 reg = <0x0 0x7d000000 0x0 0x4000>;
 779                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 780                 phy_type = "utmi";
 781                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
 782                 resets = <&tegra_car 22>;
 783                 reset-names = "usb";
 784                 nvidia,phy = <&phy1>;
 785                 status = "disabled";
 786         };
 787
 788         phy1: usb-phy@0,7d000000 {
 789                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 790                 reg = <0x0 0x7d000000 0x0 0x4000>,
 791                       <0x0 0x7d000000 0x0 0x4000>;
 792                 phy_type = "utmi";
 793                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
 794                          <&tegra_car TEGRA124_CLK_PLL_U>,
 795                          <&tegra_car TEGRA124_CLK_USBD>;
 796                 clock-names = "reg", "pll_u", "utmi-pads";
 797                 resets = <&tegra_car 59>, <&tegra_car 22>;
 798                 reset-names = "usb", "utmi-pads";
 799                 nvidia,hssync-start-delay = <0>;
 800                 nvidia,idle-wait-delay = <17>;
 801                 nvidia,elastic-limit = <16>;
 802                 nvidia,term-range-adj = <6>;
 803                 nvidia,xcvr-setup = <9>;
 804                 nvidia,xcvr-lsfslew = <0>;
 805                 nvidia,xcvr-lsrslew = <3>;
 806                 nvidia,hssquelch-level = <2>;
 807                 nvidia,hsdiscon-level = <5>;
 808                 nvidia,xcvr-hsslew = <12>;
 809                 status = "disabled";
 810         };
 811
 812         usb@0,7d004000 {
 813                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 814                 reg = <0x0 0x7d004000 0x0 0x4000>;
 815                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 816                 phy_type = "utmi";
 817                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
 818                 resets = <&tegra_car 58>;
 819                 reset-names = "usb";
 820                 nvidia,phy = <&phy2>;
 821                 status = "disabled";
 822         };
 823
 824         phy2: usb-phy@0,7d004000 {
 825                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 826                 reg = <0x0 0x7d004000 0x0 0x4000>,
 827                       <0x0 0x7d000000 0x0 0x4000>;
 828                 phy_type = "utmi";
 829                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
 830                          <&tegra_car TEGRA124_CLK_PLL_U>,
 831                          <&tegra_car TEGRA124_CLK_USBD>;
 832                 clock-names = "reg", "pll_u", "utmi-pads";
 833                 resets = <&tegra_car 22>, <&tegra_car 22>;
 834                 reset-names = "usb", "utmi-pads";
 835                 nvidia,hssync-start-delay = <0>;
 836                 nvidia,idle-wait-delay = <17>;
 837                 nvidia,elastic-limit = <16>;
 838                 nvidia,term-range-adj = <6>;
 839                 nvidia,xcvr-setup = <9>;
 840                 nvidia,xcvr-lsfslew = <0>;
 841                 nvidia,xcvr-lsrslew = <3>;
 842                 nvidia,hssquelch-level = <2>;
 843                 nvidia,hsdiscon-level = <5>;
 844                 nvidia,xcvr-hsslew = <12>;
 845                 nvidia,has-utmi-pad-registers;
 846                 status = "disabled";
 847         };
 848
 849         usb@0,7d008000 {
 850                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 851                 reg = <0x0 0x7d008000 0x0 0x4000>;
 852                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 853                 phy_type = "utmi";
 854                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
 855                 resets = <&tegra_car 59>;
 856                 reset-names = "usb";
 857                 nvidia,phy = <&phy3>;
 858                 status = "disabled";
 859         };
 860
 861         phy3: usb-phy@0,7d008000 {
 862                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 863                 reg = <0x0 0x7d008000 0x0 0x4000>,
 864                       <0x0 0x7d000000 0x0 0x4000>;
 865                 phy_type = "utmi";
 866                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
 867                          <&tegra_car TEGRA124_CLK_PLL_U>,
 868                          <&tegra_car TEGRA124_CLK_USBD>;
 869                 clock-names = "reg", "pll_u", "utmi-pads";
 870                 resets = <&tegra_car 58>, <&tegra_car 22>;
 871                 reset-names = "usb", "utmi-pads";
 872                 nvidia,hssync-start-delay = <0>;
 873                 nvidia,idle-wait-delay = <17>;
 874                 nvidia,elastic-limit = <16>;
 875                 nvidia,term-range-adj = <6>;
 876                 nvidia,xcvr-setup = <9>;
 877                 nvidia,xcvr-lsfslew = <0>;
 878                 nvidia,xcvr-lsrslew = <3>;
 879                 nvidia,hssquelch-level = <2>;
 880                 nvidia,hsdiscon-level = <5>;
 881                 nvidia,xcvr-hsslew = <12>;
 882                 status = "disabled";
 883         };
 884
 885         cpus {
 886                 #address-cells = <1>;
 887                 #size-cells = <0>;
 888
 889                 cpu@0 {
 890                         device_type = "cpu";
 891                         compatible = "arm,cortex-a15";
 892                         reg = <0>;
 893                 };
 894
 895                 cpu@1 {
 896                         device_type = "cpu";
 897                         compatible = "arm,cortex-a15";
 898                         reg = <1>;
 899                 };
 900
 901                 cpu@2 {
 902                         device_type = "cpu";
 903                         compatible = "arm,cortex-a15";
 904                         reg = <2>;
 905                 };
 906
 907                 cpu@3 {
 908                         device_type = "cpu";
 909                         compatible = "arm,cortex-a15";
 910                         reg = <3>;
 911                 };
 912         };
 913
 914         thermal-zones {
 915                 cpu {
 916                         polling-delay-passive = <1000>;
 917                         polling-delay = <1000>;
 918
 919                         thermal-sensors =
 920                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
 921                 };
 922
 923                 mem {
 924                         polling-delay-passive = <1000>;
 925                         polling-delay = <1000>;
 926
 927                         thermal-sensors =
 928                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
 929                 };
 930
 931                 gpu {
 932                         polling-delay-passive = <1000>;
 933                         polling-delay = <1000>;
 934
 935                         thermal-sensors =
 936                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
 937                 };
 938
 939                 pllx {
 940                         polling-delay-passive = <1000>;
 941                         polling-delay = <1000>;
 942
 943                         thermal-sensors =
 944                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
 945                 };
 946         };
 947
 948         timer {
 949                 compatible = "arm,armv7-timer";
 950                 interrupts = <GIC_PPI 13
 951                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 952                              <GIC_PPI 14
 953                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 954                              <GIC_PPI 11
 955                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 956                              <GIC_PPI 10
 957                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 958         };
 959 };