arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/thermal/tegra124-soctherm.h>
   7
   8 #include "skeleton.dtsi"
   9
  10 / {
  11         compatible = "nvidia,tegra124";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         pcie-controller@0,01003000 {
  17                 compatible = "nvidia,tegra124-pcie";
  18                 device_type = "pci";
  19                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  20                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  21                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  22                 reg-names = "pads", "afi", "cs";
  23                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  24                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  25                 interrupt-names = "intr", "msi";
  26
  27                 #interrupt-cells = <1>;
  28                 interrupt-map-mask = <0 0 0 0>;
  29                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  30
  31                 bus-range = <0x00 0xff>;
  32                 #address-cells = <3>;
  33                 #size-cells = <2>;
  34
  35                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  36                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  37                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  38                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  39                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  40
  41                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  42                          <&tegra_car TEGRA124_CLK_AFI>,
  43                          <&tegra_car TEGRA124_CLK_PLL_E>,
  44                          <&tegra_car TEGRA124_CLK_CML0>;
  45                 clock-names = "pex", "afi", "pll_e", "cml";
  46                 resets = <&tegra_car 70>,
  47                          <&tegra_car 72>,
  48                          <&tegra_car 74>;
  49                 reset-names = "pex", "afi", "pcie_x";
  50                 status = "disabled";
  51
  52                 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
  53                 phy-names = "pcie";
  54
  55                 pci@1,0 {
  56                         device_type = "pci";
  57                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  58                         reg = <0x000800 0 0 0 0>;
  59                         status = "disabled";
  60
  61                         #address-cells = <3>;
  62                         #size-cells = <2>;
  63                         ranges;
  64
  65                         nvidia,num-lanes = <2>;
  66                 };
  67
  68                 pci@2,0 {
  69                         device_type = "pci";
  70                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  71                         reg = <0x001000 0 0 0 0>;
  72                         status = "disabled";
  73
  74                         #address-cells = <3>;
  75                         #size-cells = <2>;
  76                         ranges;
  77
  78                         nvidia,num-lanes = <1>;
  79                 };
  80         };
  81
  82         host1x@0,50000000 {
  83                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  84                 reg = <0x0 0x50000000 0x0 0x00034000>;
  85                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  86                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  87                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  88                 resets = <&tegra_car 28>;
  89                 reset-names = "host1x";
  90
  91                 #address-cells = <2>;
  92                 #size-cells = <2>;
  93
  94                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  95
  96                 dc@0,54200000 {
  97                         compatible = "nvidia,tegra124-dc";
  98                         reg = <0x0 0x54200000 0x0 0x00040000>;
  99                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 100                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
 101                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 102                         clock-names = "dc", "parent";
 103                         resets = <&tegra_car 27>;
 104                         reset-names = "dc";
 105
 106                         nvidia,head = <0>;
 107                 };
 108
 109                 dc@0,54240000 {
 110                         compatible = "nvidia,tegra124-dc";
 111                         reg = <0x0 0x54240000 0x0 0x00040000>;
 112                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 113                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
 114                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 115                         clock-names = "dc", "parent";
 116                         resets = <&tegra_car 26>;
 117                         reset-names = "dc";
 118
 119                         nvidia,head = <1>;
 120                 };
 121
 122                 hdmi@0,54280000 {
 123                         compatible = "nvidia,tegra124-hdmi";
 124                         reg = <0x0 0x54280000 0x0 0x00040000>;
 125                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 126                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
 127                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
 128                         clock-names = "hdmi", "parent";
 129                         resets = <&tegra_car 51>;
 130                         reset-names = "hdmi";
 131                         status = "disabled";
 132                 };
 133
 134                 sor@0,54540000 {
 135                         compatible = "nvidia,tegra124-sor";
 136                         reg = <0x0 0x54540000 0x0 0x00040000>;
 137                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 138                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
 139                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
 140                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
 141                                  <&tegra_car TEGRA124_CLK_CLK_M>;
 142                         clock-names = "sor", "parent", "dp", "safe";
 143                         resets = <&tegra_car 182>;
 144                         reset-names = "sor";
 145                         status = "disabled";
 146                 };
 147
 148                 dpaux: dpaux@0,545c0000 {
 149                         compatible = "nvidia,tegra124-dpaux";
 150                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 151                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 152                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
 153                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
 154                         clock-names = "dpaux", "parent";
 155                         resets = <&tegra_car 181>;
 156                         reset-names = "dpaux";
 157                         status = "disabled";
 158                 };
 159         };
 160
 161         gic: interrupt-controller@0,50041000 {
 162                 compatible = "arm,cortex-a15-gic";
 163                 #interrupt-cells = <3>;
 164                 interrupt-controller;
 165                 reg = <0x0 0x50041000 0x0 0x1000>,
 166                       <0x0 0x50042000 0x0 0x1000>,
 167                       <0x0 0x50044000 0x0 0x2000>,
 168                       <0x0 0x50046000 0x0 0x2000>;
 169                 interrupts = <GIC_PPI 9
 170                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 171         };
 172
 173         gpu@0,57000000 {
 174                 compatible = "nvidia,gk20a";
 175                 reg = <0x0 0x57000000 0x0 0x01000000>,
 176                       <0x0 0x58000000 0x0 0x01000000>;
 177                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 179                 interrupt-names = "stall", "nonstall";
 180                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 181                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 182                 clock-names = "gpu", "pwr";
 183                 resets = <&tegra_car 184>;
 184                 reset-names = "gpu";
 185                 status = "disabled";
 186         };
 187
 188         timer@0,60005000 {
 189                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 190                 reg = <0x0 0x60005000 0x0 0x400>;
 191                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 197                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 198         };
 199
 200         tegra_car: clock@0,60006000 {
 201                 compatible = "nvidia,tegra124-car";
 202                 reg = <0x0 0x60006000 0x0 0x1000>;
 203                 #clock-cells = <1>;
 204                 #reset-cells = <1>;
 205         };
 206
 207         flow-controller@0,60007000 {
 208                 compatible = "nvidia,tegra124-flowctrl";
 209                 reg = <0x0 0x60007000 0x0 0x1000>;
 210         };
 211
 212         gpio: gpio@0,6000d000 {
 213                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 214                 reg = <0x0 0x6000d000 0x0 0x1000>;
 215                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 217                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 223                 #gpio-cells = <2>;
 224                 gpio-controller;
 225                 #interrupt-cells = <2>;
 226                 interrupt-controller;
 227         };
 228
 229         apbdma: dma@0,60020000 {
 230                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 231                 reg = <0x0 0x60020000 0x0 0x1400>;
 232                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 233                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 234                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 235                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 236                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 241                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 243                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 244                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 245                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 246                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 247                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 248                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 249                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 250                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 251                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 252                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 253                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 264                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 265                 resets = <&tegra_car 34>;
 266                 reset-names = "dma";
 267                 #dma-cells = <1>;
 268         };
 269
 270         apbmisc@0,70000800 {
 271                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 272                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 273                       <0x0 0x7000E864 0x0 0x04>;   /* Strapping options */
 274         };
 275
 276         pinmux: pinmux@0,70000868 {
 277                 compatible = "nvidia,tegra124-pinmux";
 278                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 279                       <0x0 0x70003000 0x0 0x434>; /* Mux registers */
 280         };
 281
 282         /*
 283          * There are two serial driver i.e. 8250 based simple serial
 284          * driver and APB DMA based serial driver for higher baudrate
 285          * and performace. To enable the 8250 based driver, the compatible
 286          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 287          * the APB DMA based serial driver, the comptible is
 288          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 289          */
 290         uarta: serial@0,70006000 {
 291                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 292                 reg = <0x0 0x70006000 0x0 0x40>;
 293                 reg-shift = <2>;
 294                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 295                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 296                 resets = <&tegra_car 6>;
 297                 reset-names = "serial";
 298                 dmas = <&apbdma 8>, <&apbdma 8>;
 299                 dma-names = "rx", "tx";
 300                 status = "disabled";
 301         };
 302
 303         uartb: serial@0,70006040 {
 304                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 305                 reg = <0x0 0x70006040 0x0 0x40>;
 306                 reg-shift = <2>;
 307                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 308                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 309                 resets = <&tegra_car 7>;
 310                 reset-names = "serial";
 311                 dmas = <&apbdma 9>, <&apbdma 9>;
 312                 dma-names = "rx", "tx";
 313                 status = "disabled";
 314         };
 315
 316         uartc: serial@0,70006200 {
 317                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 318                 reg = <0x0 0x70006200 0x0 0x40>;
 319                 reg-shift = <2>;
 320                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 321                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 322                 resets = <&tegra_car 55>;
 323                 reset-names = "serial";
 324                 dmas = <&apbdma 10>, <&apbdma 10>;
 325                 dma-names = "rx", "tx";
 326                 status = "disabled";
 327         };
 328
 329         uartd: serial@0,70006300 {
 330                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 331                 reg = <0x0 0x70006300 0x0 0x40>;
 332                 reg-shift = <2>;
 333                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 334                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 335                 resets = <&tegra_car 65>;
 336                 reset-names = "serial";
 337                 dmas = <&apbdma 19>, <&apbdma 19>;
 338                 dma-names = "rx", "tx";
 339                 status = "disabled";
 340         };
 341
 342         pwm: pwm@0,7000a000 {
 343                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 344                 reg = <0x0 0x7000a000 0x0 0x100>;
 345                 #pwm-cells = <2>;
 346                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 347                 resets = <&tegra_car 17>;
 348                 reset-names = "pwm";
 349                 status = "disabled";
 350         };
 351
 352         i2c@0,7000c000 {
 353                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 354                 reg = <0x0 0x7000c000 0x0 0x100>;
 355                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 356                 #address-cells = <1>;
 357                 #size-cells = <0>;
 358                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 359                 clock-names = "div-clk";
 360                 resets = <&tegra_car 12>;
 361                 reset-names = "i2c";
 362                 dmas = <&apbdma 21>, <&apbdma 21>;
 363                 dma-names = "rx", "tx";
 364                 status = "disabled";
 365         };
 366
 367         i2c@0,7000c400 {
 368                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 369                 reg = <0x0 0x7000c400 0x0 0x100>;
 370                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 371                 #address-cells = <1>;
 372                 #size-cells = <0>;
 373                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 374                 clock-names = "div-clk";
 375                 resets = <&tegra_car 54>;
 376                 reset-names = "i2c";
 377                 dmas = <&apbdma 22>, <&apbdma 22>;
 378                 dma-names = "rx", "tx";
 379                 status = "disabled";
 380         };
 381
 382         i2c@0,7000c500 {
 383                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 384                 reg = <0x0 0x7000c500 0x0 0x100>;
 385                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 389                 clock-names = "div-clk";
 390                 resets = <&tegra_car 67>;
 391                 reset-names = "i2c";
 392                 dmas = <&apbdma 23>, <&apbdma 23>;
 393                 dma-names = "rx", "tx";
 394                 status = "disabled";
 395         };
 396
 397         i2c@0,7000c700 {
 398                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 399                 reg = <0x0 0x7000c700 0x0 0x100>;
 400                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 404                 clock-names = "div-clk";
 405                 resets = <&tegra_car 103>;
 406                 reset-names = "i2c";
 407                 dmas = <&apbdma 26>, <&apbdma 26>;
 408                 dma-names = "rx", "tx";
 409                 status = "disabled";
 410         };
 411
 412         i2c@0,7000d000 {
 413                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 414                 reg = <0x0 0x7000d000 0x0 0x100>;
 415                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 419                 clock-names = "div-clk";
 420                 resets = <&tegra_car 47>;
 421                 reset-names = "i2c";
 422                 dmas = <&apbdma 24>, <&apbdma 24>;
 423                 dma-names = "rx", "tx";
 424                 status = "disabled";
 425         };
 426
 427         i2c@0,7000d100 {
 428                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 429                 reg = <0x0 0x7000d100 0x0 0x100>;
 430                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 431                 #address-cells = <1>;
 432                 #size-cells = <0>;
 433                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 434                 clock-names = "div-clk";
 435                 resets = <&tegra_car 166>;
 436                 reset-names = "i2c";
 437                 dmas = <&apbdma 30>, <&apbdma 30>;
 438                 dma-names = "rx", "tx";
 439                 status = "disabled";
 440         };
 441
 442         spi@0,7000d400 {
 443                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 444                 reg = <0x0 0x7000d400 0x0 0x200>;
 445                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 446                 #address-cells = <1>;
 447                 #size-cells = <0>;
 448                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 449                 clock-names = "spi";
 450                 resets = <&tegra_car 41>;
 451                 reset-names = "spi";
 452                 dmas = <&apbdma 15>, <&apbdma 15>;
 453                 dma-names = "rx", "tx";
 454                 status = "disabled";
 455         };
 456
 457         spi@0,7000d600 {
 458                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 459                 reg = <0x0 0x7000d600 0x0 0x200>;
 460                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 464                 clock-names = "spi";
 465                 resets = <&tegra_car 44>;
 466                 reset-names = "spi";
 467                 dmas = <&apbdma 16>, <&apbdma 16>;
 468                 dma-names = "rx", "tx";
 469                 status = "disabled";
 470         };
 471
 472         spi@0,7000d800 {
 473                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 474                 reg = <0x0 0x7000d800 0x0 0x200>;
 475                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 476                 #address-cells = <1>;
 477                 #size-cells = <0>;
 478                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 479                 clock-names = "spi";
 480                 resets = <&tegra_car 46>;
 481                 reset-names = "spi";
 482                 dmas = <&apbdma 17>, <&apbdma 17>;
 483                 dma-names = "rx", "tx";
 484                 status = "disabled";
 485         };
 486
 487         spi@0,7000da00 {
 488                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 489                 reg = <0x0 0x7000da00 0x0 0x200>;
 490                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 491                 #address-cells = <1>;
 492                 #size-cells = <0>;
 493                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 494                 clock-names = "spi";
 495                 resets = <&tegra_car 68>;
 496                 reset-names = "spi";
 497                 dmas = <&apbdma 18>, <&apbdma 18>;
 498                 dma-names = "rx", "tx";
 499                 status = "disabled";
 500         };
 501
 502         spi@0,7000dc00 {
 503                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 504                 reg = <0x0 0x7000dc00 0x0 0x200>;
 505                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 506                 #address-cells = <1>;
 507                 #size-cells = <0>;
 508                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 509                 clock-names = "spi";
 510                 resets = <&tegra_car 104>;
 511                 reset-names = "spi";
 512                 dmas = <&apbdma 27>, <&apbdma 27>;
 513                 dma-names = "rx", "tx";
 514                 status = "disabled";
 515         };
 516
 517         spi@0,7000de00 {
 518                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 519                 reg = <0x0 0x7000de00 0x0 0x200>;
 520                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 521                 #address-cells = <1>;
 522                 #size-cells = <0>;
 523                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 524                 clock-names = "spi";
 525                 resets = <&tegra_car 105>;
 526                 reset-names = "spi";
 527                 dmas = <&apbdma 28>, <&apbdma 28>;
 528                 dma-names = "rx", "tx";
 529                 status = "disabled";
 530         };
 531
 532         rtc@0,7000e000 {
 533                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 534                 reg = <0x0 0x7000e000 0x0 0x100>;
 535                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 536                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 537         };
 538
 539         pmc@0,7000e400 {
 540                 compatible = "nvidia,tegra124-pmc";
 541                 reg = <0x0 0x7000e400 0x0 0x400>;
 542                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 543                 clock-names = "pclk", "clk32k_in";
 544         };
 545
 546         fuse@0,7000f800 {
 547                 compatible = "nvidia,tegra124-efuse";
 548                 reg = <0x0 0x7000f800 0x0 0x400>;
 549                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 550                 clock-names = "fuse";
 551                 resets = <&tegra_car 39>;
 552                 reset-names = "fuse";
 553         };
 554
 555         sata@0,70020000 {
 556                 compatible = "nvidia,tegra124-ahci";
 557
 558                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 559                         <0x0 0x70020000 0x0 0x7000>; /* SATA */
 560
 561                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 562
 563                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 564                         <&tegra_car TEGRA124_CLK_SATA_OOB>,
 565                         <&tegra_car TEGRA124_CLK_CML1>,
 566                         <&tegra_car TEGRA124_CLK_PLL_E>;
 567                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 568
 569                 resets = <&tegra_car 124>,
 570                         <&tegra_car 123>,
 571                         <&tegra_car 129>;
 572                 reset-names = "sata", "sata-oob", "sata-cold";
 573
 574                 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
 575                 phy-names = "sata-phy";
 576
 577                 status = "disabled";
 578         };
 579
 580         hda@0,70030000 {
 581                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 582                 reg = <0x0 0x70030000 0x0 0x10000>;
 583                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 584                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 585                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 586                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 587                 clock-names = "hda", "hda2hdmi", "hdacodec_2x";
 588                 resets = <&tegra_car 125>, /* hda */
 589                          <&tegra_car 128>, /* hda2hdmi */
 590                          <&tegra_car 111>; /* hda2codec_2x */
 591                 reset-names = "hda", "hda2hdmi", "hdacodec_2x";
 592                 status = "disabled";
 593         };
 594
 595         padctl: padctl@0,7009f000 {
 596                 compatible = "nvidia,tegra124-xusb-padctl";
 597                 reg = <0x0 0x7009f000 0x0 0x1000>;
 598                 resets = <&tegra_car 142>;
 599                 reset-names = "padctl";
 600
 601                 #phy-cells = <1>;
 602         };
 603
 604         sdhci@0,700b0000 {
 605                 compatible = "nvidia,tegra124-sdhci";
 606                 reg = <0x0 0x700b0000 0x0 0x200>;
 607                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 608                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 609                 resets = <&tegra_car 14>;
 610                 reset-names = "sdhci";
 611                 status = "disabled";
 612         };
 613
 614         sdhci@0,700b0200 {
 615                 compatible = "nvidia,tegra124-sdhci";
 616                 reg = <0x0 0x700b0200 0x0 0x200>;
 617                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 618                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 619                 resets = <&tegra_car 9>;
 620                 reset-names = "sdhci";
 621                 status = "disabled";
 622         };
 623
 624         sdhci@0,700b0400 {
 625                 compatible = "nvidia,tegra124-sdhci";
 626                 reg = <0x0 0x700b0400 0x0 0x200>;
 627                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 628                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 629                 resets = <&tegra_car 69>;
 630                 reset-names = "sdhci";
 631                 status = "disabled";
 632         };
 633
 634         sdhci@0,700b0600 {
 635                 compatible = "nvidia,tegra124-sdhci";
 636                 reg = <0x0 0x700b0600 0x0 0x200>;
 637                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 638                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 639                 resets = <&tegra_car 15>;
 640                 reset-names = "sdhci";
 641                 status = "disabled";
 642         };
 643
 644         soctherm: thermal-sensor@0,700e2000 {
 645                 compatible = "nvidia,tegra124-soctherm";
 646                 reg = <0x0 0x700e2000 0x0 0x1000>;
 647                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 648                 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
 649                         <&tegra_car TEGRA124_CLK_SOC_THERM>;
 650                 clock-names = "tsensor", "soctherm";
 651                 resets = <&tegra_car 78>;
 652                 reset-names = "soctherm";
 653                 #thermal-sensor-cells = <1>;
 654         };
 655
 656         ahub@0,70300000 {
 657                 compatible = "nvidia,tegra124-ahub";
 658                 reg = <0x0 0x70300000 0x0 0x200>,
 659                       <0x0 0x70300800 0x0 0x800>,
 660                       <0x0 0x70300200 0x0 0x600>;
 661                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 662                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 663                          <&tegra_car TEGRA124_CLK_APBIF>;
 664                 clock-names = "d_audio", "apbif";
 665                 resets = <&tegra_car 106>, /* d_audio */
 666                          <&tegra_car 107>, /* apbif */
 667                          <&tegra_car 30>,  /* i2s0 */
 668                          <&tegra_car 11>,  /* i2s1 */
 669                          <&tegra_car 18>,  /* i2s2 */
 670                          <&tegra_car 101>, /* i2s3 */
 671                          <&tegra_car 102>, /* i2s4 */
 672                          <&tegra_car 108>, /* dam0 */
 673                          <&tegra_car 109>, /* dam1 */
 674                          <&tegra_car 110>, /* dam2 */
 675                          <&tegra_car 10>,  /* spdif */
 676                          <&tegra_car 153>, /* amx */
 677                          <&tegra_car 185>, /* amx1 */
 678                          <&tegra_car 154>, /* adx */
 679                          <&tegra_car 180>, /* adx1 */
 680                          <&tegra_car 186>, /* afc0 */
 681                          <&tegra_car 187>, /* afc1 */
 682                          <&tegra_car 188>, /* afc2 */
 683                          <&tegra_car 189>, /* afc3 */
 684                          <&tegra_car 190>, /* afc4 */
 685                          <&tegra_car 191>; /* afc5 */
 686                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 687                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 688                               "spdif", "amx", "amx1", "adx", "adx1",
 689                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 690                 dmas = <&apbdma 1>, <&apbdma 1>,
 691                        <&apbdma 2>, <&apbdma 2>,
 692                        <&apbdma 3>, <&apbdma 3>,
 693                        <&apbdma 4>, <&apbdma 4>,
 694                        <&apbdma 6>, <&apbdma 6>,
 695                        <&apbdma 7>, <&apbdma 7>,
 696                        <&apbdma 12>, <&apbdma 12>,
 697                        <&apbdma 13>, <&apbdma 13>,
 698                        <&apbdma 14>, <&apbdma 14>,
 699                        <&apbdma 29>, <&apbdma 29>;
 700                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 701                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 702                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 703                             "rx9", "tx9";
 704                 ranges;
 705                 #address-cells = <2>;
 706                 #size-cells = <2>;
 707
 708                 tegra_i2s0: i2s@0,70301000 {
 709                         compatible = "nvidia,tegra124-i2s";
 710                         reg = <0x0 0x70301000 0x0 0x100>;
 711                         nvidia,ahub-cif-ids = <4 4>;
 712                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 713                         resets = <&tegra_car 30>;
 714                         reset-names = "i2s";
 715                         status = "disabled";
 716                 };
 717
 718                 tegra_i2s1: i2s@0,70301100 {
 719                         compatible = "nvidia,tegra124-i2s";
 720                         reg = <0x0 0x70301100 0x0 0x100>;
 721                         nvidia,ahub-cif-ids = <5 5>;
 722                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 723                         resets = <&tegra_car 11>;
 724                         reset-names = "i2s";
 725                         status = "disabled";
 726                 };
 727
 728                 tegra_i2s2: i2s@0,70301200 {
 729                         compatible = "nvidia,tegra124-i2s";
 730                         reg = <0x0 0x70301200 0x0 0x100>;
 731                         nvidia,ahub-cif-ids = <6 6>;
 732                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 733                         resets = <&tegra_car 18>;
 734                         reset-names = "i2s";
 735                         status = "disabled";
 736                 };
 737
 738                 tegra_i2s3: i2s@0,70301300 {
 739                         compatible = "nvidia,tegra124-i2s";
 740                         reg = <0x0 0x70301300 0x0 0x100>;
 741                         nvidia,ahub-cif-ids = <7 7>;
 742                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 743                         resets = <&tegra_car 101>;
 744                         reset-names = "i2s";
 745                         status = "disabled";
 746                 };
 747
 748                 tegra_i2s4: i2s@0,70301400 {
 749                         compatible = "nvidia,tegra124-i2s";
 750                         reg = <0x0 0x70301400 0x0 0x100>;
 751                         nvidia,ahub-cif-ids = <8 8>;
 752                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 753                         resets = <&tegra_car 102>;
 754                         reset-names = "i2s";
 755                         status = "disabled";
 756                 };
 757         };
 758
 759         usb@0,7d000000 {
 760                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 761                 reg = <0x0 0x7d000000 0x0 0x4000>;
 762                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 763                 phy_type = "utmi";
 764                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
 765                 resets = <&tegra_car 22>;
 766                 reset-names = "usb";
 767                 nvidia,phy = <&phy1>;
 768                 status = "disabled";
 769         };
 770
 771         phy1: usb-phy@0,7d000000 {
 772                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 773                 reg = <0x0 0x7d000000 0x0 0x4000>,
 774                       <0x0 0x7d000000 0x0 0x4000>;
 775                 phy_type = "utmi";
 776                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
 777                          <&tegra_car TEGRA124_CLK_PLL_U>,
 778                          <&tegra_car TEGRA124_CLK_USBD>;
 779                 clock-names = "reg", "pll_u", "utmi-pads";
 780                 resets = <&tegra_car 59>, <&tegra_car 22>;
 781                 reset-names = "usb", "utmi-pads";
 782                 nvidia,hssync-start-delay = <0>;
 783                 nvidia,idle-wait-delay = <17>;
 784                 nvidia,elastic-limit = <16>;
 785                 nvidia,term-range-adj = <6>;
 786                 nvidia,xcvr-setup = <9>;
 787                 nvidia,xcvr-lsfslew = <0>;
 788                 nvidia,xcvr-lsrslew = <3>;
 789                 nvidia,hssquelch-level = <2>;
 790                 nvidia,hsdiscon-level = <5>;
 791                 nvidia,xcvr-hsslew = <12>;
 792                 status = "disabled";
 793         };
 794
 795         usb@0,7d004000 {
 796                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 797                 reg = <0x0 0x7d004000 0x0 0x4000>;
 798                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 799                 phy_type = "utmi";
 800                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
 801                 resets = <&tegra_car 58>;
 802                 reset-names = "usb";
 803                 nvidia,phy = <&phy2>;
 804                 status = "disabled";
 805         };
 806
 807         phy2: usb-phy@0,7d004000 {
 808                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 809                 reg = <0x0 0x7d004000 0x0 0x4000>,
 810                       <0x0 0x7d000000 0x0 0x4000>;
 811                 phy_type = "utmi";
 812                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
 813                          <&tegra_car TEGRA124_CLK_PLL_U>,
 814                          <&tegra_car TEGRA124_CLK_USBD>;
 815                 clock-names = "reg", "pll_u", "utmi-pads";
 816                 resets = <&tegra_car 22>, <&tegra_car 22>;
 817                 reset-names = "usb", "utmi-pads";
 818                 nvidia,hssync-start-delay = <0>;
 819                 nvidia,idle-wait-delay = <17>;
 820                 nvidia,elastic-limit = <16>;
 821                 nvidia,term-range-adj = <6>;
 822                 nvidia,xcvr-setup = <9>;
 823                 nvidia,xcvr-lsfslew = <0>;
 824                 nvidia,xcvr-lsrslew = <3>;
 825                 nvidia,hssquelch-level = <2>;
 826                 nvidia,hsdiscon-level = <5>;
 827                 nvidia,xcvr-hsslew = <12>;
 828                 nvidia,has-utmi-pad-registers;
 829                 status = "disabled";
 830         };
 831
 832         usb@0,7d008000 {
 833                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 834                 reg = <0x0 0x7d008000 0x0 0x4000>;
 835                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 836                 phy_type = "utmi";
 837                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
 838                 resets = <&tegra_car 59>;
 839                 reset-names = "usb";
 840                 nvidia,phy = <&phy3>;
 841                 status = "disabled";
 842         };
 843
 844         phy3: usb-phy@0,7d008000 {
 845                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 846                 reg = <0x0 0x7d008000 0x0 0x4000>,
 847                       <0x0 0x7d000000 0x0 0x4000>;
 848                 phy_type = "utmi";
 849                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
 850                          <&tegra_car TEGRA124_CLK_PLL_U>,
 851                          <&tegra_car TEGRA124_CLK_USBD>;
 852                 clock-names = "reg", "pll_u", "utmi-pads";
 853                 resets = <&tegra_car 58>, <&tegra_car 22>;
 854                 reset-names = "usb", "utmi-pads";
 855                 nvidia,hssync-start-delay = <0>;
 856                 nvidia,idle-wait-delay = <17>;
 857                 nvidia,elastic-limit = <16>;
 858                 nvidia,term-range-adj = <6>;
 859                 nvidia,xcvr-setup = <9>;
 860                 nvidia,xcvr-lsfslew = <0>;
 861                 nvidia,xcvr-lsrslew = <3>;
 862                 nvidia,hssquelch-level = <2>;
 863                 nvidia,hsdiscon-level = <5>;
 864                 nvidia,xcvr-hsslew = <12>;
 865                 status = "disabled";
 866         };
 867
 868         cpus {
 869                 #address-cells = <1>;
 870                 #size-cells = <0>;
 871
 872                 cpu@0 {
 873                         device_type = "cpu";
 874                         compatible = "arm,cortex-a15";
 875                         reg = <0>;
 876                 };
 877
 878                 cpu@1 {
 879                         device_type = "cpu";
 880                         compatible = "arm,cortex-a15";
 881                         reg = <1>;
 882                 };
 883
 884                 cpu@2 {
 885                         device_type = "cpu";
 886                         compatible = "arm,cortex-a15";
 887                         reg = <2>;
 888                 };
 889
 890                 cpu@3 {
 891                         device_type = "cpu";
 892                         compatible = "arm,cortex-a15";
 893                         reg = <3>;
 894                 };
 895         };
 896
 897         thermal-zones {
 898                 cpu {
 899                         polling-delay-passive = <1000>;
 900                         polling-delay = <1000>;
 901
 902                         thermal-sensors =
 903                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
 904                 };
 905
 906                 mem {
 907                         polling-delay-passive = <1000>;
 908                         polling-delay = <1000>;
 909
 910                         thermal-sensors =
 911                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
 912                 };
 913
 914                 gpu {
 915                         polling-delay-passive = <1000>;
 916                         polling-delay = <1000>;
 917
 918                         thermal-sensors =
 919                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
 920                 };
 921
 922                 pllx {
 923                         polling-delay-passive = <1000>;
 924                         polling-delay = <1000>;
 925
 926                         thermal-sensors =
 927                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
 928                 };
 929         };
 930
 931         timer {
 932                 compatible = "arm,armv7-timer";
 933                 interrupts = <GIC_PPI 13
 934                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 935                              <GIC_PPI 14
 936                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 937                              <GIC_PPI 11
 938                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 939                              <GIC_PPI 10
 940                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 941         };
 942 };