2 * Copyright (C) 2011 - 2014 Xilinx
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 /include/ "skeleton.dtsi"
16 compatible = "xlnx,zynq-7000";
23 compatible = "arm,cortex-a9";
27 clock-latency = <1000>;
28 cpu0-supply = <®ulator_vccpint>;
38 compatible = "arm,cortex-a9";
46 compatible = "arm,cortex-a9-pmu";
47 interrupts = <0 5 4>, <0 6 4>;
48 interrupt-parent = <&intc>;
49 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
52 regulator_vccpint: fixedregulator@0 {
53 compatible = "regulator-fixed";
54 regulator-name = "VCCPINT";
55 regulator-min-microvolt = <1000000>;
56 regulator-max-microvolt = <1000000>;
62 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
69 compatible = "xlnx,zynq-xadc-1.00.a";
70 reg = <0xf8007100 0x20>;
72 interrupt-parent = <&intc>;
76 gpio0: gpio@e000a000 {
77 compatible = "xlnx,zynq-gpio-1.0";
81 interrupt-parent = <&intc>;
82 interrupts = <0 20 4>;
83 reg = <0xe000a000 0x1000>;
87 compatible = "cdns,i2c-r1p10";
90 interrupt-parent = <&intc>;
91 interrupts = <0 25 4>;
92 reg = <0xe0004000 0x1000>;
98 compatible = "cdns,i2c-r1p10";
101 interrupt-parent = <&intc>;
102 interrupts = <0 48 4>;
103 reg = <0xe0005000 0x1000>;
104 #address-cells = <1>;
108 intc: interrupt-controller@f8f01000 {
109 compatible = "arm,cortex-a9-gic";
110 #interrupt-cells = <3>;
111 interrupt-controller;
112 reg = <0xF8F01000 0x1000>,
116 L2: cache-controller {
117 compatible = "arm,pl310-cache";
118 reg = <0xF8F02000 0x1000>;
119 arm,data-latency = <3 2 2>;
120 arm,tag-latency = <2 2 2>;
125 uart0: serial@e0000000 {
126 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
128 clocks = <&clkc 23>, <&clkc 40>;
129 clock-names = "uart_clk", "pclk";
130 reg = <0xE0000000 0x1000>;
131 interrupts = <0 27 4>;
134 uart1: serial@e0001000 {
135 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
137 clocks = <&clkc 24>, <&clkc 41>;
138 clock-names = "uart_clk", "pclk";
139 reg = <0xE0001000 0x1000>;
140 interrupts = <0 50 4>;
143 gem0: ethernet@e000b000 {
144 compatible = "cdns,gem";
145 reg = <0xe000b000 0x4000>;
147 interrupts = <0 22 4>;
148 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
149 clock-names = "pclk", "hclk", "tx_clk";
152 gem1: ethernet@e000c000 {
153 compatible = "cdns,gem";
154 reg = <0xe000c000 0x4000>;
156 interrupts = <0 45 4>;
157 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
158 clock-names = "pclk", "hclk", "tx_clk";
161 sdhci0: sdhci@e0100000 {
162 compatible = "arasan,sdhci-8.9a";
164 clock-names = "clk_xin", "clk_ahb";
165 clocks = <&clkc 21>, <&clkc 32>;
166 interrupt-parent = <&intc>;
167 interrupts = <0 24 4>;
168 reg = <0xe0100000 0x1000>;
171 sdhci1: sdhci@e0101000 {
172 compatible = "arasan,sdhci-8.9a";
174 clock-names = "clk_xin", "clk_ahb";
175 clocks = <&clkc 22>, <&clkc 33>;
176 interrupt-parent = <&intc>;
177 interrupts = <0 47 4>;
178 reg = <0xe0101000 0x1000>;
181 slcr: slcr@f8000000 {
182 #address-cells = <1>;
184 compatible = "xlnx,zynq-slcr", "syscon";
185 reg = <0xF8000000 0x1000>;
189 compatible = "xlnx,ps7-clkc";
190 ps-clk-frequency = <33333333>;
192 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
193 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
194 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
195 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
196 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
197 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
198 "gem1_aper", "sdio0_aper", "sdio1_aper",
199 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
200 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
201 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
202 "dbg_trc", "dbg_apb";
207 dmac_s: dmac@f8003000 {
208 compatible = "arm,pl330", "arm,primecell";
209 reg = <0xf8003000 0x1000>;
210 interrupt-parent = <&intc>;
211 interrupts = <0 13 4>,
220 clock-names = "apb_pclk";
223 devcfg: devcfg@f8007000 {
224 compatible = "xlnx,zynq-devcfg-1.0";
225 reg = <0xf8007000 0x100>;
228 global_timer: timer@f8f00200 {
229 compatible = "arm,cortex-a9-global-timer";
230 reg = <0xf8f00200 0x20>;
231 interrupts = <1 11 0x301>;
232 interrupt-parent = <&intc>;
236 ttc0: timer@f8001000 {
237 interrupt-parent = <&intc>;
238 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
239 compatible = "cdns,ttc";
241 reg = <0xF8001000 0x1000>;
244 ttc1: timer@f8002000 {
245 interrupt-parent = <&intc>;
246 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
247 compatible = "cdns,ttc";
249 reg = <0xF8002000 0x1000>;
252 scutimer: timer@f8f00600 {
253 interrupt-parent = <&intc>;
254 interrupts = <1 13 0x301>;
255 compatible = "arm,cortex-a9-twd-timer";
256 reg = <0xf8f00600 0x20>;