arch/arm/boot/dts/zynq-parallella.dts

   1 /*
   2  * Copyright (c) 2014 SUSE LINUX Products GmbH
   3  *
   4  * Derived from zynq-zed.dts:
   5  *
   6  *  Copyright (C) 2011 Xilinx
   7  *  Copyright (C) 2012 National Instruments Corp.
   8  *  Copyright (C) 2013 Xilinx
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19 /dts-v1/;
  20 /include/ "zynq-7000.dtsi"
  21
  22 / {
  23         model = "Adapteva Parallella Board";
  24         compatible = "adapteva,parallella", "xlnx,zynq-7000";
  25
  26         memory {
  27                 device_type = "memory";
  28                 reg = <0x0 0x40000000>;
  29         };
  30
  31         chosen {
  32                 bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
  33                 linux,stdout-path = "/amba/serial@e0001000";
  34         };
  35 };
  36
  37 &clkc {
  38         fclk-enable = <0xf>;
  39 };
  40
  41 &gem0 {
  42         status = "okay";
  43         phy-mode = "rgmii-id";
  44         phy-handle = <&ethernet_phy>;
  45
  46         ethernet_phy: ethernet-phy@0 {
  47                 /* Marvell 88E1318 */
  48                 compatible = "ethernet-phy-id0141.0e90",
  49                              "ethernet-phy-ieee802.3-c22";
  50                 reg = <0>;
  51                 marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
  52                                    <0x3 0x11 0xfff0 0xa>;
  53         };
  54 };
  55
  56 &i2c0 {
  57         status = "okay";
  58
  59         isl9305: isl9305@68 {
  60                 compatible = "isl,isl9305";
  61                 reg = <0x68>;
  62
  63                 regulators {
  64                         dcd1 {
  65                                 regulator-name = "VDD_DSP";
  66                                 regulator-always-on;
  67                         };
  68                         dcd2 {
  69                                 regulator-name = "1P35V";
  70                                 regulator-always-on;
  71                         };
  72                         ldo1 {
  73                                 regulator-name = "VDD_ADJ";
  74                         };
  75                         ldo2 {
  76                                 regulator-name = "VDD_GPIO";
  77                                 regulator-always-on;
  78                         };
  79                 };
  80         };
  81 };
  82
  83 &sdhci1 {
  84         status = "okay";
  85 };
  86
  87 &uart1 {
  88         status = "okay";
  89 };