2 * arch/arm/include/asm/arch_gicv3.h
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __ASM_ARCH_GICV3_H
19 #define __ASM_ARCH_GICV3_H
24 #include <asm/barrier.h>
27 #define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1)
28 #define ICC_DIR __ACCESS_CP15(c12, 0, c11, 1)
29 #define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0)
30 #define ICC_SGI1R __ACCESS_CP15_64(0, c12)
31 #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0)
32 #define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4)
33 #define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5)
34 #define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7)
36 #define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5)
38 #define ICH_VSEIR __ACCESS_CP15(c12, 4, c9, 4)
39 #define ICH_HCR __ACCESS_CP15(c12, 4, c11, 0)
40 #define ICH_VTR __ACCESS_CP15(c12, 4, c11, 1)
41 #define ICH_MISR __ACCESS_CP15(c12, 4, c11, 2)
42 #define ICH_EISR __ACCESS_CP15(c12, 4, c11, 3)
43 #define ICH_ELSR __ACCESS_CP15(c12, 4, c11, 5)
44 #define ICH_VMCR __ACCESS_CP15(c12, 4, c11, 7)
46 #define __LR0(x) __ACCESS_CP15(c12, 4, c12, x)
47 #define __LR8(x) __ACCESS_CP15(c12, 4, c13, x)
49 #define ICH_LR0 __LR0(0)
50 #define ICH_LR1 __LR0(1)
51 #define ICH_LR2 __LR0(2)
52 #define ICH_LR3 __LR0(3)
53 #define ICH_LR4 __LR0(4)
54 #define ICH_LR5 __LR0(5)
55 #define ICH_LR6 __LR0(6)
56 #define ICH_LR7 __LR0(7)
57 #define ICH_LR8 __LR8(0)
58 #define ICH_LR9 __LR8(1)
59 #define ICH_LR10 __LR8(2)
60 #define ICH_LR11 __LR8(3)
61 #define ICH_LR12 __LR8(4)
62 #define ICH_LR13 __LR8(5)
63 #define ICH_LR14 __LR8(6)
64 #define ICH_LR15 __LR8(7)
67 #define __LRC0(x) __ACCESS_CP15(c12, 4, c14, x)
68 #define __LRC8(x) __ACCESS_CP15(c12, 4, c15, x)
70 #define ICH_LRC0 __LRC0(0)
71 #define ICH_LRC1 __LRC0(1)
72 #define ICH_LRC2 __LRC0(2)
73 #define ICH_LRC3 __LRC0(3)
74 #define ICH_LRC4 __LRC0(4)
75 #define ICH_LRC5 __LRC0(5)
76 #define ICH_LRC6 __LRC0(6)
77 #define ICH_LRC7 __LRC0(7)
78 #define ICH_LRC8 __LRC8(0)
79 #define ICH_LRC9 __LRC8(1)
80 #define ICH_LRC10 __LRC8(2)
81 #define ICH_LRC11 __LRC8(3)
82 #define ICH_LRC12 __LRC8(4)
83 #define ICH_LRC13 __LRC8(5)
84 #define ICH_LRC14 __LRC8(6)
85 #define ICH_LRC15 __LRC8(7)
87 #define __AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x)
88 #define ICH_AP0R0 __AP0Rx(0)
89 #define ICH_AP0R1 __AP0Rx(1)
90 #define ICH_AP0R2 __AP0Rx(2)
91 #define ICH_AP0R3 __AP0Rx(3)
93 #define __AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x)
94 #define ICH_AP1R0 __AP1Rx(0)
95 #define ICH_AP1R1 __AP1Rx(1)
96 #define ICH_AP1R2 __AP1Rx(2)
97 #define ICH_AP1R3 __AP1Rx(3)
99 /* A32-to-A64 mappings used by VGIC save/restore */
101 #define CPUIF_MAP(a32, a64) \
102 static inline void write_ ## a64(u32 val) \
104 write_sysreg(val, a32); \
106 static inline u32 read_ ## a64(void) \
108 return read_sysreg(a32); \
111 #define CPUIF_MAP_LO_HI(a32lo, a32hi, a64) \
112 static inline void write_ ## a64(u64 val) \
114 write_sysreg(lower_32_bits(val), a32lo);\
115 write_sysreg(upper_32_bits(val), a32hi);\
117 static inline u64 read_ ## a64(void) \
119 u64 val = read_sysreg(a32lo); \
121 val |= (u64)read_sysreg(a32hi) << 32; \
126 CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)
127 CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)
128 CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
129 CPUIF_MAP(ICH_EISR, ICH_EISR_EL2)
130 CPUIF_MAP(ICH_ELSR, ICH_ELSR_EL2)
131 CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2)
132 CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2)
133 CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2)
134 CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2)
135 CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2)
136 CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2)
137 CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2)
138 CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2)
139 CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2)
140 CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2)
141 CPUIF_MAP(ICC_SRE, ICC_SRE_EL1)
143 CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2)
144 CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2)
145 CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2)
146 CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2)
147 CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2)
148 CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2)
149 CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2)
150 CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2)
151 CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2)
152 CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2)
153 CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2)
154 CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2)
155 CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2)
156 CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2)
157 CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2)
158 CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2)
160 #define read_gicreg(r) read_##r()
161 #define write_gicreg(v, r) write_##r(v)
163 /* Low-level accessors */
165 static inline void gic_write_eoir(u32 irq)
167 write_sysreg(irq, ICC_EOIR1);
171 static inline void gic_write_dir(u32 val)
173 write_sysreg(val, ICC_DIR);
177 static inline u32 gic_read_iar(void)
179 u32 irqstat = read_sysreg(ICC_IAR1);
186 static inline void gic_write_pmr(u32 val)
188 write_sysreg(val, ICC_PMR);
191 static inline void gic_write_ctlr(u32 val)
193 write_sysreg(val, ICC_CTLR);
197 static inline void gic_write_grpen1(u32 val)
199 write_sysreg(val, ICC_IGRPEN1);
203 static inline void gic_write_sgi1r(u64 val)
205 write_sysreg(val, ICC_SGI1R);
208 static inline u32 gic_read_sre(void)
210 return read_sysreg(ICC_SRE);
213 static inline void gic_write_sre(u32 val)
215 write_sysreg(val, ICC_SRE);
219 static inline void gic_write_bpr1(u32 val)
221 #if defined(__write_sysreg) && defined(ICC_BPR1)
222 write_sysreg(val, ICC_BPR1);
224 asm volatile("mcr " __stringify(ICC_BPR1) : : "r" (val));
229 * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
230 * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
232 * Moreover, 64bit I/O emulation is extremely difficult to implement on
233 * AArch32, since the syndrome register doesn't provide any information for
235 * Consequently, the following IO helpers use 32bit accesses.
237 * There are only two registers that need 64bit accesses in this driver:
238 * - GICD_IROUTERn, contain the affinity values associated to each interrupt.
239 * The upper-word (aff3) will always be 0, so there is no need for a lock.
240 * - GICR_TYPER is an ID register and doesn't need atomicity.
242 static inline void gic_write_irouter(u64 val, volatile void __iomem *addr)
244 writel_relaxed((u32)val, addr);
245 writel_relaxed((u32)(val >> 32), addr + 4);
248 static inline u64 gic_read_typer(const volatile void __iomem *addr)
252 val = readl_relaxed(addr);
253 val |= (u64)readl_relaxed(addr + 4) << 32;
257 #endif /* !__ASSEMBLY__ */
258 #endif /* !__ASM_ARCH_GICV3_H */