arch/arm/include/asm/arch_gicv3.h

   1 /*
   2  * arch/arm/include/asm/arch_gicv3.h
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #ifndef __ASM_ARCH_GICV3_H
  19 #define __ASM_ARCH_GICV3_H
  20
  21 #ifndef __ASSEMBLY__
  22
  23 #include <linux/io.h>
  24 #include <asm/barrier.h>
  25 #include <asm/cp15.h>
  26
  27 #define ICC_EOIR1                       __ACCESS_CP15(c12, 0, c12, 1)
  28 #define ICC_DIR                         __ACCESS_CP15(c12, 0, c11, 1)
  29 #define ICC_IAR1                        __ACCESS_CP15(c12, 0, c12, 0)
  30 #define ICC_SGI1R                       __ACCESS_CP15_64(0, c12)
  31 #define ICC_PMR                         __ACCESS_CP15(c4, 0, c6, 0)
  32 #define ICC_CTLR                        __ACCESS_CP15(c12, 0, c12, 4)
  33 #define ICC_SRE                         __ACCESS_CP15(c12, 0, c12, 5)
  34 #define ICC_IGRPEN1                     __ACCESS_CP15(c12, 0, c12, 7)
  35
  36 #define ICC_HSRE                        __ACCESS_CP15(c12, 4, c9, 5)
  37
  38 #define ICH_VSEIR                       __ACCESS_CP15(c12, 4, c9, 4)
  39 #define ICH_HCR                         __ACCESS_CP15(c12, 4, c11, 0)
  40 #define ICH_VTR                         __ACCESS_CP15(c12, 4, c11, 1)
  41 #define ICH_MISR                        __ACCESS_CP15(c12, 4, c11, 2)
  42 #define ICH_EISR                        __ACCESS_CP15(c12, 4, c11, 3)
  43 #define ICH_ELSR                        __ACCESS_CP15(c12, 4, c11, 5)
  44 #define ICH_VMCR                        __ACCESS_CP15(c12, 4, c11, 7)
  45
  46 #define __LR0(x)                        __ACCESS_CP15(c12, 4, c12, x)
  47 #define __LR8(x)                        __ACCESS_CP15(c12, 4, c13, x)
  48
  49 #define ICH_LR0                         __LR0(0)
  50 #define ICH_LR1                         __LR0(1)
  51 #define ICH_LR2                         __LR0(2)
  52 #define ICH_LR3                         __LR0(3)
  53 #define ICH_LR4                         __LR0(4)
  54 #define ICH_LR5                         __LR0(5)
  55 #define ICH_LR6                         __LR0(6)
  56 #define ICH_LR7                         __LR0(7)
  57 #define ICH_LR8                         __LR8(0)
  58 #define ICH_LR9                         __LR8(1)
  59 #define ICH_LR10                        __LR8(2)
  60 #define ICH_LR11                        __LR8(3)
  61 #define ICH_LR12                        __LR8(4)
  62 #define ICH_LR13                        __LR8(5)
  63 #define ICH_LR14                        __LR8(6)
  64 #define ICH_LR15                        __LR8(7)
  65
  66 /* LR top half */
  67 #define __LRC0(x)                       __ACCESS_CP15(c12, 4, c14, x)
  68 #define __LRC8(x)                       __ACCESS_CP15(c12, 4, c15, x)
  69
  70 #define ICH_LRC0                        __LRC0(0)
  71 #define ICH_LRC1                        __LRC0(1)
  72 #define ICH_LRC2                        __LRC0(2)
  73 #define ICH_LRC3                        __LRC0(3)
  74 #define ICH_LRC4                        __LRC0(4)
  75 #define ICH_LRC5                        __LRC0(5)
  76 #define ICH_LRC6                        __LRC0(6)
  77 #define ICH_LRC7                        __LRC0(7)
  78 #define ICH_LRC8                        __LRC8(0)
  79 #define ICH_LRC9                        __LRC8(1)
  80 #define ICH_LRC10                       __LRC8(2)
  81 #define ICH_LRC11                       __LRC8(3)
  82 #define ICH_LRC12                       __LRC8(4)
  83 #define ICH_LRC13                       __LRC8(5)
  84 #define ICH_LRC14                       __LRC8(6)
  85 #define ICH_LRC15                       __LRC8(7)
  86
  87 #define __AP0Rx(x)                      __ACCESS_CP15(c12, 4, c8, x)
  88 #define ICH_AP0R0                       __AP0Rx(0)
  89 #define ICH_AP0R1                       __AP0Rx(1)
  90 #define ICH_AP0R2                       __AP0Rx(2)
  91 #define ICH_AP0R3                       __AP0Rx(3)
  92
  93 #define __AP1Rx(x)                      __ACCESS_CP15(c12, 4, c9, x)
  94 #define ICH_AP1R0                       __AP1Rx(0)
  95 #define ICH_AP1R1                       __AP1Rx(1)
  96 #define ICH_AP1R2                       __AP1Rx(2)
  97 #define ICH_AP1R3                       __AP1Rx(3)
  98
  99 /* Low-level accessors */
 100
 101 static inline void gic_write_eoir(u32 irq)
 102 {
 103         write_sysreg(irq, ICC_EOIR1);
 104         isb();
 105 }
 106
 107 static inline void gic_write_dir(u32 val)
 108 {
 109         write_sysreg(val, ICC_DIR);
 110         isb();
 111 }
 112
 113 static inline u32 gic_read_iar(void)
 114 {
 115         u32 irqstat = read_sysreg(ICC_IAR1);
 116
 117         dsb(sy);
 118
 119         return irqstat;
 120 }
 121
 122 static inline void gic_write_pmr(u32 val)
 123 {
 124         write_sysreg(val, ICC_PMR);
 125 }
 126
 127 static inline void gic_write_ctlr(u32 val)
 128 {
 129         write_sysreg(val, ICC_CTLR);
 130         isb();
 131 }
 132
 133 static inline void gic_write_grpen1(u32 val)
 134 {
 135         write_sysreg(val, ICC_IGRPEN1);
 136         isb();
 137 }
 138
 139 static inline void gic_write_sgi1r(u64 val)
 140 {
 141         write_sysreg(val, ICC_SGI1R);
 142 }
 143
 144 static inline u32 gic_read_sre(void)
 145 {
 146         return read_sysreg(ICC_SRE);
 147 }
 148
 149 static inline void gic_write_sre(u32 val)
 150 {
 151         write_sysreg(val, ICC_SRE);
 152         isb();
 153 }
 154
 155 /*
 156  * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
 157  * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
 158  * make much sense.
 159  * Moreover, 64bit I/O emulation is extremely difficult to implement on
 160  * AArch32, since the syndrome register doesn't provide any information for
 161  * them.
 162  * Consequently, the following IO helpers use 32bit accesses.
 163  *
 164  * There are only two registers that need 64bit accesses in this driver:
 165  * - GICD_IROUTERn, contain the affinity values associated to each interrupt.
 166  *   The upper-word (aff3) will always be 0, so there is no need for a lock.
 167  * - GICR_TYPER is an ID register and doesn't need atomicity.
 168  */
 169 static inline void gic_write_irouter(u64 val, volatile void __iomem *addr)
 170 {
 171         writel_relaxed((u32)val, addr);
 172         writel_relaxed((u32)(val >> 32), addr + 4);
 173 }
 174
 175 static inline u64 gic_read_typer(const volatile void __iomem *addr)
 176 {
 177         u64 val;
 178
 179         val = readl_relaxed(addr);
 180         val |= (u64)readl_relaxed(addr + 4) << 32;
 181         return val;
 182 }
 183
 184 #endif /* !__ASSEMBLY__ */
 185 #endif /* !__ASM_ARCH_GICV3_H */