arch/arm/include/asm/cputype.h

   1 #ifndef __ASM_ARM_CPUTYPE_H
   2 #define __ASM_ARM_CPUTYPE_H
   3
   4 #include <linux/stringify.h>
   5 #include <linux/kernel.h>
   6
   7 #define CPUID_ID        0
   8 #define CPUID_CACHETYPE 1
   9 #define CPUID_TCM       2
  10 #define CPUID_TLBTYPE   3
  11 #define CPUID_MPUIR     4
  12 #define CPUID_MPIDR     5
  13 #define CPUID_REVIDR    6
  14
  15 #ifdef CONFIG_CPU_V7M
  16 #define CPUID_EXT_PFR0  0x40
  17 #define CPUID_EXT_PFR1  0x44
  18 #define CPUID_EXT_DFR0  0x48
  19 #define CPUID_EXT_AFR0  0x4c
  20 #define CPUID_EXT_MMFR0 0x50
  21 #define CPUID_EXT_MMFR1 0x54
  22 #define CPUID_EXT_MMFR2 0x58
  23 #define CPUID_EXT_MMFR3 0x5c
  24 #define CPUID_EXT_ISAR0 0x60
  25 #define CPUID_EXT_ISAR1 0x64
  26 #define CPUID_EXT_ISAR2 0x68
  27 #define CPUID_EXT_ISAR3 0x6c
  28 #define CPUID_EXT_ISAR4 0x70
  29 #define CPUID_EXT_ISAR5 0x74
  30 #else
  31 #define CPUID_EXT_PFR0  "c1, 0"
  32 #define CPUID_EXT_PFR1  "c1, 1"
  33 #define CPUID_EXT_DFR0  "c1, 2"
  34 #define CPUID_EXT_AFR0  "c1, 3"
  35 #define CPUID_EXT_MMFR0 "c1, 4"
  36 #define CPUID_EXT_MMFR1 "c1, 5"
  37 #define CPUID_EXT_MMFR2 "c1, 6"
  38 #define CPUID_EXT_MMFR3 "c1, 7"
  39 #define CPUID_EXT_ISAR0 "c2, 0"
  40 #define CPUID_EXT_ISAR1 "c2, 1"
  41 #define CPUID_EXT_ISAR2 "c2, 2"
  42 #define CPUID_EXT_ISAR3 "c2, 3"
  43 #define CPUID_EXT_ISAR4 "c2, 4"
  44 #define CPUID_EXT_ISAR5 "c2, 5"
  45 #endif
  46
  47 #define MPIDR_SMP_BITMASK (0x3 << 30)
  48 #define MPIDR_SMP_VALUE (0x2 << 30)
  49
  50 #define MPIDR_MT_BITMASK (0x1 << 24)
  51
  52 #define MPIDR_HWID_BITMASK 0xFFFFFF
  53
  54 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
  55
  56 #define MPIDR_LEVEL_BITS 8
  57 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
  58 #define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level)
  59
  60 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  61         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
  62
  63 #define ARM_CPU_IMP_ARM                 0x41
  64 #define ARM_CPU_IMP_INTEL               0x69
  65
  66 /* ARM implemented processors */
  67 #define ARM_CPU_PART_ARM1136            0x4100b360
  68 #define ARM_CPU_PART_ARM1156            0x4100b560
  69 #define ARM_CPU_PART_ARM1176            0x4100b760
  70 #define ARM_CPU_PART_ARM11MPCORE        0x4100b020
  71 #define ARM_CPU_PART_CORTEX_A8          0x4100c080
  72 #define ARM_CPU_PART_CORTEX_A9          0x4100c090
  73 #define ARM_CPU_PART_CORTEX_A5          0x4100c050
  74 #define ARM_CPU_PART_CORTEX_A7          0x4100c070
  75 #define ARM_CPU_PART_CORTEX_A12         0x4100c0d0
  76 #define ARM_CPU_PART_CORTEX_A17         0x4100c0e0
  77 #define ARM_CPU_PART_CORTEX_A15         0x4100c0f0
  78 #define ARM_CPU_PART_MASK               0xff00fff0
  79
  80 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
  81 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
  82 #define ARM_CPU_XSCALE_ARCH_V2          0x4000
  83 #define ARM_CPU_XSCALE_ARCH_V3          0x6000
  84
  85 extern unsigned int processor_id;
  86
  87 #ifdef CONFIG_CPU_CP15
  88 #define read_cpuid(reg)                                                 \
  89         ({                                                              \
  90                 unsigned int __val;                                     \
  91                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
  92                     : "=r" (__val)                                      \
  93                     :                                                   \
  94                     : "cc");                                            \
  95                 __val;                                                  \
  96         })
  97
  98 /*
  99  * The memory clobber prevents gcc 4.5 from reordering the mrc before
 100  * any is_smp() tests, which can cause undefined instruction aborts on
 101  * ARM1136 r0 due to the missing extended CP15 registers.
 102  */
 103 #define read_cpuid_ext(ext_reg)                                         \
 104         ({                                                              \
 105                 unsigned int __val;                                     \
 106                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
 107                     : "=r" (__val)                                      \
 108                     :                                                   \
 109                     : "memory");                                        \
 110                 __val;                                                  \
 111         })
 112
 113 #elif defined(CONFIG_CPU_V7M)
 114
 115 #include <asm/io.h>
 116 #include <asm/v7m.h>
 117
 118 #define read_cpuid(reg)                                                 \
 119         ({                                                              \
 120                 WARN_ON_ONCE(1);                                        \
 121                 0;                                                      \
 122         })
 123
 124 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
 125 {
 126         return readl(BASEADDR_V7M_SCB + offset);
 127 }
 128
 129 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 130
 131 /*
 132  * read_cpuid and read_cpuid_ext should only ever be called on machines that
 133  * have cp15 so warn on other usages.
 134  */
 135 #define read_cpuid(reg)                                                 \
 136         ({                                                              \
 137                 WARN_ON_ONCE(1);                                        \
 138                 0;                                                      \
 139         })
 140
 141 #define read_cpuid_ext(reg) read_cpuid(reg)
 142
 143 #endif /* ifdef CONFIG_CPU_CP15 / else */
 144
 145 #ifdef CONFIG_CPU_CP15
 146 /*
 147  * The CPU ID never changes at run time, so we might as well tell the
 148  * compiler that it's constant.  Use this function to read the CPU ID
 149  * rather than directly reading processor_id or read_cpuid() directly.
 150  */
 151 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 152 {
 153         return read_cpuid(CPUID_ID);
 154 }
 155
 156 #elif defined(CONFIG_CPU_V7M)
 157
 158 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 159 {
 160         return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
 161 }
 162
 163 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 164
 165 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 166 {
 167         return processor_id;
 168 }
 169
 170 #endif /* ifdef CONFIG_CPU_CP15 / else */
 171
 172 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 173 {
 174         return (read_cpuid_id() & 0xFF000000) >> 24;
 175 }
 176
 177 /*
 178  * The CPU part number is meaningless without referring to the CPU
 179  * implementer: implementers are free to define their own part numbers
 180  * which are permitted to clash with other implementer part numbers.
 181  */
 182 static inline unsigned int __attribute_const__ read_cpuid_part(void)
 183 {
 184         return read_cpuid_id() & ARM_CPU_PART_MASK;
 185 }
 186
 187 static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
 188 {
 189         return read_cpuid_id() & 0xFFF0;
 190 }
 191
 192 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 193 {
 194         return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
 195 }
 196
 197 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 198 {
 199         return read_cpuid(CPUID_CACHETYPE);
 200 }
 201
 202 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 203 {
 204         return read_cpuid(CPUID_TCM);
 205 }
 206
 207 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
 208 {
 209         return read_cpuid(CPUID_MPIDR);
 210 }
 211
 212 /*
 213  * Intel's XScale3 core supports some v6 features (supersections, L2)
 214  * but advertises itself as v5 as it does not support the v6 ISA.  For
 215  * this reason, we need a way to explicitly test for this type of CPU.
 216  */
 217 #ifndef CONFIG_CPU_XSC3
 218 #define cpu_is_xsc3()   0
 219 #else
 220 static inline int cpu_is_xsc3(void)
 221 {
 222         unsigned int id;
 223         id = read_cpuid_id() & 0xffffe000;
 224         /* It covers both Intel ID and Marvell ID */
 225         if ((id == 0x69056000) || (id == 0x56056000))
 226                 return 1;
 227
 228         return 0;
 229 }
 230 #endif
 231
 232 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
 233     !defined(CONFIG_CPU_MOHAWK)
 234 #define cpu_is_xscale_family() 0
 235 #else
 236 static inline int cpu_is_xscale_family(void)
 237 {
 238         unsigned int id;
 239         id = read_cpuid_id() & 0xffffe000;
 240
 241         switch (id) {
 242         case 0x69052000: /* Intel XScale 1 */
 243         case 0x69054000: /* Intel XScale 2 */
 244         case 0x69056000: /* Intel XScale 3 */
 245         case 0x56056000: /* Marvell XScale 3 */
 246         case 0x56158000: /* Marvell Mohawk */
 247                 return 1;
 248         }
 249
 250         return 0;
 251 }
 252 #endif
 253
 254 /*
 255  * Marvell's PJ4 and PJ4B cores are based on V7 version,
 256  * but require a specical sequence for enabling coprocessors.
 257  * For this reason, we need a way to distinguish them.
 258  */
 259 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 260 static inline int cpu_is_pj4(void)
 261 {
 262         unsigned int id;
 263
 264         id = read_cpuid_id();
 265         if ((id & 0xff0fff00) == 0x560f5800)
 266                 return 1;
 267
 268         return 0;
 269 }
 270 #else
 271 #define cpu_is_pj4()    0
 272 #endif
 273
 274 static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
 275                                                                   int field)
 276 {
 277         int feature = (features >> field) & 15;
 278
 279         /* feature registers are signed values */
 280         if (feature > 7)
 281                 feature -= 16;
 282
 283         return feature;
 284 }
 285
 286 #define cpuid_feature_extract(reg, field) \
 287         cpuid_feature_extract_field(read_cpuid_ext(reg), field)
 288
 289 #endif