arch/arm/mach-davinci/board-mityomapl138.c

   1 /*
   2  * Critical Link MityOMAP-L138 SoM
   3  *
   4  * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of
   8  * any kind, whether express or implied.
   9  */
  10
  11 #define pr_fmt(fmt) "MityOMAPL138: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/console.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/mtd/partitions.h>
  18 #include <linux/regulator/machine.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_data/at24.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/flash.h>
  24
  25 #include <asm/io.h>
  26 #include <asm/mach-types.h>
  27 #include <asm/mach/arch.h>
  28 #include <mach/common.h>
  29 #include "cp_intc.h"
  30 #include <mach/da8xx.h>
  31 #include <linux/platform_data/mtd-davinci.h>
  32 #include <linux/platform_data/mtd-davinci-aemif.h>
  33 #include <mach/mux.h>
  34 #include <linux/platform_data/spi-davinci.h>
  35
  36 #define MITYOMAPL138_PHY_ID             ""
  37
  38 #define FACTORY_CONFIG_MAGIC    0x012C0138
  39 #define FACTORY_CONFIG_VERSION  0x00010001
  40
  41 /* Data Held in On-Board I2C device */
  42 struct factory_config {
  43         u32     magic;
  44         u32     version;
  45         u8      mac[6];
  46         u32     fpga_type;
  47         u32     spare;
  48         u32     serialnumber;
  49         char    partnum[32];
  50 };
  51
  52 static struct factory_config factory_config;
  53
  54 #ifdef CONFIG_CPU_FREQ
  55 struct part_no_info {
  56         const char      *part_no;       /* part number string of interest */
  57         int             max_freq;       /* khz */
  58 };
  59
  60 static struct part_no_info mityomapl138_pn_info[] = {
  61         {
  62                 .part_no        = "L138-C",
  63                 .max_freq       = 300000,
  64         },
  65         {
  66                 .part_no        = "L138-D",
  67                 .max_freq       = 375000,
  68         },
  69         {
  70                 .part_no        = "L138-F",
  71                 .max_freq       = 456000,
  72         },
  73         {
  74                 .part_no        = "1808-C",
  75                 .max_freq       = 300000,
  76         },
  77         {
  78                 .part_no        = "1808-D",
  79                 .max_freq       = 375000,
  80         },
  81         {
  82                 .part_no        = "1808-F",
  83                 .max_freq       = 456000,
  84         },
  85         {
  86                 .part_no        = "1810-D",
  87                 .max_freq       = 375000,
  88         },
  89 };
  90
  91 static void mityomapl138_cpufreq_init(const char *partnum)
  92 {
  93         int i, ret;
  94
  95         for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
  96                 /*
  97                  * the part number has additional characters beyond what is
  98                  * stored in the table.  This information is not needed for
  99                  * determining the speed grade, and would require several
 100                  * more table entries.  Only check the first N characters
 101                  * for a match.
 102                  */
 103                 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
 104                              strlen(mityomapl138_pn_info[i].part_no))) {
 105                         da850_max_speed = mityomapl138_pn_info[i].max_freq;
 106                         break;
 107                 }
 108         }
 109
 110         ret = da850_register_cpufreq("pll0_sysclk3");
 111         if (ret)
 112                 pr_warn("cpufreq registration failed: %d\n", ret);
 113 }
 114 #else
 115 static void mityomapl138_cpufreq_init(const char *partnum) { }
 116 #endif
 117
 118 static void read_factory_config(struct nvmem_device *nvmem, void *context)
 119 {
 120         int ret;
 121         const char *partnum = NULL;
 122         struct davinci_soc_info *soc_info = &davinci_soc_info;
 123
 124         ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
 125                                 &factory_config);
 126         if (ret != sizeof(struct factory_config)) {
 127                 pr_warn("Read Factory Config Failed: %d\n", ret);
 128                 goto bad_config;
 129         }
 130
 131         if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
 132                 pr_warn("Factory Config Magic Wrong (%X)\n",
 133                         factory_config.magic);
 134                 goto bad_config;
 135         }
 136
 137         if (factory_config.version != FACTORY_CONFIG_VERSION) {
 138                 pr_warn("Factory Config Version Wrong (%X)\n",
 139                         factory_config.version);
 140                 goto bad_config;
 141         }
 142
 143         pr_info("Found MAC = %pM\n", factory_config.mac);
 144         if (is_valid_ether_addr(factory_config.mac))
 145                 memcpy(soc_info->emac_pdata->mac_addr,
 146                         factory_config.mac, ETH_ALEN);
 147         else
 148                 pr_warn("Invalid MAC found in factory config block\n");
 149
 150         partnum = factory_config.partnum;
 151         pr_info("Part Number = %s\n", partnum);
 152
 153 bad_config:
 154         /* default maximum speed is valid for all platforms */
 155         mityomapl138_cpufreq_init(partnum);
 156 }
 157
 158 static struct at24_platform_data mityomapl138_fd_chip = {
 159         .byte_len       = 256,
 160         .page_size      = 8,
 161         .flags          = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
 162         .setup          = read_factory_config,
 163         .context        = NULL,
 164 };
 165
 166 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
 167         .bus_freq       = 100,  /* kHz */
 168         .bus_delay      = 0,    /* usec */
 169 };
 170
 171 /* TPS65023 voltage regulator support */
 172 /* 1.2V Core */
 173 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
 174         {
 175                 .supply = "cvdd",
 176         },
 177 };
 178
 179 /* 1.8V */
 180 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
 181         {
 182                 .supply = "usb0_vdda18",
 183         },
 184         {
 185                 .supply = "usb1_vdda18",
 186         },
 187         {
 188                 .supply = "ddr_dvdd18",
 189         },
 190         {
 191                 .supply = "sata_vddr",
 192         },
 193 };
 194
 195 /* 1.2V */
 196 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
 197         {
 198                 .supply = "sata_vdd",
 199         },
 200         {
 201                 .supply = "usb_cvdd",
 202         },
 203         {
 204                 .supply = "pll0_vdda",
 205         },
 206         {
 207                 .supply = "pll1_vdda",
 208         },
 209 };
 210
 211 /* 1.8V Aux LDO, not used */
 212 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
 213         {
 214                 .supply = "1.8v_aux",
 215         },
 216 };
 217
 218 /* FPGA VCC Aux (2.5 or 3.3) LDO */
 219 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
 220         {
 221                 .supply = "vccaux",
 222         },
 223 };
 224
 225 static struct regulator_init_data tps65023_regulator_data[] = {
 226         /* dcdc1 */
 227         {
 228                 .constraints = {
 229                         .min_uV = 1150000,
 230                         .max_uV = 1350000,
 231                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 232                                           REGULATOR_CHANGE_STATUS,
 233                         .boot_on = 1,
 234                 },
 235                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
 236                 .consumer_supplies = tps65023_dcdc1_consumers,
 237         },
 238         /* dcdc2 */
 239         {
 240                 .constraints = {
 241                         .min_uV = 1800000,
 242                         .max_uV = 1800000,
 243                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 244                         .boot_on = 1,
 245                 },
 246                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
 247                 .consumer_supplies = tps65023_dcdc2_consumers,
 248         },
 249         /* dcdc3 */
 250         {
 251                 .constraints = {
 252                         .min_uV = 1200000,
 253                         .max_uV = 1200000,
 254                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 255                         .boot_on = 1,
 256                 },
 257                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
 258                 .consumer_supplies = tps65023_dcdc3_consumers,
 259         },
 260         /* ldo1 */
 261         {
 262                 .constraints = {
 263                         .min_uV = 1800000,
 264                         .max_uV = 1800000,
 265                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 266                         .boot_on = 1,
 267                 },
 268                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
 269                 .consumer_supplies = tps65023_ldo1_consumers,
 270         },
 271         /* ldo2 */
 272         {
 273                 .constraints = {
 274                         .min_uV = 2500000,
 275                         .max_uV = 3300000,
 276                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 277                                           REGULATOR_CHANGE_STATUS,
 278                         .boot_on = 1,
 279                 },
 280                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
 281                 .consumer_supplies = tps65023_ldo2_consumers,
 282         },
 283 };
 284
 285 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
 286         {
 287                 I2C_BOARD_INFO("tps65023", 0x48),
 288                 .platform_data = &tps65023_regulator_data[0],
 289         },
 290         {
 291                 I2C_BOARD_INFO("24c02", 0x50),
 292                 .platform_data = &mityomapl138_fd_chip,
 293         },
 294 };
 295
 296 static int __init pmic_tps65023_init(void)
 297 {
 298         return i2c_register_board_info(1, mityomap_tps65023_info,
 299                                         ARRAY_SIZE(mityomap_tps65023_info));
 300 }
 301
 302 /*
 303  * SPI Devices:
 304  *      SPI1_CS0: 8M Flash ST-M25P64-VME6G
 305  */
 306 static struct mtd_partition spi_flash_partitions[] = {
 307         [0] = {
 308                 .name           = "ubl",
 309                 .offset         = 0,
 310                 .size           = SZ_64K,
 311                 .mask_flags     = MTD_WRITEABLE,
 312         },
 313         [1] = {
 314                 .name           = "u-boot",
 315                 .offset         = MTDPART_OFS_APPEND,
 316                 .size           = SZ_512K,
 317                 .mask_flags     = MTD_WRITEABLE,
 318         },
 319         [2] = {
 320                 .name           = "u-boot-env",
 321                 .offset         = MTDPART_OFS_APPEND,
 322                 .size           = SZ_64K,
 323                 .mask_flags     = MTD_WRITEABLE,
 324         },
 325         [3] = {
 326                 .name           = "periph-config",
 327                 .offset         = MTDPART_OFS_APPEND,
 328                 .size           = SZ_64K,
 329                 .mask_flags     = MTD_WRITEABLE,
 330         },
 331         [4] = {
 332                 .name           = "reserved",
 333                 .offset         = MTDPART_OFS_APPEND,
 334                 .size           = SZ_256K + SZ_64K,
 335         },
 336         [5] = {
 337                 .name           = "kernel",
 338                 .offset         = MTDPART_OFS_APPEND,
 339                 .size           = SZ_2M + SZ_1M,
 340         },
 341         [6] = {
 342                 .name           = "fpga",
 343                 .offset         = MTDPART_OFS_APPEND,
 344                 .size           = SZ_2M,
 345         },
 346         [7] = {
 347                 .name           = "spare",
 348                 .offset         = MTDPART_OFS_APPEND,
 349                 .size           = MTDPART_SIZ_FULL,
 350         },
 351 };
 352
 353 static struct flash_platform_data mityomapl138_spi_flash_data = {
 354         .name           = "m25p80",
 355         .parts          = spi_flash_partitions,
 356         .nr_parts       = ARRAY_SIZE(spi_flash_partitions),
 357         .type           = "m24p64",
 358 };
 359
 360 static struct davinci_spi_config spi_eprom_config = {
 361         .io_type        = SPI_IO_TYPE_DMA,
 362         .c2tdelay       = 8,
 363         .t2cdelay       = 8,
 364 };
 365
 366 static struct spi_board_info mityomapl138_spi_flash_info[] = {
 367         {
 368                 .modalias               = "m25p80",
 369                 .platform_data          = &mityomapl138_spi_flash_data,
 370                 .controller_data        = &spi_eprom_config,
 371                 .mode                   = SPI_MODE_0,
 372                 .max_speed_hz           = 30000000,
 373                 .bus_num                = 1,
 374                 .chip_select            = 0,
 375         },
 376 };
 377
 378 /*
 379  * MityDSP-L138 includes a 256 MByte large-page NAND flash
 380  * (128K blocks).
 381  */
 382 static struct mtd_partition mityomapl138_nandflash_partition[] = {
 383         {
 384                 .name           = "rootfs",
 385                 .offset         = 0,
 386                 .size           = SZ_128M,
 387                 .mask_flags     = 0, /* MTD_WRITEABLE, */
 388         },
 389         {
 390                 .name           = "homefs",
 391                 .offset         = MTDPART_OFS_APPEND,
 392                 .size           = MTDPART_SIZ_FULL,
 393                 .mask_flags     = 0,
 394         },
 395 };
 396
 397 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
 398         .parts          = mityomapl138_nandflash_partition,
 399         .nr_parts       = ARRAY_SIZE(mityomapl138_nandflash_partition),
 400         .ecc_mode       = NAND_ECC_HW,
 401         .bbt_options    = NAND_BBT_USE_FLASH,
 402         .options        = NAND_BUSWIDTH_16,
 403         .ecc_bits       = 1, /* 4 bit mode is not supported with 16 bit NAND */
 404 };
 405
 406 static struct resource mityomapl138_nandflash_resource[] = {
 407         {
 408                 .start  = DA8XX_AEMIF_CS3_BASE,
 409                 .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
 410                 .flags  = IORESOURCE_MEM,
 411         },
 412         {
 413                 .start  = DA8XX_AEMIF_CTL_BASE,
 414                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
 415                 .flags  = IORESOURCE_MEM,
 416         },
 417 };
 418
 419 static struct platform_device mityomapl138_nandflash_device = {
 420         .name           = "davinci_nand",
 421         .id             = 1,
 422         .dev            = {
 423                 .platform_data  = &mityomapl138_nandflash_data,
 424         },
 425         .num_resources  = ARRAY_SIZE(mityomapl138_nandflash_resource),
 426         .resource       = mityomapl138_nandflash_resource,
 427 };
 428
 429 static struct platform_device *mityomapl138_devices[] __initdata = {
 430         &mityomapl138_nandflash_device,
 431 };
 432
 433 static void __init mityomapl138_setup_nand(void)
 434 {
 435         platform_add_devices(mityomapl138_devices,
 436                                  ARRAY_SIZE(mityomapl138_devices));
 437
 438         if (davinci_aemif_setup(&mityomapl138_nandflash_device))
 439                 pr_warn("%s: Cannot configure AEMIF\n", __func__);
 440 }
 441
 442 static const short mityomap_mii_pins[] = {
 443         DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
 444         DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
 445         DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
 446         DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
 447         DA850_MDIO_D,
 448         -1
 449 };
 450
 451 static const short mityomap_rmii_pins[] = {
 452         DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
 453         DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
 454         DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
 455         DA850_MDIO_D,
 456         -1
 457 };
 458
 459 static void __init mityomapl138_config_emac(void)
 460 {
 461         void __iomem *cfg_chip3_base;
 462         int ret;
 463         u32 val;
 464         struct davinci_soc_info *soc_info = &davinci_soc_info;
 465
 466         soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
 467
 468         cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
 469         val = __raw_readl(cfg_chip3_base);
 470
 471         if (soc_info->emac_pdata->rmii_en) {
 472                 val |= BIT(8);
 473                 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
 474                 pr_info("RMII PHY configured\n");
 475         } else {
 476                 val &= ~BIT(8);
 477                 ret = davinci_cfg_reg_list(mityomap_mii_pins);
 478                 pr_info("MII PHY configured\n");
 479         }
 480
 481         if (ret) {
 482                 pr_warn("mii/rmii mux setup failed: %d\n", ret);
 483                 return;
 484         }
 485
 486         /* configure the CFGCHIP3 register for RMII or MII */
 487         __raw_writel(val, cfg_chip3_base);
 488
 489         soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
 490
 491         ret = da8xx_register_emac();
 492         if (ret)
 493                 pr_warn("emac registration failed: %d\n", ret);
 494 }
 495
 496 static struct davinci_pm_config da850_pm_pdata = {
 497         .sleepcount = 128,
 498 };
 499
 500 static struct platform_device da850_pm_device = {
 501         .name   = "pm-davinci",
 502         .dev = {
 503                 .platform_data  = &da850_pm_pdata,
 504         },
 505         .id     = -1,
 506 };
 507
 508 static void __init mityomapl138_init(void)
 509 {
 510         int ret;
 511
 512         /* for now, no special EDMA channels are reserved */
 513         ret = da850_register_edma(NULL);
 514         if (ret)
 515                 pr_warn("edma registration failed: %d\n", ret);
 516
 517         ret = da8xx_register_watchdog();
 518         if (ret)
 519                 pr_warn("watchdog registration failed: %d\n", ret);
 520
 521         davinci_serial_init(da8xx_serial_device);
 522
 523         ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
 524         if (ret)
 525                 pr_warn("i2c0 registration failed: %d\n", ret);
 526
 527         ret = pmic_tps65023_init();
 528         if (ret)
 529                 pr_warn("TPS65023 PMIC init failed: %d\n", ret);
 530
 531         mityomapl138_setup_nand();
 532
 533         ret = spi_register_board_info(mityomapl138_spi_flash_info,
 534                                       ARRAY_SIZE(mityomapl138_spi_flash_info));
 535         if (ret)
 536                 pr_warn("spi info registration failed: %d\n", ret);
 537
 538         ret = da8xx_register_spi_bus(1,
 539                                      ARRAY_SIZE(mityomapl138_spi_flash_info));
 540         if (ret)
 541                 pr_warn("spi 1 registration failed: %d\n", ret);
 542
 543         mityomapl138_config_emac();
 544
 545         ret = da8xx_register_rtc();
 546         if (ret)
 547                 pr_warn("rtc setup failed: %d\n", ret);
 548
 549         ret = da8xx_register_cpuidle();
 550         if (ret)
 551                 pr_warn("cpuidle registration failed: %d\n", ret);
 552
 553         ret = da850_register_pm(&da850_pm_device);
 554         if (ret)
 555                 pr_warn("suspend registration failed: %d\n", ret);
 556 }
 557
 558 #ifdef CONFIG_SERIAL_8250_CONSOLE
 559 static int __init mityomapl138_console_init(void)
 560 {
 561         if (!machine_is_mityomapl138())
 562                 return 0;
 563
 564         return add_preferred_console("ttyS", 1, "115200");
 565 }
 566 console_initcall(mityomapl138_console_init);
 567 #endif
 568
 569 static void __init mityomapl138_map_io(void)
 570 {
 571         da850_init();
 572 }
 573
 574 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
 575         .atag_offset    = 0x100,
 576         .map_io         = mityomapl138_map_io,
 577         .init_irq       = cp_intc_init,
 578         .init_time      = davinci_timer_init,
 579         .init_machine   = mityomapl138_init,
 580         .init_late      = davinci_init_late,
 581         .dma_zone_size  = SZ_128M,
 582         .restart        = da8xx_restart,
 583 MACHINE_END