arch/arm/mach-exynos/clock-exynos4.c

   1 /*
   2  * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS4 - Clock support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/syscore_ops.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23 #include <plat/pm.h>
  24
  25 #include <mach/map.h>
  26 #include <mach/regs-clock.h>
  27 #include <mach/sysmmu.h>
  28
  29 #include "common.h"
  30 #include "clock-exynos4.h"
  31
  32 #ifdef CONFIG_PM_SLEEP
  33 static struct sleep_save exynos4_clock_save[] = {
  34         SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
  35         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
  36         SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
  37         SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
  38         SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
  39         SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
  40         SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
  41         SAVE_ITEM(EXYNOS4_CLKSRC_TV),
  42         SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
  43         SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
  44         SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
  45         SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
  46         SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
  47         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
  48         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
  49         SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
  50         SAVE_ITEM(EXYNOS4_CLKDIV_TV),
  51         SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
  52         SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
  53         SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
  54         SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
  55         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
  56         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
  57         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
  58         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
  59         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
  60         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
  61         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
  62         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
  63         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
  64         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
  65         SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
  66         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
  67         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
  68         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
  69         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
  70         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
  71         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
  72         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
  73         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
  74         SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
  75         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
  76         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
  77         SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
  78         SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
  79         SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
  80         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
  81         SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
  82         SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
  83         SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
  84         SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
  85         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
  86         SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
  87         SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
  88         SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
  89         SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
  90         SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
  91         SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
  92         SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
  93         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
  94         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
  95 };
  96 #endif
  97
  98 static struct clk exynos4_clk_sclk_hdmi27m = {
  99         .name           = "sclk_hdmi27m",
 100         .rate           = 27000000,
 101 };
 102
 103 static struct clk exynos4_clk_sclk_hdmiphy = {
 104         .name           = "sclk_hdmiphy",
 105 };
 106
 107 static struct clk exynos4_clk_sclk_usbphy0 = {
 108         .name           = "sclk_usbphy0",
 109         .rate           = 27000000,
 110 };
 111
 112 static struct clk exynos4_clk_sclk_usbphy1 = {
 113         .name           = "sclk_usbphy1",
 114 };
 115
 116 static struct clk dummy_apb_pclk = {
 117         .name           = "apb_pclk",
 118         .id             = -1,
 119 };
 120
 121 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 122 {
 123         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
 124 }
 125
 126 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
 127 {
 128         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
 129 }
 130
 131 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
 132 {
 133         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
 134 }
 135
 136 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 137 {
 138         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
 139 }
 140
 141 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 142 {
 143         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
 144 }
 145
 146 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
 147 {
 148         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
 149 }
 150
 151 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 152 {
 153         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
 154 }
 155
 156 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
 157 {
 158         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
 159 }
 160
 161 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 162 {
 163         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
 164 }
 165
 166 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 167 {
 168         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
 169 }
 170
 171 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 172 {
 173         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
 174 }
 175
 176 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 177 {
 178         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
 179 }
 180
 181 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 182 {
 183         return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
 184 }
 185
 186 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 187 {
 188         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
 189 }
 190
 191 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 192 {
 193         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
 194 }
 195
 196 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 197 {
 198         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
 199 }
 200
 201 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 202 {
 203         return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
 204 }
 205
 206 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
 207 {
 208         return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
 209 }
 210
 211 /* Core list of CMU_CPU side */
 212
 213 static struct clksrc_clk exynos4_clk_mout_apll = {
 214         .clk    = {
 215                 .name           = "mout_apll",
 216         },
 217         .sources = &clk_src_apll,
 218         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
 219 };
 220
 221 static struct clksrc_clk exynos4_clk_sclk_apll = {
 222         .clk    = {
 223                 .name           = "sclk_apll",
 224                 .parent         = &exynos4_clk_mout_apll.clk,
 225         },
 226         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
 227 };
 228
 229 static struct clksrc_clk exynos4_clk_mout_epll = {
 230         .clk    = {
 231                 .name           = "mout_epll",
 232         },
 233         .sources = &clk_src_epll,
 234         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
 235 };
 236
 237 struct clksrc_clk exynos4_clk_mout_mpll = {
 238         .clk    = {
 239                 .name           = "mout_mpll",
 240         },
 241         .sources = &clk_src_mpll,
 242
 243         /* reg_src will be added in each SoCs' clock */
 244 };
 245
 246 static struct clk *exynos4_clkset_moutcore_list[] = {
 247         [0] = &exynos4_clk_mout_apll.clk,
 248         [1] = &exynos4_clk_mout_mpll.clk,
 249 };
 250
 251 static struct clksrc_sources exynos4_clkset_moutcore = {
 252         .sources        = exynos4_clkset_moutcore_list,
 253         .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
 254 };
 255
 256 static struct clksrc_clk exynos4_clk_moutcore = {
 257         .clk    = {
 258                 .name           = "moutcore",
 259         },
 260         .sources = &exynos4_clkset_moutcore,
 261         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
 262 };
 263
 264 static struct clksrc_clk exynos4_clk_coreclk = {
 265         .clk    = {
 266                 .name           = "core_clk",
 267                 .parent         = &exynos4_clk_moutcore.clk,
 268         },
 269         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
 270 };
 271
 272 static struct clksrc_clk exynos4_clk_armclk = {
 273         .clk    = {
 274                 .name           = "armclk",
 275                 .parent         = &exynos4_clk_coreclk.clk,
 276         },
 277 };
 278
 279 static struct clksrc_clk exynos4_clk_aclk_corem0 = {
 280         .clk    = {
 281                 .name           = "aclk_corem0",
 282                 .parent         = &exynos4_clk_coreclk.clk,
 283         },
 284         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 285 };
 286
 287 static struct clksrc_clk exynos4_clk_aclk_cores = {
 288         .clk    = {
 289                 .name           = "aclk_cores",
 290                 .parent         = &exynos4_clk_coreclk.clk,
 291         },
 292         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 293 };
 294
 295 static struct clksrc_clk exynos4_clk_aclk_corem1 = {
 296         .clk    = {
 297                 .name           = "aclk_corem1",
 298                 .parent         = &exynos4_clk_coreclk.clk,
 299         },
 300         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
 301 };
 302
 303 static struct clksrc_clk exynos4_clk_periphclk = {
 304         .clk    = {
 305                 .name           = "periphclk",
 306                 .parent         = &exynos4_clk_coreclk.clk,
 307         },
 308         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
 309 };
 310
 311 /* Core list of CMU_CORE side */
 312
 313 static struct clk *exynos4_clkset_corebus_list[] = {
 314         [0] = &exynos4_clk_mout_mpll.clk,
 315         [1] = &exynos4_clk_sclk_apll.clk,
 316 };
 317
 318 struct clksrc_sources exynos4_clkset_mout_corebus = {
 319         .sources        = exynos4_clkset_corebus_list,
 320         .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
 321 };
 322
 323 static struct clksrc_clk exynos4_clk_mout_corebus = {
 324         .clk    = {
 325                 .name           = "mout_corebus",
 326         },
 327         .sources = &exynos4_clkset_mout_corebus,
 328         .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
 329 };
 330
 331 static struct clksrc_clk exynos4_clk_sclk_dmc = {
 332         .clk    = {
 333                 .name           = "sclk_dmc",
 334                 .parent         = &exynos4_clk_mout_corebus.clk,
 335         },
 336         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
 337 };
 338
 339 static struct clksrc_clk exynos4_clk_aclk_cored = {
 340         .clk    = {
 341                 .name           = "aclk_cored",
 342                 .parent         = &exynos4_clk_sclk_dmc.clk,
 343         },
 344         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
 345 };
 346
 347 static struct clksrc_clk exynos4_clk_aclk_corep = {
 348         .clk    = {
 349                 .name           = "aclk_corep",
 350                 .parent         = &exynos4_clk_aclk_cored.clk,
 351         },
 352         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
 353 };
 354
 355 static struct clksrc_clk exynos4_clk_aclk_acp = {
 356         .clk    = {
 357                 .name           = "aclk_acp",
 358                 .parent         = &exynos4_clk_mout_corebus.clk,
 359         },
 360         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
 361 };
 362
 363 static struct clksrc_clk exynos4_clk_pclk_acp = {
 364         .clk    = {
 365                 .name           = "pclk_acp",
 366                 .parent         = &exynos4_clk_aclk_acp.clk,
 367         },
 368         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
 369 };
 370
 371 /* Core list of CMU_TOP side */
 372
 373 struct clk *exynos4_clkset_aclk_top_list[] = {
 374         [0] = &exynos4_clk_mout_mpll.clk,
 375         [1] = &exynos4_clk_sclk_apll.clk,
 376 };
 377
 378 static struct clksrc_sources exynos4_clkset_aclk = {
 379         .sources        = exynos4_clkset_aclk_top_list,
 380         .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
 381 };
 382
 383 static struct clksrc_clk exynos4_clk_aclk_200 = {
 384         .clk    = {
 385                 .name           = "aclk_200",
 386         },
 387         .sources = &exynos4_clkset_aclk,
 388         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
 389         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
 390 };
 391
 392 static struct clksrc_clk exynos4_clk_aclk_100 = {
 393         .clk    = {
 394                 .name           = "aclk_100",
 395         },
 396         .sources = &exynos4_clkset_aclk,
 397         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
 398         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
 399 };
 400
 401 static struct clksrc_clk exynos4_clk_aclk_160 = {
 402         .clk    = {
 403                 .name           = "aclk_160",
 404         },
 405         .sources = &exynos4_clkset_aclk,
 406         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
 407         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
 408 };
 409
 410 struct clksrc_clk exynos4_clk_aclk_133 = {
 411         .clk    = {
 412                 .name           = "aclk_133",
 413         },
 414         .sources = &exynos4_clkset_aclk,
 415         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
 416         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
 417 };
 418
 419 static struct clk *exynos4_clkset_vpllsrc_list[] = {
 420         [0] = &clk_fin_vpll,
 421         [1] = &exynos4_clk_sclk_hdmi27m,
 422 };
 423
 424 static struct clksrc_sources exynos4_clkset_vpllsrc = {
 425         .sources        = exynos4_clkset_vpllsrc_list,
 426         .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
 427 };
 428
 429 static struct clksrc_clk exynos4_clk_vpllsrc = {
 430         .clk    = {
 431                 .name           = "vpll_src",
 432                 .enable         = exynos4_clksrc_mask_top_ctrl,
 433                 .ctrlbit        = (1 << 0),
 434         },
 435         .sources = &exynos4_clkset_vpllsrc,
 436         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
 437 };
 438
 439 static struct clk *exynos4_clkset_sclk_vpll_list[] = {
 440         [0] = &exynos4_clk_vpllsrc.clk,
 441         [1] = &clk_fout_vpll,
 442 };
 443
 444 static struct clksrc_sources exynos4_clkset_sclk_vpll = {
 445         .sources        = exynos4_clkset_sclk_vpll_list,
 446         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
 447 };
 448
 449 static struct clksrc_clk exynos4_clk_sclk_vpll = {
 450         .clk    = {
 451                 .name           = "sclk_vpll",
 452         },
 453         .sources = &exynos4_clkset_sclk_vpll,
 454         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
 455 };
 456
 457 static struct clk exynos4_init_clocks_off[] = {
 458         {
 459                 .name           = "timers",
 460                 .parent         = &exynos4_clk_aclk_100.clk,
 461                 .enable         = exynos4_clk_ip_peril_ctrl,
 462                 .ctrlbit        = (1<<24),
 463         }, {
 464                 .name           = "csis",
 465                 .devname        = "s5p-mipi-csis.0",
 466                 .enable         = exynos4_clk_ip_cam_ctrl,
 467                 .ctrlbit        = (1 << 4),
 468         }, {
 469                 .name           = "csis",
 470                 .devname        = "s5p-mipi-csis.1",
 471                 .enable         = exynos4_clk_ip_cam_ctrl,
 472                 .ctrlbit        = (1 << 5),
 473         }, {
 474                 .name           = "fimc",
 475                 .devname        = "exynos4-fimc.0",
 476                 .enable         = exynos4_clk_ip_cam_ctrl,
 477                 .ctrlbit        = (1 << 0),
 478         }, {
 479                 .name           = "fimc",
 480                 .devname        = "exynos4-fimc.1",
 481                 .enable         = exynos4_clk_ip_cam_ctrl,
 482                 .ctrlbit        = (1 << 1),
 483         }, {
 484                 .name           = "fimc",
 485                 .devname        = "exynos4-fimc.2",
 486                 .enable         = exynos4_clk_ip_cam_ctrl,
 487                 .ctrlbit        = (1 << 2),
 488         }, {
 489                 .name           = "fimc",
 490                 .devname        = "exynos4-fimc.3",
 491                 .enable         = exynos4_clk_ip_cam_ctrl,
 492                 .ctrlbit        = (1 << 3),
 493         }, {
 494                 .name           = "hsmmc",
 495                 .devname        = "s3c-sdhci.0",
 496                 .parent         = &exynos4_clk_aclk_133.clk,
 497                 .enable         = exynos4_clk_ip_fsys_ctrl,
 498                 .ctrlbit        = (1 << 5),
 499         }, {
 500                 .name           = "hsmmc",
 501                 .devname        = "s3c-sdhci.1",
 502                 .parent         = &exynos4_clk_aclk_133.clk,
 503                 .enable         = exynos4_clk_ip_fsys_ctrl,
 504                 .ctrlbit        = (1 << 6),
 505         }, {
 506                 .name           = "hsmmc",
 507                 .devname        = "s3c-sdhci.2",
 508                 .parent         = &exynos4_clk_aclk_133.clk,
 509                 .enable         = exynos4_clk_ip_fsys_ctrl,
 510                 .ctrlbit        = (1 << 7),
 511         }, {
 512                 .name           = "hsmmc",
 513                 .devname        = "s3c-sdhci.3",
 514                 .parent         = &exynos4_clk_aclk_133.clk,
 515                 .enable         = exynos4_clk_ip_fsys_ctrl,
 516                 .ctrlbit        = (1 << 8),
 517         }, {
 518                 .name           = "dwmmc",
 519                 .parent         = &exynos4_clk_aclk_133.clk,
 520                 .enable         = exynos4_clk_ip_fsys_ctrl,
 521                 .ctrlbit        = (1 << 9),
 522         }, {
 523                 .name           = "dac",
 524                 .devname        = "s5p-sdo",
 525                 .enable         = exynos4_clk_ip_tv_ctrl,
 526                 .ctrlbit        = (1 << 2),
 527         }, {
 528                 .name           = "mixer",
 529                 .devname        = "s5p-mixer",
 530                 .enable         = exynos4_clk_ip_tv_ctrl,
 531                 .ctrlbit        = (1 << 1),
 532         }, {
 533                 .name           = "vp",
 534                 .devname        = "s5p-mixer",
 535                 .enable         = exynos4_clk_ip_tv_ctrl,
 536                 .ctrlbit        = (1 << 0),
 537         }, {
 538                 .name           = "hdmi",
 539                 .devname        = "exynos4-hdmi",
 540                 .enable         = exynos4_clk_ip_tv_ctrl,
 541                 .ctrlbit        = (1 << 3),
 542         }, {
 543                 .name           = "hdmiphy",
 544                 .devname        = "exynos4-hdmi",
 545                 .enable         = exynos4_clk_hdmiphy_ctrl,
 546                 .ctrlbit        = (1 << 0),
 547         }, {
 548                 .name           = "dacphy",
 549                 .devname        = "s5p-sdo",
 550                 .enable         = exynos4_clk_dac_ctrl,
 551                 .ctrlbit        = (1 << 0),
 552         }, {
 553                 .name           = "adc",
 554                 .enable         = exynos4_clk_ip_peril_ctrl,
 555                 .ctrlbit        = (1 << 15),
 556         }, {
 557                 .name           = "keypad",
 558                 .enable         = exynos4_clk_ip_perir_ctrl,
 559                 .ctrlbit        = (1 << 16),
 560         }, {
 561                 .name           = "rtc",
 562                 .enable         = exynos4_clk_ip_perir_ctrl,
 563                 .ctrlbit        = (1 << 15),
 564         }, {
 565                 .name           = "watchdog",
 566                 .parent         = &exynos4_clk_aclk_100.clk,
 567                 .enable         = exynos4_clk_ip_perir_ctrl,
 568                 .ctrlbit        = (1 << 14),
 569         }, {
 570                 .name           = "usbhost",
 571                 .enable         = exynos4_clk_ip_fsys_ctrl ,
 572                 .ctrlbit        = (1 << 12),
 573         }, {
 574                 .name           = "otg",
 575                 .enable         = exynos4_clk_ip_fsys_ctrl,
 576                 .ctrlbit        = (1 << 13),
 577         }, {
 578                 .name           = "spi",
 579                 .devname        = "s3c64xx-spi.0",
 580                 .enable         = exynos4_clk_ip_peril_ctrl,
 581                 .ctrlbit        = (1 << 16),
 582         }, {
 583                 .name           = "spi",
 584                 .devname        = "s3c64xx-spi.1",
 585                 .enable         = exynos4_clk_ip_peril_ctrl,
 586                 .ctrlbit        = (1 << 17),
 587         }, {
 588                 .name           = "spi",
 589                 .devname        = "s3c64xx-spi.2",
 590                 .enable         = exynos4_clk_ip_peril_ctrl,
 591                 .ctrlbit        = (1 << 18),
 592         }, {
 593                 .name           = "iis",
 594                 .devname        = "samsung-i2s.0",
 595                 .enable         = exynos4_clk_ip_peril_ctrl,
 596                 .ctrlbit        = (1 << 19),
 597         }, {
 598                 .name           = "iis",
 599                 .devname        = "samsung-i2s.1",
 600                 .enable         = exynos4_clk_ip_peril_ctrl,
 601                 .ctrlbit        = (1 << 20),
 602         }, {
 603                 .name           = "iis",
 604                 .devname        = "samsung-i2s.2",
 605                 .enable         = exynos4_clk_ip_peril_ctrl,
 606                 .ctrlbit        = (1 << 21),
 607         }, {
 608                 .name           = "ac97",
 609                 .devname        = "samsung-ac97",
 610                 .enable         = exynos4_clk_ip_peril_ctrl,
 611                 .ctrlbit        = (1 << 27),
 612         }, {
 613                 .name           = "fimg2d",
 614                 .enable         = exynos4_clk_ip_image_ctrl,
 615                 .ctrlbit        = (1 << 0),
 616         }, {
 617                 .name           = "mfc",
 618                 .devname        = "s5p-mfc",
 619                 .enable         = exynos4_clk_ip_mfc_ctrl,
 620                 .ctrlbit        = (1 << 0),
 621         }, {
 622                 .name           = "i2c",
 623                 .devname        = "s3c2440-i2c.0",
 624                 .parent         = &exynos4_clk_aclk_100.clk,
 625                 .enable         = exynos4_clk_ip_peril_ctrl,
 626                 .ctrlbit        = (1 << 6),
 627         }, {
 628                 .name           = "i2c",
 629                 .devname        = "s3c2440-i2c.1",
 630                 .parent         = &exynos4_clk_aclk_100.clk,
 631                 .enable         = exynos4_clk_ip_peril_ctrl,
 632                 .ctrlbit        = (1 << 7),
 633         }, {
 634                 .name           = "i2c",
 635                 .devname        = "s3c2440-i2c.2",
 636                 .parent         = &exynos4_clk_aclk_100.clk,
 637                 .enable         = exynos4_clk_ip_peril_ctrl,
 638                 .ctrlbit        = (1 << 8),
 639         }, {
 640                 .name           = "i2c",
 641                 .devname        = "s3c2440-i2c.3",
 642                 .parent         = &exynos4_clk_aclk_100.clk,
 643                 .enable         = exynos4_clk_ip_peril_ctrl,
 644                 .ctrlbit        = (1 << 9),
 645         }, {
 646                 .name           = "i2c",
 647                 .devname        = "s3c2440-i2c.4",
 648                 .parent         = &exynos4_clk_aclk_100.clk,
 649                 .enable         = exynos4_clk_ip_peril_ctrl,
 650                 .ctrlbit        = (1 << 10),
 651         }, {
 652                 .name           = "i2c",
 653                 .devname        = "s3c2440-i2c.5",
 654                 .parent         = &exynos4_clk_aclk_100.clk,
 655                 .enable         = exynos4_clk_ip_peril_ctrl,
 656                 .ctrlbit        = (1 << 11),
 657         }, {
 658                 .name           = "i2c",
 659                 .devname        = "s3c2440-i2c.6",
 660                 .parent         = &exynos4_clk_aclk_100.clk,
 661                 .enable         = exynos4_clk_ip_peril_ctrl,
 662                 .ctrlbit        = (1 << 12),
 663         }, {
 664                 .name           = "i2c",
 665                 .devname        = "s3c2440-i2c.7",
 666                 .parent         = &exynos4_clk_aclk_100.clk,
 667                 .enable         = exynos4_clk_ip_peril_ctrl,
 668                 .ctrlbit        = (1 << 13),
 669         }, {
 670                 .name           = "i2c",
 671                 .devname        = "s3c2440-hdmiphy-i2c",
 672                 .parent         = &exynos4_clk_aclk_100.clk,
 673                 .enable         = exynos4_clk_ip_peril_ctrl,
 674                 .ctrlbit        = (1 << 14),
 675         }, {
 676                 .name           = "SYSMMU_MDMA",
 677                 .enable         = exynos4_clk_ip_image_ctrl,
 678                 .ctrlbit        = (1 << 5),
 679         }, {
 680                 .name           = "SYSMMU_FIMC0",
 681                 .enable         = exynos4_clk_ip_cam_ctrl,
 682                 .ctrlbit        = (1 << 7),
 683         }, {
 684                 .name           = "SYSMMU_FIMC1",
 685                 .enable         = exynos4_clk_ip_cam_ctrl,
 686                 .ctrlbit        = (1 << 8),
 687         }, {
 688                 .name           = "SYSMMU_FIMC2",
 689                 .enable         = exynos4_clk_ip_cam_ctrl,
 690                 .ctrlbit        = (1 << 9),
 691         }, {
 692                 .name           = "SYSMMU_FIMC3",
 693                 .enable         = exynos4_clk_ip_cam_ctrl,
 694                 .ctrlbit        = (1 << 10),
 695         }, {
 696                 .name           = "SYSMMU_JPEG",
 697                 .enable         = exynos4_clk_ip_cam_ctrl,
 698                 .ctrlbit        = (1 << 11),
 699         }, {
 700                 .name           = "SYSMMU_FIMD0",
 701                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 702                 .ctrlbit        = (1 << 4),
 703         }, {
 704                 .name           = "SYSMMU_FIMD1",
 705                 .enable         = exynos4_clk_ip_lcd1_ctrl,
 706                 .ctrlbit        = (1 << 4),
 707         }, {
 708                 .name           = "SYSMMU_PCIe",
 709                 .enable         = exynos4_clk_ip_fsys_ctrl,
 710                 .ctrlbit        = (1 << 18),
 711         }, {
 712                 .name           = "SYSMMU_G2D",
 713                 .enable         = exynos4_clk_ip_image_ctrl,
 714                 .ctrlbit        = (1 << 3),
 715         }, {
 716                 .name           = "SYSMMU_ROTATOR",
 717                 .enable         = exynos4_clk_ip_image_ctrl,
 718                 .ctrlbit        = (1 << 4),
 719         }, {
 720                 .name           = "SYSMMU_TV",
 721                 .enable         = exynos4_clk_ip_tv_ctrl,
 722                 .ctrlbit        = (1 << 4),
 723         }, {
 724                 .name           = "SYSMMU_MFC_L",
 725                 .enable         = exynos4_clk_ip_mfc_ctrl,
 726                 .ctrlbit        = (1 << 1),
 727         }, {
 728                 .name           = "SYSMMU_MFC_R",
 729                 .enable         = exynos4_clk_ip_mfc_ctrl,
 730                 .ctrlbit        = (1 << 2),
 731         }
 732 };
 733
 734 static struct clk exynos4_init_clocks_on[] = {
 735         {
 736                 .name           = "uart",
 737                 .devname        = "s5pv210-uart.0",
 738                 .enable         = exynos4_clk_ip_peril_ctrl,
 739                 .ctrlbit        = (1 << 0),
 740         }, {
 741                 .name           = "uart",
 742                 .devname        = "s5pv210-uart.1",
 743                 .enable         = exynos4_clk_ip_peril_ctrl,
 744                 .ctrlbit        = (1 << 1),
 745         }, {
 746                 .name           = "uart",
 747                 .devname        = "s5pv210-uart.2",
 748                 .enable         = exynos4_clk_ip_peril_ctrl,
 749                 .ctrlbit        = (1 << 2),
 750         }, {
 751                 .name           = "uart",
 752                 .devname        = "s5pv210-uart.3",
 753                 .enable         = exynos4_clk_ip_peril_ctrl,
 754                 .ctrlbit        = (1 << 3),
 755         }, {
 756                 .name           = "uart",
 757                 .devname        = "s5pv210-uart.4",
 758                 .enable         = exynos4_clk_ip_peril_ctrl,
 759                 .ctrlbit        = (1 << 4),
 760         }, {
 761                 .name           = "uart",
 762                 .devname        = "s5pv210-uart.5",
 763                 .enable         = exynos4_clk_ip_peril_ctrl,
 764                 .ctrlbit        = (1 << 5),
 765         }
 766 };
 767
 768 static struct clk exynos4_clk_pdma0 = {
 769         .name           = "dma",
 770         .devname        = "dma-pl330.0",
 771         .enable         = exynos4_clk_ip_fsys_ctrl,
 772         .ctrlbit        = (1 << 0),
 773 };
 774
 775 static struct clk exynos4_clk_pdma1 = {
 776         .name           = "dma",
 777         .devname        = "dma-pl330.1",
 778         .enable         = exynos4_clk_ip_fsys_ctrl,
 779         .ctrlbit        = (1 << 1),
 780 };
 781
 782 static struct clk exynos4_clk_mdma1 = {
 783         .name           = "dma",
 784         .devname        = "dma-pl330.2",
 785         .enable         = exynos4_clk_ip_image_ctrl,
 786         .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
 787 };
 788
 789 static struct clk exynos4_clk_fimd0 = {
 790         .name           = "fimd",
 791         .devname        = "exynos4-fb.0",
 792         .enable         = exynos4_clk_ip_lcd0_ctrl,
 793         .ctrlbit        = (1 << 0),
 794 };
 795
 796 struct clk *exynos4_clkset_group_list[] = {
 797         [0] = &clk_ext_xtal_mux,
 798         [1] = &clk_xusbxti,
 799         [2] = &exynos4_clk_sclk_hdmi27m,
 800         [3] = &exynos4_clk_sclk_usbphy0,
 801         [4] = &exynos4_clk_sclk_usbphy1,
 802         [5] = &exynos4_clk_sclk_hdmiphy,
 803         [6] = &exynos4_clk_mout_mpll.clk,
 804         [7] = &exynos4_clk_mout_epll.clk,
 805         [8] = &exynos4_clk_sclk_vpll.clk,
 806 };
 807
 808 struct clksrc_sources exynos4_clkset_group = {
 809         .sources        = exynos4_clkset_group_list,
 810         .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
 811 };
 812
 813 static struct clk *exynos4_clkset_mout_g2d0_list[] = {
 814         [0] = &exynos4_clk_mout_mpll.clk,
 815         [1] = &exynos4_clk_sclk_apll.clk,
 816 };
 817
 818 static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
 819         .sources        = exynos4_clkset_mout_g2d0_list,
 820         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
 821 };
 822
 823 static struct clksrc_clk exynos4_clk_mout_g2d0 = {
 824         .clk    = {
 825                 .name           = "mout_g2d0",
 826         },
 827         .sources = &exynos4_clkset_mout_g2d0,
 828         .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
 829 };
 830
 831 static struct clk *exynos4_clkset_mout_g2d1_list[] = {
 832         [0] = &exynos4_clk_mout_epll.clk,
 833         [1] = &exynos4_clk_sclk_vpll.clk,
 834 };
 835
 836 static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
 837         .sources        = exynos4_clkset_mout_g2d1_list,
 838         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
 839 };
 840
 841 static struct clksrc_clk exynos4_clk_mout_g2d1 = {
 842         .clk    = {
 843                 .name           = "mout_g2d1",
 844         },
 845         .sources = &exynos4_clkset_mout_g2d1,
 846         .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
 847 };
 848
 849 static struct clk *exynos4_clkset_mout_g2d_list[] = {
 850         [0] = &exynos4_clk_mout_g2d0.clk,
 851         [1] = &exynos4_clk_mout_g2d1.clk,
 852 };
 853
 854 static struct clksrc_sources exynos4_clkset_mout_g2d = {
 855         .sources        = exynos4_clkset_mout_g2d_list,
 856         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
 857 };
 858
 859 static struct clk *exynos4_clkset_mout_mfc0_list[] = {
 860         [0] = &exynos4_clk_mout_mpll.clk,
 861         [1] = &exynos4_clk_sclk_apll.clk,
 862 };
 863
 864 static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
 865         .sources        = exynos4_clkset_mout_mfc0_list,
 866         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
 867 };
 868
 869 static struct clksrc_clk exynos4_clk_mout_mfc0 = {
 870         .clk    = {
 871                 .name           = "mout_mfc0",
 872         },
 873         .sources = &exynos4_clkset_mout_mfc0,
 874         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
 875 };
 876
 877 static struct clk *exynos4_clkset_mout_mfc1_list[] = {
 878         [0] = &exynos4_clk_mout_epll.clk,
 879         [1] = &exynos4_clk_sclk_vpll.clk,
 880 };
 881
 882 static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
 883         .sources        = exynos4_clkset_mout_mfc1_list,
 884         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
 885 };
 886
 887 static struct clksrc_clk exynos4_clk_mout_mfc1 = {
 888         .clk    = {
 889                 .name           = "mout_mfc1",
 890         },
 891         .sources = &exynos4_clkset_mout_mfc1,
 892         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
 893 };
 894
 895 static struct clk *exynos4_clkset_mout_mfc_list[] = {
 896         [0] = &exynos4_clk_mout_mfc0.clk,
 897         [1] = &exynos4_clk_mout_mfc1.clk,
 898 };
 899
 900 static struct clksrc_sources exynos4_clkset_mout_mfc = {
 901         .sources        = exynos4_clkset_mout_mfc_list,
 902         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
 903 };
 904
 905 static struct clk *exynos4_clkset_sclk_dac_list[] = {
 906         [0] = &exynos4_clk_sclk_vpll.clk,
 907         [1] = &exynos4_clk_sclk_hdmiphy,
 908 };
 909
 910 static struct clksrc_sources exynos4_clkset_sclk_dac = {
 911         .sources        = exynos4_clkset_sclk_dac_list,
 912         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
 913 };
 914
 915 static struct clksrc_clk exynos4_clk_sclk_dac = {
 916         .clk            = {
 917                 .name           = "sclk_dac",
 918                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 919                 .ctrlbit        = (1 << 8),
 920         },
 921         .sources = &exynos4_clkset_sclk_dac,
 922         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
 923 };
 924
 925 static struct clksrc_clk exynos4_clk_sclk_pixel = {
 926         .clk            = {
 927                 .name           = "sclk_pixel",
 928                 .parent         = &exynos4_clk_sclk_vpll.clk,
 929         },
 930         .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
 931 };
 932
 933 static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
 934         [0] = &exynos4_clk_sclk_pixel.clk,
 935         [1] = &exynos4_clk_sclk_hdmiphy,
 936 };
 937
 938 static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
 939         .sources        = exynos4_clkset_sclk_hdmi_list,
 940         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
 941 };
 942
 943 static struct clksrc_clk exynos4_clk_sclk_hdmi = {
 944         .clk            = {
 945                 .name           = "sclk_hdmi",
 946                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 947                 .ctrlbit        = (1 << 0),
 948         },
 949         .sources = &exynos4_clkset_sclk_hdmi,
 950         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
 951 };
 952
 953 static struct clk *exynos4_clkset_sclk_mixer_list[] = {
 954         [0] = &exynos4_clk_sclk_dac.clk,
 955         [1] = &exynos4_clk_sclk_hdmi.clk,
 956 };
 957
 958 static struct clksrc_sources exynos4_clkset_sclk_mixer = {
 959         .sources        = exynos4_clkset_sclk_mixer_list,
 960         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
 961 };
 962
 963 static struct clksrc_clk exynos4_clk_sclk_mixer = {
 964         .clk    = {
 965                 .name           = "sclk_mixer",
 966                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 967                 .ctrlbit        = (1 << 4),
 968         },
 969         .sources = &exynos4_clkset_sclk_mixer,
 970         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
 971 };
 972
 973 static struct clksrc_clk *exynos4_sclk_tv[] = {
 974         &exynos4_clk_sclk_dac,
 975         &exynos4_clk_sclk_pixel,
 976         &exynos4_clk_sclk_hdmi,
 977         &exynos4_clk_sclk_mixer,
 978 };
 979
 980 static struct clksrc_clk exynos4_clk_dout_mmc0 = {
 981         .clk    = {
 982                 .name           = "dout_mmc0",
 983         },
 984         .sources = &exynos4_clkset_group,
 985         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
 986         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 987 };
 988
 989 static struct clksrc_clk exynos4_clk_dout_mmc1 = {
 990         .clk    = {
 991                 .name           = "dout_mmc1",
 992         },
 993         .sources = &exynos4_clkset_group,
 994         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
 995         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 996 };
 997
 998 static struct clksrc_clk exynos4_clk_dout_mmc2 = {
 999         .clk    = {
1000                 .name           = "dout_mmc2",
1001         },
1002         .sources = &exynos4_clkset_group,
1003         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
1004         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1005 };
1006
1007 static struct clksrc_clk exynos4_clk_dout_mmc3 = {
1008         .clk    = {
1009                 .name           = "dout_mmc3",
1010         },
1011         .sources = &exynos4_clkset_group,
1012         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1013         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1014 };
1015
1016 static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1017         .clk            = {
1018                 .name           = "dout_mmc4",
1019         },
1020         .sources = &exynos4_clkset_group,
1021         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1022         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1023 };
1024
1025 static struct clksrc_clk exynos4_clksrcs[] = {
1026         {
1027                 .clk    = {
1028                         .name           = "sclk_pwm",
1029                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
1030                         .ctrlbit        = (1 << 24),
1031                 },
1032                 .sources = &exynos4_clkset_group,
1033                 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1034                 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1035         }, {
1036                 .clk    = {
1037                         .name           = "sclk_csis",
1038                         .devname        = "s5p-mipi-csis.0",
1039                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1040                         .ctrlbit        = (1 << 24),
1041                 },
1042                 .sources = &exynos4_clkset_group,
1043                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1044                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1045         }, {
1046                 .clk    = {
1047                         .name           = "sclk_csis",
1048                         .devname        = "s5p-mipi-csis.1",
1049                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1050                         .ctrlbit        = (1 << 28),
1051                 },
1052                 .sources = &exynos4_clkset_group,
1053                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1054                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1055         }, {
1056                 .clk    = {
1057                         .name           = "sclk_cam0",
1058                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1059                         .ctrlbit        = (1 << 16),
1060                 },
1061                 .sources = &exynos4_clkset_group,
1062                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1063                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1064         }, {
1065                 .clk    = {
1066                         .name           = "sclk_cam1",
1067                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1068                         .ctrlbit        = (1 << 20),
1069                 },
1070                 .sources = &exynos4_clkset_group,
1071                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1072                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1073         }, {
1074                 .clk    = {
1075                         .name           = "sclk_fimc",
1076                         .devname        = "exynos4-fimc.0",
1077                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1078                         .ctrlbit        = (1 << 0),
1079                 },
1080                 .sources = &exynos4_clkset_group,
1081                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1082                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1083         }, {
1084                 .clk    = {
1085                         .name           = "sclk_fimc",
1086                         .devname        = "exynos4-fimc.1",
1087                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1088                         .ctrlbit        = (1 << 4),
1089                 },
1090                 .sources = &exynos4_clkset_group,
1091                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1092                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1093         }, {
1094                 .clk    = {
1095                         .name           = "sclk_fimc",
1096                         .devname        = "exynos4-fimc.2",
1097                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1098                         .ctrlbit        = (1 << 8),
1099                 },
1100                 .sources = &exynos4_clkset_group,
1101                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1102                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1103         }, {
1104                 .clk    = {
1105                         .name           = "sclk_fimc",
1106                         .devname        = "exynos4-fimc.3",
1107                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1108                         .ctrlbit        = (1 << 12),
1109                 },
1110                 .sources = &exynos4_clkset_group,
1111                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1112                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1113         }, {
1114                 .clk    = {
1115                         .name           = "sclk_fimd",
1116                         .devname        = "exynos4-fb.0",
1117                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
1118                         .ctrlbit        = (1 << 0),
1119                 },
1120                 .sources = &exynos4_clkset_group,
1121                 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1122                 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1123         }, {
1124                 .clk    = {
1125                         .name           = "sclk_fimg2d",
1126                 },
1127                 .sources = &exynos4_clkset_mout_g2d,
1128                 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1129                 .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1130         }, {
1131                 .clk    = {
1132                         .name           = "sclk_mfc",
1133                         .devname        = "s5p-mfc",
1134                 },
1135                 .sources = &exynos4_clkset_mout_mfc,
1136                 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1137                 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1138         }, {
1139                 .clk    = {
1140                         .name           = "sclk_dwmmc",
1141                         .parent         = &exynos4_clk_dout_mmc4.clk,
1142                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1143                         .ctrlbit        = (1 << 16),
1144                 },
1145                 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1146         }
1147 };
1148
1149 static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1150         .clk    = {
1151                 .name           = "uclk1",
1152                 .devname        = "exynos4210-uart.0",
1153                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1154                 .ctrlbit        = (1 << 0),
1155         },
1156         .sources = &exynos4_clkset_group,
1157         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1158         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1159 };
1160
1161 static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1162         .clk    = {
1163                 .name           = "uclk1",
1164                 .devname        = "exynos4210-uart.1",
1165                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1166                 .ctrlbit        = (1 << 4),
1167         },
1168         .sources = &exynos4_clkset_group,
1169         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1170         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1171 };
1172
1173 static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1174         .clk    = {
1175                 .name           = "uclk1",
1176                 .devname        = "exynos4210-uart.2",
1177                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1178                 .ctrlbit        = (1 << 8),
1179         },
1180         .sources = &exynos4_clkset_group,
1181         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1182         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1183 };
1184
1185 static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1186         .clk    = {
1187                 .name           = "uclk1",
1188                 .devname        = "exynos4210-uart.3",
1189                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1190                 .ctrlbit        = (1 << 12),
1191         },
1192         .sources = &exynos4_clkset_group,
1193         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1194         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1195 };
1196
1197 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1198         .clk    = {
1199                 .name           = "sclk_mmc",
1200                 .devname        = "s3c-sdhci.0",
1201                 .parent         = &exynos4_clk_dout_mmc0.clk,
1202                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1203                 .ctrlbit        = (1 << 0),
1204         },
1205         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1206 };
1207
1208 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1209         .clk    = {
1210                 .name           = "sclk_mmc",
1211                 .devname        = "s3c-sdhci.1",
1212                 .parent         = &exynos4_clk_dout_mmc1.clk,
1213                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1214                 .ctrlbit        = (1 << 4),
1215         },
1216         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1217 };
1218
1219 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1220         .clk    = {
1221                 .name           = "sclk_mmc",
1222                 .devname        = "s3c-sdhci.2",
1223                 .parent         = &exynos4_clk_dout_mmc2.clk,
1224                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1225                 .ctrlbit        = (1 << 8),
1226         },
1227         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1228 };
1229
1230 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1231         .clk    = {
1232                 .name           = "sclk_mmc",
1233                 .devname        = "s3c-sdhci.3",
1234                 .parent         = &exynos4_clk_dout_mmc3.clk,
1235                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1236                 .ctrlbit        = (1 << 12),
1237         },
1238         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1239 };
1240
1241 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1242         .clk    = {
1243                 .name           = "sclk_spi",
1244                 .devname        = "s3c64xx-spi.0",
1245                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1246                 .ctrlbit        = (1 << 16),
1247         },
1248         .sources = &exynos4_clkset_group,
1249         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1250         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1251 };
1252
1253 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1254         .clk    = {
1255                 .name           = "sclk_spi",
1256                 .devname        = "s3c64xx-spi.1",
1257                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1258                 .ctrlbit        = (1 << 20),
1259         },
1260         .sources = &exynos4_clkset_group,
1261         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1262         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1263 };
1264
1265 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1266         .clk    = {
1267                 .name           = "sclk_spi",
1268                 .devname        = "s3c64xx-spi.2",
1269                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1270                 .ctrlbit        = (1 << 24),
1271         },
1272         .sources = &exynos4_clkset_group,
1273         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1274         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1275 };
1276
1277 /* Clock initialization code */
1278 static struct clksrc_clk *exynos4_sysclks[] = {
1279         &exynos4_clk_mout_apll,
1280         &exynos4_clk_sclk_apll,
1281         &exynos4_clk_mout_epll,
1282         &exynos4_clk_mout_mpll,
1283         &exynos4_clk_moutcore,
1284         &exynos4_clk_coreclk,
1285         &exynos4_clk_armclk,
1286         &exynos4_clk_aclk_corem0,
1287         &exynos4_clk_aclk_cores,
1288         &exynos4_clk_aclk_corem1,
1289         &exynos4_clk_periphclk,
1290         &exynos4_clk_mout_corebus,
1291         &exynos4_clk_sclk_dmc,
1292         &exynos4_clk_aclk_cored,
1293         &exynos4_clk_aclk_corep,
1294         &exynos4_clk_aclk_acp,
1295         &exynos4_clk_pclk_acp,
1296         &exynos4_clk_vpllsrc,
1297         &exynos4_clk_sclk_vpll,
1298         &exynos4_clk_aclk_200,
1299         &exynos4_clk_aclk_100,
1300         &exynos4_clk_aclk_160,
1301         &exynos4_clk_aclk_133,
1302         &exynos4_clk_dout_mmc0,
1303         &exynos4_clk_dout_mmc1,
1304         &exynos4_clk_dout_mmc2,
1305         &exynos4_clk_dout_mmc3,
1306         &exynos4_clk_dout_mmc4,
1307         &exynos4_clk_mout_mfc0,
1308         &exynos4_clk_mout_mfc1,
1309 };
1310
1311 static struct clk *exynos4_clk_cdev[] = {
1312         &exynos4_clk_pdma0,
1313         &exynos4_clk_pdma1,
1314         &exynos4_clk_mdma1,
1315         &exynos4_clk_fimd0,
1316 };
1317
1318 static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1319         &exynos4_clk_sclk_uart0,
1320         &exynos4_clk_sclk_uart1,
1321         &exynos4_clk_sclk_uart2,
1322         &exynos4_clk_sclk_uart3,
1323         &exynos4_clk_sclk_mmc0,
1324         &exynos4_clk_sclk_mmc1,
1325         &exynos4_clk_sclk_mmc2,
1326         &exynos4_clk_sclk_mmc3,
1327         &exynos4_clk_sclk_spi0,
1328         &exynos4_clk_sclk_spi1,
1329         &exynos4_clk_sclk_spi2,
1330
1331 };
1332
1333 static struct clk_lookup exynos4_clk_lookup[] = {
1334         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1335         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1336         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1337         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1338         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1339         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1340         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1341         CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1342         CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1343         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1344         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1345         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1346         CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1347         CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1348         CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1349 };
1350
1351 static int xtal_rate;
1352
1353 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1354 {
1355         if (soc_is_exynos4210())
1356                 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1357                                         pll_4508);
1358         else if (soc_is_exynos4212() || soc_is_exynos4412())
1359                 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1360         else
1361                 return 0;
1362 }
1363
1364 static struct clk_ops exynos4_fout_apll_ops = {
1365         .get_rate = exynos4_fout_apll_get_rate,
1366 };
1367
1368 static u32 exynos4_vpll_div[][8] = {
1369         {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
1370         { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1371 };
1372
1373 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1374 {
1375         return clk->rate;
1376 }
1377
1378 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1379 {
1380         unsigned int vpll_con0, vpll_con1 = 0;
1381         unsigned int i;
1382
1383         /* Return if nothing changed */
1384         if (clk->rate == rate)
1385                 return 0;
1386
1387         vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1388         vpll_con0 &= ~(0x1 << 27 |                                      \
1389                         PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
1390                         PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
1391                         PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1392
1393         vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1394         vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
1395                         PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1396                         PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1397
1398         for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1399                 if (exynos4_vpll_div[i][0] == rate) {
1400                         vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1401                         vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1402                         vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1403                         vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1404                         vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1405                         vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1406                         vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1407                         break;
1408                 }
1409         }
1410
1411         if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1412                 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1413                                 __func__);
1414                 return -EINVAL;
1415         }
1416
1417         __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1418         __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1419
1420         /* Wait for VPLL lock */
1421         while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1422                 continue;
1423
1424         clk->rate = rate;
1425         return 0;
1426 }
1427
1428 static struct clk_ops exynos4_vpll_ops = {
1429         .get_rate = exynos4_vpll_get_rate,
1430         .set_rate = exynos4_vpll_set_rate,
1431 };
1432
1433 void __init_or_cpufreq exynos4_setup_clocks(void)
1434 {
1435         struct clk *xtal_clk;
1436         unsigned long apll = 0;
1437         unsigned long mpll = 0;
1438         unsigned long epll = 0;
1439         unsigned long vpll = 0;
1440         unsigned long vpllsrc;
1441         unsigned long xtal;
1442         unsigned long armclk;
1443         unsigned long sclk_dmc;
1444         unsigned long aclk_200;
1445         unsigned long aclk_100;
1446         unsigned long aclk_160;
1447         unsigned long aclk_133;
1448         unsigned int ptr;
1449
1450         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1451
1452         xtal_clk = clk_get(NULL, "xtal");
1453         BUG_ON(IS_ERR(xtal_clk));
1454
1455         xtal = clk_get_rate(xtal_clk);
1456
1457         xtal_rate = xtal;
1458
1459         clk_put(xtal_clk);
1460
1461         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1462
1463         if (soc_is_exynos4210()) {
1464                 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1465                                         pll_4508);
1466                 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1467                                         pll_4508);
1468                 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1469                                         __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1470
1471                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1472                 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1473                                         __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1474         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1475                 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1476                 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1477                 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1478                                         __raw_readl(EXYNOS4_EPLL_CON1));
1479
1480                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1481                 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1482                                         __raw_readl(EXYNOS4_VPLL_CON1));
1483         } else {
1484                 /* nothing */
1485         }
1486
1487         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1488         clk_fout_mpll.rate = mpll;
1489         clk_fout_epll.rate = epll;
1490         clk_fout_vpll.ops = &exynos4_vpll_ops;
1491         clk_fout_vpll.rate = vpll;
1492
1493         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1494                         apll, mpll, epll, vpll);
1495
1496         armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1497         sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1498
1499         aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1500         aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1501         aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1502         aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1503
1504         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1505                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1506                         armclk, sclk_dmc, aclk_200,
1507                         aclk_100, aclk_160, aclk_133);
1508
1509         clk_f.rate = armclk;
1510         clk_h.rate = sclk_dmc;
1511         clk_p.rate = aclk_100;
1512
1513         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1514                 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1515 }
1516
1517 static struct clk *exynos4_clks[] __initdata = {
1518         &exynos4_clk_sclk_hdmi27m,
1519         &exynos4_clk_sclk_hdmiphy,
1520         &exynos4_clk_sclk_usbphy0,
1521         &exynos4_clk_sclk_usbphy1,
1522 };
1523
1524 #ifdef CONFIG_PM_SLEEP
1525 static int exynos4_clock_suspend(void)
1526 {
1527         s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1528         return 0;
1529 }
1530
1531 static void exynos4_clock_resume(void)
1532 {
1533         s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1534 }
1535
1536 #else
1537 #define exynos4_clock_suspend NULL
1538 #define exynos4_clock_resume NULL
1539 #endif
1540
1541 static struct syscore_ops exynos4_clock_syscore_ops = {
1542         .suspend        = exynos4_clock_suspend,
1543         .resume         = exynos4_clock_resume,
1544 };
1545
1546 void __init exynos4_register_clocks(void)
1547 {
1548         int ptr;
1549
1550         s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1551
1552         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1553                 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1554
1555         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1556                 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1557
1558         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1559                 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1560
1561         s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1562         s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1563
1564         s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1565         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1566                 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1567
1568         s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1569         s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1570         clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1571
1572         register_syscore_ops(&exynos4_clock_syscore_ops);
1573         s3c24xx_register_clock(&dummy_apb_pclk);
1574
1575         s3c_pwmclk_init();
1576 }