arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/irqchip.h>
  16 #include <linux/io.h>
  17 #include <linux/device.h>
  18 #include <linux/gpio.h>
  19 #include <linux/sched.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/of.h>
  22 #include <linux/of_fdt.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/export.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/irqchip.h>
  27 #include <linux/of_address.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/clk-provider.h>
  30 #include <linux/irqchip/arm-gic.h>
  31
  32 #include <asm/proc-fns.h>
  33 #include <asm/exception.h>
  34 #include <asm/hardware/cache-l2x0.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/cacheflush.h>
  38
  39 #include <mach/regs-irq.h>
  40 #include <mach/regs-pmu.h>
  41 #include <mach/regs-gpio.h>
  42
  43 #include <plat/cpu.h>
  44 #include <plat/devs.h>
  45 #include <plat/pm.h>
  46 #include <plat/sdhci.h>
  47 #include <plat/gpio-cfg.h>
  48 #include <plat/adc-core.h>
  49 #include <plat/fb-core.h>
  50 #include <plat/fimc-core.h>
  51 #include <plat/iic-core.h>
  52 #include <plat/tv-core.h>
  53 #include <plat/spi-core.h>
  54 #include <plat/regs-serial.h>
  55
  56 #include "common.h"
  57 #define L2_AUX_VAL 0x7C470001
  58 #define L2_AUX_MASK 0xC200ffff
  59
  60 static const char name_exynos4210[] = "EXYNOS4210";
  61 static const char name_exynos4212[] = "EXYNOS4212";
  62 static const char name_exynos4412[] = "EXYNOS4412";
  63 static const char name_exynos5250[] = "EXYNOS5250";
  64 static const char name_exynos5440[] = "EXYNOS5440";
  65
  66 static void exynos4_map_io(void);
  67 static void exynos5_map_io(void);
  68 static void exynos5440_map_io(void);
  69 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  70 static int exynos_init(void);
  71
  72 unsigned long xxti_f = 0, xusbxti_f = 0;
  73
  74 static struct cpu_table cpu_ids[] __initdata = {
  75         {
  76                 .idcode         = EXYNOS4210_CPU_ID,
  77                 .idmask         = EXYNOS4_CPU_MASK,
  78                 .map_io         = exynos4_map_io,
  79                 .init_uarts     = exynos4_init_uarts,
  80                 .init           = exynos_init,
  81                 .name           = name_exynos4210,
  82         }, {
  83                 .idcode         = EXYNOS4212_CPU_ID,
  84                 .idmask         = EXYNOS4_CPU_MASK,
  85                 .map_io         = exynos4_map_io,
  86                 .init_uarts     = exynos4_init_uarts,
  87                 .init           = exynos_init,
  88                 .name           = name_exynos4212,
  89         }, {
  90                 .idcode         = EXYNOS4412_CPU_ID,
  91                 .idmask         = EXYNOS4_CPU_MASK,
  92                 .map_io         = exynos4_map_io,
  93                 .init_uarts     = exynos4_init_uarts,
  94                 .init           = exynos_init,
  95                 .name           = name_exynos4412,
  96         }, {
  97                 .idcode         = EXYNOS5250_SOC_ID,
  98                 .idmask         = EXYNOS5_SOC_MASK,
  99                 .map_io         = exynos5_map_io,
 100                 .init           = exynos_init,
 101                 .name           = name_exynos5250,
 102         }, {
 103                 .idcode         = EXYNOS5440_SOC_ID,
 104                 .idmask         = EXYNOS5_SOC_MASK,
 105                 .map_io         = exynos5440_map_io,
 106                 .init           = exynos_init,
 107                 .name           = name_exynos5440,
 108         },
 109 };
 110
 111 /* Initial IO mappings */
 112
 113 static struct map_desc exynos_iodesc[] __initdata = {
 114         {
 115                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 116                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 117                 .length         = SZ_4K,
 118                 .type           = MT_DEVICE,
 119         },
 120 };
 121
 122 #ifdef CONFIG_ARCH_EXYNOS5
 123 static struct map_desc exynos5440_iodesc[] __initdata = {
 124         {
 125                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 126                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
 127                 .length         = SZ_4K,
 128                 .type           = MT_DEVICE,
 129         },
 130 };
 131 #endif
 132
 133 static struct map_desc exynos4_iodesc[] __initdata = {
 134         {
 135                 .virtual        = (unsigned long)S3C_VA_SYS,
 136                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 137                 .length         = SZ_64K,
 138                 .type           = MT_DEVICE,
 139         }, {
 140                 .virtual        = (unsigned long)S3C_VA_TIMER,
 141                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 142                 .length         = SZ_16K,
 143                 .type           = MT_DEVICE,
 144         }, {
 145                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 146                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 147                 .length         = SZ_4K,
 148                 .type           = MT_DEVICE,
 149         }, {
 150                 .virtual        = (unsigned long)S5P_VA_SROMC,
 151                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 152                 .length         = SZ_4K,
 153                 .type           = MT_DEVICE,
 154         }, {
 155                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 156                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 157                 .length         = SZ_4K,
 158                 .type           = MT_DEVICE,
 159         }, {
 160                 .virtual        = (unsigned long)S5P_VA_PMU,
 161                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 162                 .length         = SZ_64K,
 163                 .type           = MT_DEVICE,
 164         }, {
 165                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 166                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 167                 .length         = SZ_4K,
 168                 .type           = MT_DEVICE,
 169         }, {
 170                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 171                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 172                 .length         = SZ_64K,
 173                 .type           = MT_DEVICE,
 174         }, {
 175                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 176                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 177                 .length         = SZ_64K,
 178                 .type           = MT_DEVICE,
 179         }, {
 180                 .virtual        = (unsigned long)S3C_VA_UART,
 181                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 182                 .length         = SZ_512K,
 183                 .type           = MT_DEVICE,
 184         }, {
 185                 .virtual        = (unsigned long)S5P_VA_CMU,
 186                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 187                 .length         = SZ_128K,
 188                 .type           = MT_DEVICE,
 189         }, {
 190                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 191                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 192                 .length         = SZ_8K,
 193                 .type           = MT_DEVICE,
 194         }, {
 195                 .virtual        = (unsigned long)S5P_VA_L2CC,
 196                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 197                 .length         = SZ_4K,
 198                 .type           = MT_DEVICE,
 199         }, {
 200                 .virtual        = (unsigned long)S5P_VA_DMC0,
 201                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 202                 .length         = SZ_64K,
 203                 .type           = MT_DEVICE,
 204         }, {
 205                 .virtual        = (unsigned long)S5P_VA_DMC1,
 206                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 207                 .length         = SZ_64K,
 208                 .type           = MT_DEVICE,
 209         }, {
 210                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 211                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 212                 .length         = SZ_4K,
 213                 .type           = MT_DEVICE,
 214         },
 215 };
 216
 217 static struct map_desc exynos4_iodesc0[] __initdata = {
 218         {
 219                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 220                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 221                 .length         = SZ_4K,
 222                 .type           = MT_DEVICE,
 223         },
 224 };
 225
 226 static struct map_desc exynos4_iodesc1[] __initdata = {
 227         {
 228                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 229                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 230                 .length         = SZ_4K,
 231                 .type           = MT_DEVICE,
 232         },
 233 };
 234
 235 static struct map_desc exynos5_iodesc[] __initdata = {
 236         {
 237                 .virtual        = (unsigned long)S3C_VA_SYS,
 238                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 239                 .length         = SZ_64K,
 240                 .type           = MT_DEVICE,
 241         }, {
 242                 .virtual        = (unsigned long)S3C_VA_TIMER,
 243                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 244                 .length         = SZ_16K,
 245                 .type           = MT_DEVICE,
 246         }, {
 247                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 248                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 249                 .length         = SZ_4K,
 250                 .type           = MT_DEVICE,
 251         }, {
 252                 .virtual        = (unsigned long)S5P_VA_SROMC,
 253                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 254                 .length         = SZ_4K,
 255                 .type           = MT_DEVICE,
 256         }, {
 257                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 258                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 259                 .length         = SZ_4K,
 260                 .type           = MT_DEVICE,
 261         }, {
 262                 .virtual        = (unsigned long)S5P_VA_CMU,
 263                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 264                 .length         = 144 * SZ_1K,
 265                 .type           = MT_DEVICE,
 266         }, {
 267                 .virtual        = (unsigned long)S5P_VA_PMU,
 268                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 269                 .length         = SZ_64K,
 270                 .type           = MT_DEVICE,
 271         }, {
 272                 .virtual        = (unsigned long)S3C_VA_UART,
 273                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 274                 .length         = SZ_512K,
 275                 .type           = MT_DEVICE,
 276         },
 277 };
 278
 279 static struct map_desc exynos5440_iodesc0[] __initdata = {
 280         {
 281                 .virtual        = (unsigned long)S3C_VA_UART,
 282                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 283                 .length         = SZ_512K,
 284                 .type           = MT_DEVICE,
 285         },
 286 };
 287
 288 void exynos4_restart(char mode, const char *cmd)
 289 {
 290         __raw_writel(0x1, S5P_SWRESET);
 291 }
 292
 293 void exynos5_restart(char mode, const char *cmd)
 294 {
 295         struct device_node *np;
 296         u32 val;
 297         void __iomem *addr;
 298
 299         if (of_machine_is_compatible("samsung,exynos5250")) {
 300                 val = 0x1;
 301                 addr = EXYNOS_SWRESET;
 302         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 303                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 304                 addr = of_iomap(np, 0) + 0xcc;
 305                 val = (0xfff << 20) | (0x1 << 16);
 306         } else {
 307                 pr_err("%s: cannot support non-DT\n", __func__);
 308                 return;
 309         }
 310
 311         __raw_writel(val, addr);
 312 }
 313
 314 void __init exynos_init_late(void)
 315 {
 316         if (of_machine_is_compatible("samsung,exynos5440"))
 317                 /* to be supported later */
 318                 return;
 319
 320         exynos_pm_late_initcall();
 321 }
 322
 323 /*
 324  * exynos_map_io
 325  *
 326  * register the standard cpu IO areas
 327  */
 328
 329 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 330 {
 331         struct map_desc *iodesc = exynos_iodesc;
 332         int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
 333 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
 334         unsigned long root = of_get_flat_dt_root();
 335
 336         /* initialize the io descriptors we need for initialization */
 337         if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
 338                 iodesc = exynos5440_iodesc;
 339                 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
 340         }
 341 #endif
 342
 343         iotable_init(iodesc, iodesc_sz);
 344
 345         if (mach_desc)
 346                 iotable_init(mach_desc, size);
 347
 348         /* detect cpu id and rev. */
 349         s5p_init_cpu(S5P_VA_CHIPID);
 350
 351         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 352 }
 353
 354 static void __init exynos4_map_io(void)
 355 {
 356         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 357
 358         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 359                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 360         else
 361                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 362
 363         /* initialize device information early */
 364         exynos4_default_sdhci0();
 365         exynos4_default_sdhci1();
 366         exynos4_default_sdhci2();
 367         exynos4_default_sdhci3();
 368
 369         s3c_adc_setname("samsung-adc-v3");
 370
 371         s3c_fimc_setname(0, "exynos4-fimc");
 372         s3c_fimc_setname(1, "exynos4-fimc");
 373         s3c_fimc_setname(2, "exynos4-fimc");
 374         s3c_fimc_setname(3, "exynos4-fimc");
 375
 376         s3c_sdhci_setname(0, "exynos4-sdhci");
 377         s3c_sdhci_setname(1, "exynos4-sdhci");
 378         s3c_sdhci_setname(2, "exynos4-sdhci");
 379         s3c_sdhci_setname(3, "exynos4-sdhci");
 380
 381         /* The I2C bus controllers are directly compatible with s3c2440 */
 382         s3c_i2c0_setname("s3c2440-i2c");
 383         s3c_i2c1_setname("s3c2440-i2c");
 384         s3c_i2c2_setname("s3c2440-i2c");
 385
 386         s5p_fb_setname(0, "exynos4-fb");
 387         s5p_hdmi_setname("exynos4-hdmi");
 388
 389         s3c64xx_spi_setname("exynos4210-spi");
 390 }
 391
 392 static void __init exynos5_map_io(void)
 393 {
 394         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 395 }
 396
 397 static void __init exynos5440_map_io(void)
 398 {
 399         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 400 }
 401
 402 void __init exynos_init_time(void)
 403 {
 404         if (of_have_populated_dt()) {
 405 #ifdef CONFIG_OF
 406                 of_clk_init(NULL);
 407                 clocksource_of_init();
 408 #endif
 409         } else {
 410                 /* todo: remove after migrating legacy E4 platforms to dt */
 411 #ifdef CONFIG_ARCH_EXYNOS4
 412                 exynos4_clk_init(NULL);
 413                 exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 414 #endif
 415                 mct_init();
 416         }
 417 }
 418
 419 void __init exynos4_init_irq(void)
 420 {
 421         unsigned int gic_bank_offset;
 422
 423         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 424
 425         if (!of_have_populated_dt())
 426                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 427 #ifdef CONFIG_OF
 428         else
 429                 irqchip_init();
 430 #endif
 431
 432         if (!of_have_populated_dt())
 433                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 434
 435         /*
 436          * The parameters of s5p_init_irq() are for VIC init.
 437          * Theses parameters should be NULL and 0 because EXYNOS4
 438          * uses GIC instead of VIC.
 439          */
 440         s5p_init_irq(NULL, 0);
 441 }
 442
 443 void __init exynos5_init_irq(void)
 444 {
 445 #ifdef CONFIG_OF
 446         irqchip_init();
 447 #endif
 448         /*
 449          * The parameters of s5p_init_irq() are for VIC init.
 450          * Theses parameters should be NULL and 0 because EXYNOS4
 451          * uses GIC instead of VIC.
 452          */
 453         if (!of_machine_is_compatible("samsung,exynos5440"))
 454                 s5p_init_irq(NULL, 0);
 455
 456         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 457 }
 458
 459 struct bus_type exynos_subsys = {
 460         .name           = "exynos-core",
 461         .dev_name       = "exynos-core",
 462 };
 463
 464 static struct device exynos4_dev = {
 465         .bus    = &exynos_subsys,
 466 };
 467
 468 static int __init exynos_core_init(void)
 469 {
 470         return subsys_system_register(&exynos_subsys, NULL);
 471 }
 472 core_initcall(exynos_core_init);
 473
 474 #ifdef CONFIG_CACHE_L2X0
 475 static int __init exynos4_l2x0_cache_init(void)
 476 {
 477         int ret;
 478
 479         if (soc_is_exynos5250() || soc_is_exynos5440())
 480                 return 0;
 481
 482         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 483         if (!ret) {
 484                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 485                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 486                 return 0;
 487         }
 488
 489         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 490                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 491                 /* TAG, Data Latency Control: 2 cycles */
 492                 l2x0_saved_regs.tag_latency = 0x110;
 493
 494                 if (soc_is_exynos4212() || soc_is_exynos4412())
 495                         l2x0_saved_regs.data_latency = 0x120;
 496                 else
 497                         l2x0_saved_regs.data_latency = 0x110;
 498
 499                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 500                 l2x0_saved_regs.pwr_ctrl =
 501                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 502
 503                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 504
 505                 __raw_writel(l2x0_saved_regs.tag_latency,
 506                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 507                 __raw_writel(l2x0_saved_regs.data_latency,
 508                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 509
 510                 /* L2X0 Prefetch Control */
 511                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 512                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 513
 514                 /* L2X0 Power Control */
 515                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 516                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 517
 518                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 519                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 520         }
 521
 522         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 523         return 0;
 524 }
 525 early_initcall(exynos4_l2x0_cache_init);
 526 #endif
 527
 528 static int __init exynos_init(void)
 529 {
 530         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 531
 532         return device_register(&exynos4_dev);
 533 }
 534
 535 /* uart registration process */
 536
 537 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 538 {
 539         struct s3c2410_uartcfg *tcfg = cfg;
 540         u32 ucnt;
 541
 542         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 543                 tcfg->has_fracval = 1;
 544
 545         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 546 }
 547
 548 static void __iomem *exynos_eint_base;
 549
 550 static DEFINE_SPINLOCK(eint_lock);
 551
 552 static unsigned int eint0_15_data[16];
 553
 554 static inline int exynos4_irq_to_gpio(unsigned int irq)
 555 {
 556         if (irq < IRQ_EINT(0))
 557                 return -EINVAL;
 558
 559         irq -= IRQ_EINT(0);
 560         if (irq < 8)
 561                 return EXYNOS4_GPX0(irq);
 562
 563         irq -= 8;
 564         if (irq < 8)
 565                 return EXYNOS4_GPX1(irq);
 566
 567         irq -= 8;
 568         if (irq < 8)
 569                 return EXYNOS4_GPX2(irq);
 570
 571         irq -= 8;
 572         if (irq < 8)
 573                 return EXYNOS4_GPX3(irq);
 574
 575         return -EINVAL;
 576 }
 577
 578 static inline int exynos5_irq_to_gpio(unsigned int irq)
 579 {
 580         if (irq < IRQ_EINT(0))
 581                 return -EINVAL;
 582
 583         irq -= IRQ_EINT(0);
 584         if (irq < 8)
 585                 return EXYNOS5_GPX0(irq);
 586
 587         irq -= 8;
 588         if (irq < 8)
 589                 return EXYNOS5_GPX1(irq);
 590
 591         irq -= 8;
 592         if (irq < 8)
 593                 return EXYNOS5_GPX2(irq);
 594
 595         irq -= 8;
 596         if (irq < 8)
 597                 return EXYNOS5_GPX3(irq);
 598
 599         return -EINVAL;
 600 }
 601
 602 static unsigned int exynos4_eint0_15_src_int[16] = {
 603         EXYNOS4_IRQ_EINT0,
 604         EXYNOS4_IRQ_EINT1,
 605         EXYNOS4_IRQ_EINT2,
 606         EXYNOS4_IRQ_EINT3,
 607         EXYNOS4_IRQ_EINT4,
 608         EXYNOS4_IRQ_EINT5,
 609         EXYNOS4_IRQ_EINT6,
 610         EXYNOS4_IRQ_EINT7,
 611         EXYNOS4_IRQ_EINT8,
 612         EXYNOS4_IRQ_EINT9,
 613         EXYNOS4_IRQ_EINT10,
 614         EXYNOS4_IRQ_EINT11,
 615         EXYNOS4_IRQ_EINT12,
 616         EXYNOS4_IRQ_EINT13,
 617         EXYNOS4_IRQ_EINT14,
 618         EXYNOS4_IRQ_EINT15,
 619 };
 620
 621 static unsigned int exynos5_eint0_15_src_int[16] = {
 622         EXYNOS5_IRQ_EINT0,
 623         EXYNOS5_IRQ_EINT1,
 624         EXYNOS5_IRQ_EINT2,
 625         EXYNOS5_IRQ_EINT3,
 626         EXYNOS5_IRQ_EINT4,
 627         EXYNOS5_IRQ_EINT5,
 628         EXYNOS5_IRQ_EINT6,
 629         EXYNOS5_IRQ_EINT7,
 630         EXYNOS5_IRQ_EINT8,
 631         EXYNOS5_IRQ_EINT9,
 632         EXYNOS5_IRQ_EINT10,
 633         EXYNOS5_IRQ_EINT11,
 634         EXYNOS5_IRQ_EINT12,
 635         EXYNOS5_IRQ_EINT13,
 636         EXYNOS5_IRQ_EINT14,
 637         EXYNOS5_IRQ_EINT15,
 638 };
 639 static inline void exynos_irq_eint_mask(struct irq_data *data)
 640 {
 641         u32 mask;
 642
 643         spin_lock(&eint_lock);
 644         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 645         mask |= EINT_OFFSET_BIT(data->irq);
 646         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 647         spin_unlock(&eint_lock);
 648 }
 649
 650 static void exynos_irq_eint_unmask(struct irq_data *data)
 651 {
 652         u32 mask;
 653
 654         spin_lock(&eint_lock);
 655         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 656         mask &= ~(EINT_OFFSET_BIT(data->irq));
 657         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 658         spin_unlock(&eint_lock);
 659 }
 660
 661 static inline void exynos_irq_eint_ack(struct irq_data *data)
 662 {
 663         __raw_writel(EINT_OFFSET_BIT(data->irq),
 664                      EINT_PEND(exynos_eint_base, data->irq));
 665 }
 666
 667 static void exynos_irq_eint_maskack(struct irq_data *data)
 668 {
 669         exynos_irq_eint_mask(data);
 670         exynos_irq_eint_ack(data);
 671 }
 672
 673 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 674 {
 675         int offs = EINT_OFFSET(data->irq);
 676         int shift;
 677         u32 ctrl, mask;
 678         u32 newvalue = 0;
 679
 680         switch (type) {
 681         case IRQ_TYPE_EDGE_RISING:
 682                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 683                 break;
 684
 685         case IRQ_TYPE_EDGE_FALLING:
 686                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 687                 break;
 688
 689         case IRQ_TYPE_EDGE_BOTH:
 690                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 691                 break;
 692
 693         case IRQ_TYPE_LEVEL_LOW:
 694                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 695                 break;
 696
 697         case IRQ_TYPE_LEVEL_HIGH:
 698                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 699                 break;
 700
 701         default:
 702                 printk(KERN_ERR "No such irq type %d", type);
 703                 return -EINVAL;
 704         }
 705
 706         shift = (offs & 0x7) * 4;
 707         mask = 0x7 << shift;
 708
 709         spin_lock(&eint_lock);
 710         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 711         ctrl &= ~mask;
 712         ctrl |= newvalue << shift;
 713         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 714         spin_unlock(&eint_lock);
 715
 716         if (soc_is_exynos5250())
 717                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 718         else
 719                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 720
 721         return 0;
 722 }
 723
 724 static struct irq_chip exynos_irq_eint = {
 725         .name           = "exynos-eint",
 726         .irq_mask       = exynos_irq_eint_mask,
 727         .irq_unmask     = exynos_irq_eint_unmask,
 728         .irq_mask_ack   = exynos_irq_eint_maskack,
 729         .irq_ack        = exynos_irq_eint_ack,
 730         .irq_set_type   = exynos_irq_eint_set_type,
 731 #ifdef CONFIG_PM
 732         .irq_set_wake   = s3c_irqext_wake,
 733 #endif
 734 };
 735
 736 /*
 737  * exynos4_irq_demux_eint
 738  *
 739  * This function demuxes the IRQ from from EINTs 16 to 31.
 740  * It is designed to be inlined into the specific handler
 741  * s5p_irq_demux_eintX_Y.
 742  *
 743  * Each EINT pend/mask registers handle eight of them.
 744  */
 745 static inline void exynos_irq_demux_eint(unsigned int start)
 746 {
 747         unsigned int irq;
 748
 749         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 750         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 751
 752         status &= ~mask;
 753         status &= 0xff;
 754
 755         while (status) {
 756                 irq = fls(status) - 1;
 757                 generic_handle_irq(irq + start);
 758                 status &= ~(1 << irq);
 759         }
 760 }
 761
 762 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 763 {
 764         struct irq_chip *chip = irq_get_chip(irq);
 765         chained_irq_enter(chip, desc);
 766         exynos_irq_demux_eint(IRQ_EINT(16));
 767         exynos_irq_demux_eint(IRQ_EINT(24));
 768         chained_irq_exit(chip, desc);
 769 }
 770
 771 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 772 {
 773         u32 *irq_data = irq_get_handler_data(irq);
 774         struct irq_chip *chip = irq_get_chip(irq);
 775
 776         chained_irq_enter(chip, desc);
 777         generic_handle_irq(*irq_data);
 778         chained_irq_exit(chip, desc);
 779 }
 780
 781 static int __init exynos_init_irq_eint(void)
 782 {
 783         int irq;
 784
 785 #ifdef CONFIG_PINCTRL_SAMSUNG
 786         /*
 787          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
 788          * functionality along with support for external gpio and wakeup
 789          * interrupts. If the samsung pinctrl driver is enabled and includes
 790          * the wakeup interrupt support, then the setting up external wakeup
 791          * interrupts here can be skipped. This check here is temporary to
 792          * allow exynos4 platforms that do not use Samsung pinctrl driver to
 793          * co-exist with platforms that do. When all of the Samsung Exynos4
 794          * platforms switch over to using the pinctrl driver, the wakeup
 795          * interrupt support code here can be completely removed.
 796          */
 797         static const struct of_device_id exynos_pinctrl_ids[] = {
 798                 { .compatible = "samsung,exynos4210-pinctrl", },
 799                 { .compatible = "samsung,exynos4x12-pinctrl", },
 800                 { .compatible = "samsung,exynos5250-pinctrl", },
 801         };
 802         struct device_node *pctrl_np, *wkup_np;
 803         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
 804
 805         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
 806                 if (of_device_is_available(pctrl_np)) {
 807                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
 808                                                         wkup_compat);
 809                         if (wkup_np)
 810                                 return -ENODEV;
 811                 }
 812         }
 813 #endif
 814         if (soc_is_exynos5440())
 815                 return 0;
 816
 817         if (soc_is_exynos5250())
 818                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 819         else
 820                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 821
 822         if (exynos_eint_base == NULL) {
 823                 pr_err("unable to ioremap for EINT base address\n");
 824                 return -ENOMEM;
 825         }
 826
 827         for (irq = 0 ; irq <= 31 ; irq++) {
 828                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 829                                          handle_level_irq);
 830                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 831         }
 832
 833         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 834
 835         for (irq = 0 ; irq <= 15 ; irq++) {
 836                 eint0_15_data[irq] = IRQ_EINT(irq);
 837
 838                 if (soc_is_exynos5250()) {
 839                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
 840                                              &eint0_15_data[irq]);
 841                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
 842                                                 exynos_irq_eint0_15);
 843                 } else {
 844                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
 845                                              &eint0_15_data[irq]);
 846                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
 847                                                 exynos_irq_eint0_15);
 848                 }
 849         }
 850
 851         return 0;
 852 }
 853 arch_initcall(exynos_init_irq_eint);