arch/arm/mach-exynos/pm.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power Management support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/cpu_pm.h>
  20 #include <linux/io.h>
  21 #include <linux/irqchip/arm-gic.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24
  25 #include <asm/cacheflush.h>
  26 #include <asm/hardware/cache-l2x0.h>
  27 #include <asm/smp_scu.h>
  28 #include <asm/suspend.h>
  29
  30 #include <plat/pm-common.h>
  31 #include <plat/pll.h>
  32 #include <plat/regs-srom.h>
  33
  34 #include <mach/map.h>
  35
  36 #include "common.h"
  37 #include "regs-pmu.h"
  38
  39 /**
  40  * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
  41  * @hwirq: Hardware IRQ signal of the GIC
  42  * @mask: Mask in PMU wake-up mask register
  43  */
  44 struct exynos_wkup_irq {
  45         unsigned int hwirq;
  46         u32 mask;
  47 };
  48
  49 static struct sleep_save exynos5_sys_save[] = {
  50         SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
  51 };
  52
  53 static struct sleep_save exynos_core_save[] = {
  54         /* SROM side */
  55         SAVE_ITEM(S5P_SROM_BW),
  56         SAVE_ITEM(S5P_SROM_BC0),
  57         SAVE_ITEM(S5P_SROM_BC1),
  58         SAVE_ITEM(S5P_SROM_BC2),
  59         SAVE_ITEM(S5P_SROM_BC3),
  60 };
  61
  62 /*
  63  * GIC wake-up support
  64  */
  65
  66 static u32 exynos_irqwake_intmask = 0xffffffff;
  67
  68 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
  69         { 76, BIT(1) }, /* RTC alarm */
  70         { 77, BIT(2) }, /* RTC tick */
  71         { /* sentinel */ },
  72 };
  73
  74 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
  75         { 75, BIT(1) }, /* RTC alarm */
  76         { 76, BIT(2) }, /* RTC tick */
  77         { /* sentinel */ },
  78 };
  79
  80 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
  81 {
  82         const struct exynos_wkup_irq *wkup_irq;
  83
  84         if (soc_is_exynos5250())
  85                 wkup_irq = exynos5250_wkup_irq;
  86         else
  87                 wkup_irq = exynos4_wkup_irq;
  88
  89         while (wkup_irq->mask) {
  90                 if (wkup_irq->hwirq == data->hwirq) {
  91                         if (!state)
  92                                 exynos_irqwake_intmask |= wkup_irq->mask;
  93                         else
  94                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
  95                         return 0;
  96                 }
  97                 ++wkup_irq;
  98         }
  99
 100         return -ENOENT;
 101 }
 102
 103 #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
 104                         S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
 105                         (sysram_base_addr + 0x24) : S5P_INFORM0))
 106 #define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
 107                         S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
 108                         (sysram_base_addr + 0x20) : S5P_INFORM1))
 109
 110 #define S5P_CHECK_AFTR  0xFCBA0D10
 111 #define S5P_CHECK_SLEEP 0x00000BAD
 112
 113 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
 114 static void exynos_set_wakeupmask(long mask)
 115 {
 116         __raw_writel(mask, S5P_WAKEUP_MASK);
 117 }
 118
 119 static void exynos_cpu_set_boot_vector(long flags)
 120 {
 121         __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
 122         __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
 123 }
 124
 125 void exynos_enter_aftr(void)
 126 {
 127         exynos_set_wakeupmask(0x0000ff3e);
 128         exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
 129         /* Set value of power down register for aftr mode */
 130         exynos_sys_powerdown_conf(SYS_AFTR);
 131 }
 132
 133 /* For Cortex-A9 Diagnostic and Power control register */
 134 static unsigned int save_arm_register[2];
 135
 136 static void exynos_cpu_save_register(void)
 137 {
 138         unsigned long tmp;
 139
 140         /* Save Power control register */
 141         asm ("mrc p15, 0, %0, c15, c0, 0"
 142              : "=r" (tmp) : : "cc");
 143
 144         save_arm_register[0] = tmp;
 145
 146         /* Save Diagnostic register */
 147         asm ("mrc p15, 0, %0, c15, c0, 1"
 148              : "=r" (tmp) : : "cc");
 149
 150         save_arm_register[1] = tmp;
 151 }
 152
 153 static void exynos_cpu_restore_register(void)
 154 {
 155         unsigned long tmp;
 156
 157         /* Restore Power control register */
 158         tmp = save_arm_register[0];
 159
 160         asm volatile ("mcr p15, 0, %0, c15, c0, 0"
 161                       : : "r" (tmp)
 162                       : "cc");
 163
 164         /* Restore Diagnostic register */
 165         tmp = save_arm_register[1];
 166
 167         asm volatile ("mcr p15, 0, %0, c15, c0, 1"
 168                       : : "r" (tmp)
 169                       : "cc");
 170 }
 171
 172 static int exynos_cpu_suspend(unsigned long arg)
 173 {
 174 #ifdef CONFIG_CACHE_L2X0
 175         outer_flush_all();
 176 #endif
 177
 178         if (soc_is_exynos5250())
 179                 flush_cache_all();
 180
 181         /* issue the standby signal into the pm unit. */
 182         cpu_do_idle();
 183
 184         pr_info("Failed to suspend the system\n");
 185         return 1; /* Aborting suspend */
 186 }
 187
 188 static void exynos_pm_prepare(void)
 189 {
 190         unsigned int tmp;
 191
 192         /* Set wake-up mask registers */
 193         __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
 194         __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 195
 196         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 197
 198         if (soc_is_exynos5250()) {
 199                 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
 200                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
 201                 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
 202                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 203                 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
 204         }
 205
 206         /* Set value of power down register for sleep mode */
 207
 208         exynos_sys_powerdown_conf(SYS_SLEEP);
 209         __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 210
 211         /* ensure at least INFORM0 has the resume address */
 212
 213         __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 214 }
 215
 216 static void exynos_pm_central_suspend(void)
 217 {
 218         unsigned long tmp;
 219
 220         /* Setting Central Sequence Register for power down mode */
 221         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 222         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 223         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 224 }
 225
 226 static int exynos_pm_suspend(void)
 227 {
 228         unsigned long tmp;
 229
 230         exynos_pm_central_suspend();
 231
 232         /* Setting SEQ_OPTION register */
 233
 234         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 235         __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 236
 237         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 238                 exynos_cpu_save_register();
 239
 240         return 0;
 241 }
 242
 243 static int exynos_pm_central_resume(void)
 244 {
 245         unsigned long tmp;
 246
 247         /*
 248          * If PMU failed while entering sleep mode, WFI will be
 249          * ignored by PMU and then exiting cpu_do_idle().
 250          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 251          * in this situation.
 252          */
 253         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 254         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 255                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 256                 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 257                 /* clear the wakeup state register */
 258                 __raw_writel(0x0, S5P_WAKEUP_STAT);
 259                 /* No need to perform below restore code */
 260                 return -1;
 261         }
 262
 263         return 0;
 264 }
 265
 266 static void exynos_pm_resume(void)
 267 {
 268         if (exynos_pm_central_resume())
 269                 goto early_wakeup;
 270
 271         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 272                 exynos_cpu_restore_register();
 273
 274         /* For release retention */
 275
 276         __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
 277         __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
 278         __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
 279         __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
 280         __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
 281         __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
 282         __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 283
 284         if (soc_is_exynos5250())
 285                 s3c_pm_do_restore(exynos5_sys_save,
 286                         ARRAY_SIZE(exynos5_sys_save));
 287
 288         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 289
 290         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 291                 scu_enable(S5P_VA_SCU);
 292
 293 early_wakeup:
 294
 295         /* Clear SLEEP mode set in INFORM1 */
 296         __raw_writel(0x0, S5P_INFORM1);
 297
 298         return;
 299 }
 300
 301 static struct syscore_ops exynos_pm_syscore_ops = {
 302         .suspend        = exynos_pm_suspend,
 303         .resume         = exynos_pm_resume,
 304 };
 305
 306 /*
 307  * Suspend Ops
 308  */
 309
 310 static int exynos_suspend_enter(suspend_state_t state)
 311 {
 312         int ret;
 313
 314         s3c_pm_debug_init();
 315
 316         S3C_PMDBG("%s: suspending the system...\n", __func__);
 317
 318         S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
 319                         exynos_irqwake_intmask, exynos_get_eint_wake_mask());
 320
 321         if (exynos_irqwake_intmask == -1U
 322             && exynos_get_eint_wake_mask() == -1U) {
 323                 pr_err("%s: No wake-up sources!\n", __func__);
 324                 pr_err("%s: Aborting sleep\n", __func__);
 325                 return -EINVAL;
 326         }
 327
 328         s3c_pm_save_uarts();
 329         exynos_pm_prepare();
 330         flush_cache_all();
 331         s3c_pm_check_store();
 332
 333         ret = cpu_suspend(0, exynos_cpu_suspend);
 334         if (ret)
 335                 return ret;
 336
 337         s3c_pm_restore_uarts();
 338
 339         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
 340                         __raw_readl(S5P_WAKEUP_STAT));
 341
 342         s3c_pm_check_restore();
 343
 344         S3C_PMDBG("%s: resuming the system...\n", __func__);
 345
 346         return 0;
 347 }
 348
 349 static int exynos_suspend_prepare(void)
 350 {
 351         s3c_pm_check_prepare();
 352
 353         return 0;
 354 }
 355
 356 static void exynos_suspend_finish(void)
 357 {
 358         s3c_pm_check_cleanup();
 359 }
 360
 361 static const struct platform_suspend_ops exynos_suspend_ops = {
 362         .enter          = exynos_suspend_enter,
 363         .prepare        = exynos_suspend_prepare,
 364         .finish         = exynos_suspend_finish,
 365         .valid          = suspend_valid_only_mem,
 366 };
 367
 368 static int exynos_cpu_pm_notifier(struct notifier_block *self,
 369                                   unsigned long cmd, void *v)
 370 {
 371         int cpu = smp_processor_id();
 372
 373         switch (cmd) {
 374         case CPU_PM_ENTER:
 375                 if (cpu == 0) {
 376                         exynos_pm_central_suspend();
 377                         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 378                                 exynos_cpu_save_register();
 379                 }
 380                 break;
 381
 382         case CPU_PM_EXIT:
 383                 if (cpu == 0) {
 384                         if (read_cpuid_part_number() ==
 385                                         ARM_CPU_PART_CORTEX_A9) {
 386                                 scu_enable(S5P_VA_SCU);
 387                                 exynos_cpu_restore_register();
 388                         }
 389                         exynos_pm_central_resume();
 390                 }
 391                 break;
 392         }
 393
 394         return NOTIFY_OK;
 395 }
 396
 397 static struct notifier_block exynos_cpu_pm_notifier_block = {
 398         .notifier_call = exynos_cpu_pm_notifier,
 399 };
 400
 401 void __init exynos_pm_init(void)
 402 {
 403         u32 tmp;
 404
 405         cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
 406
 407         /* Platform-specific GIC callback */
 408         gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 409
 410         /* All wakeup disable */
 411         tmp = __raw_readl(S5P_WAKEUP_MASK);
 412         tmp |= ((0xFF << 8) | (0x1F << 1));
 413         __raw_writel(tmp, S5P_WAKEUP_MASK);
 414
 415         register_syscore_ops(&exynos_pm_syscore_ops);
 416         suspend_set_ops(&exynos_suspend_ops);
 417 }