arch/arm/mach-exynos/pm.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power Management support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/cpu_pm.h>
  20 #include <linux/io.h>
  21 #include <linux/irqchip/arm-gic.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24
  25 #include <asm/cacheflush.h>
  26 #include <asm/hardware/cache-l2x0.h>
  27 #include <asm/smp_scu.h>
  28 #include <asm/suspend.h>
  29
  30 #include <plat/pm-common.h>
  31 #include <plat/pll.h>
  32 #include <plat/regs-srom.h>
  33
  34 #include <mach/map.h>
  35
  36 #include "common.h"
  37 #include "regs-pmu.h"
  38 #include "regs-sys.h"
  39
  40 /**
  41  * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
  42  * @hwirq: Hardware IRQ signal of the GIC
  43  * @mask: Mask in PMU wake-up mask register
  44  */
  45 struct exynos_wkup_irq {
  46         unsigned int hwirq;
  47         u32 mask;
  48 };
  49
  50 static struct sleep_save exynos5_sys_save[] = {
  51         SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
  52 };
  53
  54 static struct sleep_save exynos_core_save[] = {
  55         /* SROM side */
  56         SAVE_ITEM(S5P_SROM_BW),
  57         SAVE_ITEM(S5P_SROM_BC0),
  58         SAVE_ITEM(S5P_SROM_BC1),
  59         SAVE_ITEM(S5P_SROM_BC2),
  60         SAVE_ITEM(S5P_SROM_BC3),
  61 };
  62
  63 /*
  64  * GIC wake-up support
  65  */
  66
  67 static u32 exynos_irqwake_intmask = 0xffffffff;
  68
  69 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
  70         { 76, BIT(1) }, /* RTC alarm */
  71         { 77, BIT(2) }, /* RTC tick */
  72         { /* sentinel */ },
  73 };
  74
  75 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
  76         { 75, BIT(1) }, /* RTC alarm */
  77         { 76, BIT(2) }, /* RTC tick */
  78         { /* sentinel */ },
  79 };
  80
  81 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
  82 {
  83         const struct exynos_wkup_irq *wkup_irq;
  84
  85         if (soc_is_exynos5250())
  86                 wkup_irq = exynos5250_wkup_irq;
  87         else
  88                 wkup_irq = exynos4_wkup_irq;
  89
  90         while (wkup_irq->mask) {
  91                 if (wkup_irq->hwirq == data->hwirq) {
  92                         if (!state)
  93                                 exynos_irqwake_intmask |= wkup_irq->mask;
  94                         else
  95                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
  96                         return 0;
  97                 }
  98                 ++wkup_irq;
  99         }
 100
 101         return -ENOENT;
 102 }
 103
 104 #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
 105                         S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
 106                         (sysram_base_addr + 0x24) : S5P_INFORM0))
 107 #define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
 108                         S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
 109                         (sysram_base_addr + 0x20) : S5P_INFORM1))
 110
 111 #define S5P_CHECK_AFTR  0xFCBA0D10
 112 #define S5P_CHECK_SLEEP 0x00000BAD
 113
 114 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
 115 static void exynos_set_wakeupmask(long mask)
 116 {
 117         __raw_writel(mask, S5P_WAKEUP_MASK);
 118 }
 119
 120 static void exynos_cpu_set_boot_vector(long flags)
 121 {
 122         __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
 123         __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
 124 }
 125
 126 void exynos_enter_aftr(void)
 127 {
 128         exynos_set_wakeupmask(0x0000ff3e);
 129         exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
 130         /* Set value of power down register for aftr mode */
 131         exynos_sys_powerdown_conf(SYS_AFTR);
 132 }
 133
 134 /* For Cortex-A9 Diagnostic and Power control register */
 135 static unsigned int save_arm_register[2];
 136
 137 static void exynos_cpu_save_register(void)
 138 {
 139         unsigned long tmp;
 140
 141         /* Save Power control register */
 142         asm ("mrc p15, 0, %0, c15, c0, 0"
 143              : "=r" (tmp) : : "cc");
 144
 145         save_arm_register[0] = tmp;
 146
 147         /* Save Diagnostic register */
 148         asm ("mrc p15, 0, %0, c15, c0, 1"
 149              : "=r" (tmp) : : "cc");
 150
 151         save_arm_register[1] = tmp;
 152 }
 153
 154 static void exynos_cpu_restore_register(void)
 155 {
 156         unsigned long tmp;
 157
 158         /* Restore Power control register */
 159         tmp = save_arm_register[0];
 160
 161         asm volatile ("mcr p15, 0, %0, c15, c0, 0"
 162                       : : "r" (tmp)
 163                       : "cc");
 164
 165         /* Restore Diagnostic register */
 166         tmp = save_arm_register[1];
 167
 168         asm volatile ("mcr p15, 0, %0, c15, c0, 1"
 169                       : : "r" (tmp)
 170                       : "cc");
 171 }
 172
 173 static int exynos_cpu_suspend(unsigned long arg)
 174 {
 175 #ifdef CONFIG_CACHE_L2X0
 176         outer_flush_all();
 177 #endif
 178
 179         if (soc_is_exynos5250())
 180                 flush_cache_all();
 181
 182         /* issue the standby signal into the pm unit. */
 183         cpu_do_idle();
 184
 185         pr_info("Failed to suspend the system\n");
 186         return 1; /* Aborting suspend */
 187 }
 188
 189 static void exynos_pm_prepare(void)
 190 {
 191         unsigned int tmp;
 192
 193         /* Set wake-up mask registers */
 194         __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
 195         __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 196
 197         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 198
 199         if (soc_is_exynos5250()) {
 200                 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
 201                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
 202                 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
 203                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 204                 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
 205         }
 206
 207         /* Set value of power down register for sleep mode */
 208
 209         exynos_sys_powerdown_conf(SYS_SLEEP);
 210         __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 211
 212         /* ensure at least INFORM0 has the resume address */
 213
 214         __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 215 }
 216
 217 static void exynos_pm_central_suspend(void)
 218 {
 219         unsigned long tmp;
 220
 221         /* Setting Central Sequence Register for power down mode */
 222         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 223         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 224         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 225 }
 226
 227 static int exynos_pm_suspend(void)
 228 {
 229         unsigned long tmp;
 230
 231         exynos_pm_central_suspend();
 232
 233         /* Setting SEQ_OPTION register */
 234
 235         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 236         __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 237
 238         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 239                 exynos_cpu_save_register();
 240
 241         return 0;
 242 }
 243
 244 static int exynos_pm_central_resume(void)
 245 {
 246         unsigned long tmp;
 247
 248         /*
 249          * If PMU failed while entering sleep mode, WFI will be
 250          * ignored by PMU and then exiting cpu_do_idle().
 251          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 252          * in this situation.
 253          */
 254         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 255         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 256                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 257                 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 258                 /* clear the wakeup state register */
 259                 __raw_writel(0x0, S5P_WAKEUP_STAT);
 260                 /* No need to perform below restore code */
 261                 return -1;
 262         }
 263
 264         return 0;
 265 }
 266
 267 static void exynos_pm_resume(void)
 268 {
 269         if (exynos_pm_central_resume())
 270                 goto early_wakeup;
 271
 272         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 273                 exynos_cpu_restore_register();
 274
 275         /* For release retention */
 276
 277         __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
 278         __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
 279         __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
 280         __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
 281         __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
 282         __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
 283         __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 284
 285         if (soc_is_exynos5250())
 286                 s3c_pm_do_restore(exynos5_sys_save,
 287                         ARRAY_SIZE(exynos5_sys_save));
 288
 289         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 290
 291         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 292                 scu_enable(S5P_VA_SCU);
 293
 294 early_wakeup:
 295
 296         /* Clear SLEEP mode set in INFORM1 */
 297         __raw_writel(0x0, S5P_INFORM1);
 298
 299         return;
 300 }
 301
 302 static struct syscore_ops exynos_pm_syscore_ops = {
 303         .suspend        = exynos_pm_suspend,
 304         .resume         = exynos_pm_resume,
 305 };
 306
 307 /*
 308  * Suspend Ops
 309  */
 310
 311 static int exynos_suspend_enter(suspend_state_t state)
 312 {
 313         int ret;
 314
 315         s3c_pm_debug_init();
 316
 317         S3C_PMDBG("%s: suspending the system...\n", __func__);
 318
 319         S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
 320                         exynos_irqwake_intmask, exynos_get_eint_wake_mask());
 321
 322         if (exynos_irqwake_intmask == -1U
 323             && exynos_get_eint_wake_mask() == -1U) {
 324                 pr_err("%s: No wake-up sources!\n", __func__);
 325                 pr_err("%s: Aborting sleep\n", __func__);
 326                 return -EINVAL;
 327         }
 328
 329         s3c_pm_save_uarts();
 330         exynos_pm_prepare();
 331         flush_cache_all();
 332         s3c_pm_check_store();
 333
 334         ret = cpu_suspend(0, exynos_cpu_suspend);
 335         if (ret)
 336                 return ret;
 337
 338         s3c_pm_restore_uarts();
 339
 340         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
 341                         __raw_readl(S5P_WAKEUP_STAT));
 342
 343         s3c_pm_check_restore();
 344
 345         S3C_PMDBG("%s: resuming the system...\n", __func__);
 346
 347         return 0;
 348 }
 349
 350 static int exynos_suspend_prepare(void)
 351 {
 352         s3c_pm_check_prepare();
 353
 354         return 0;
 355 }
 356
 357 static void exynos_suspend_finish(void)
 358 {
 359         s3c_pm_check_cleanup();
 360 }
 361
 362 static const struct platform_suspend_ops exynos_suspend_ops = {
 363         .enter          = exynos_suspend_enter,
 364         .prepare        = exynos_suspend_prepare,
 365         .finish         = exynos_suspend_finish,
 366         .valid          = suspend_valid_only_mem,
 367 };
 368
 369 static int exynos_cpu_pm_notifier(struct notifier_block *self,
 370                                   unsigned long cmd, void *v)
 371 {
 372         int cpu = smp_processor_id();
 373
 374         switch (cmd) {
 375         case CPU_PM_ENTER:
 376                 if (cpu == 0) {
 377                         exynos_pm_central_suspend();
 378                         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 379                                 exynos_cpu_save_register();
 380                 }
 381                 break;
 382
 383         case CPU_PM_EXIT:
 384                 if (cpu == 0) {
 385                         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
 386                                 scu_enable(S5P_VA_SCU);
 387                                 exynos_cpu_restore_register();
 388                         }
 389                         exynos_pm_central_resume();
 390                 }
 391                 break;
 392         }
 393
 394         return NOTIFY_OK;
 395 }
 396
 397 static struct notifier_block exynos_cpu_pm_notifier_block = {
 398         .notifier_call = exynos_cpu_pm_notifier,
 399 };
 400
 401 void __init exynos_pm_init(void)
 402 {
 403         u32 tmp;
 404
 405         cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
 406
 407         /* Platform-specific GIC callback */
 408         gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 409
 410         /* All wakeup disable */
 411         tmp = __raw_readl(S5P_WAKEUP_MASK);
 412         tmp |= ((0xFF << 8) | (0x1F << 1));
 413         __raw_writel(tmp, S5P_WAKEUP_MASK);
 414
 415         register_syscore_ops(&exynos_pm_syscore_ops);
 416         suspend_set_ops(&exynos_suspend_ops);
 417 }