arch/arm/mach-exynos/suspend.c

   1 /*
   2  * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Suspend support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/cpu_pm.h>
  20 #include <linux/io.h>
  21 #include <linux/irqchip/arm-gic.h>
  22 #include <linux/err.h>
  23 #include <linux/regulator/machine.h>
  24
  25 #include <asm/cacheflush.h>
  26 #include <asm/hardware/cache-l2x0.h>
  27 #include <asm/firmware.h>
  28 #include <asm/mcpm.h>
  29 #include <asm/smp_scu.h>
  30 #include <asm/suspend.h>
  31
  32 #include <plat/pm-common.h>
  33 #include <plat/regs-srom.h>
  34
  35 #include "common.h"
  36 #include "regs-pmu.h"
  37 #include "exynos-pmu.h"
  38
  39 #define S5P_CHECK_SLEEP 0x00000BAD
  40
  41 #define REG_TABLE_END (-1U)
  42
  43 #define EXYNOS5420_CPU_STATE    0x28
  44
  45 /**
  46  * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
  47  * @hwirq: Hardware IRQ signal of the GIC
  48  * @mask: Mask in PMU wake-up mask register
  49  */
  50 struct exynos_wkup_irq {
  51         unsigned int hwirq;
  52         u32 mask;
  53 };
  54
  55 static struct sleep_save exynos_core_save[] = {
  56         /* SROM side */
  57         SAVE_ITEM(S5P_SROM_BW),
  58         SAVE_ITEM(S5P_SROM_BC0),
  59         SAVE_ITEM(S5P_SROM_BC1),
  60         SAVE_ITEM(S5P_SROM_BC2),
  61         SAVE_ITEM(S5P_SROM_BC3),
  62 };
  63
  64 struct exynos_pm_data {
  65         const struct exynos_wkup_irq *wkup_irq;
  66         unsigned int wake_disable_mask;
  67         unsigned int *release_ret_regs;
  68
  69         void (*pm_prepare)(void);
  70         void (*pm_resume_prepare)(void);
  71         void (*pm_resume)(void);
  72         int (*pm_suspend)(void);
  73         int (*cpu_suspend)(unsigned long);
  74 };
  75
  76 static const struct exynos_pm_data *pm_data;
  77
  78 static int exynos5420_cpu_state;
  79 static unsigned int exynos_pmu_spare3;
  80
  81 /*
  82  * GIC wake-up support
  83  */
  84
  85 static u32 exynos_irqwake_intmask = 0xffffffff;
  86
  87 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
  88         { 73, BIT(1) }, /* RTC alarm */
  89         { 74, BIT(2) }, /* RTC tick */
  90         { /* sentinel */ },
  91 };
  92
  93 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
  94         { 76, BIT(1) }, /* RTC alarm */
  95         { 77, BIT(2) }, /* RTC tick */
  96         { /* sentinel */ },
  97 };
  98
  99 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
 100         { 75, BIT(1) }, /* RTC alarm */
 101         { 76, BIT(2) }, /* RTC tick */
 102         { /* sentinel */ },
 103 };
 104
 105 static unsigned int exynos_release_ret_regs[] = {
 106         S5P_PAD_RET_MAUDIO_OPTION,
 107         S5P_PAD_RET_GPIO_OPTION,
 108         S5P_PAD_RET_UART_OPTION,
 109         S5P_PAD_RET_MMCA_OPTION,
 110         S5P_PAD_RET_MMCB_OPTION,
 111         S5P_PAD_RET_EBIA_OPTION,
 112         S5P_PAD_RET_EBIB_OPTION,
 113         REG_TABLE_END,
 114 };
 115
 116 static unsigned int exynos3250_release_ret_regs[] = {
 117         S5P_PAD_RET_MAUDIO_OPTION,
 118         S5P_PAD_RET_GPIO_OPTION,
 119         S5P_PAD_RET_UART_OPTION,
 120         S5P_PAD_RET_MMCA_OPTION,
 121         S5P_PAD_RET_MMCB_OPTION,
 122         S5P_PAD_RET_EBIA_OPTION,
 123         S5P_PAD_RET_EBIB_OPTION,
 124         S5P_PAD_RET_MMC2_OPTION,
 125         S5P_PAD_RET_SPI_OPTION,
 126         REG_TABLE_END,
 127 };
 128
 129 static unsigned int exynos5420_release_ret_regs[] = {
 130         EXYNOS_PAD_RET_DRAM_OPTION,
 131         EXYNOS_PAD_RET_MAUDIO_OPTION,
 132         EXYNOS_PAD_RET_JTAG_OPTION,
 133         EXYNOS5420_PAD_RET_GPIO_OPTION,
 134         EXYNOS5420_PAD_RET_UART_OPTION,
 135         EXYNOS5420_PAD_RET_MMCA_OPTION,
 136         EXYNOS5420_PAD_RET_MMCB_OPTION,
 137         EXYNOS5420_PAD_RET_MMCC_OPTION,
 138         EXYNOS5420_PAD_RET_HSI_OPTION,
 139         EXYNOS_PAD_RET_EBIA_OPTION,
 140         EXYNOS_PAD_RET_EBIB_OPTION,
 141         EXYNOS5420_PAD_RET_SPI_OPTION,
 142         EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
 143         REG_TABLE_END,
 144 };
 145
 146 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
 147 {
 148         const struct exynos_wkup_irq *wkup_irq;
 149
 150         if (!pm_data->wkup_irq)
 151                 return -ENOENT;
 152         wkup_irq = pm_data->wkup_irq;
 153
 154         while (wkup_irq->mask) {
 155                 if (wkup_irq->hwirq == data->hwirq) {
 156                         if (!state)
 157                                 exynos_irqwake_intmask |= wkup_irq->mask;
 158                         else
 159                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
 160                         return 0;
 161                 }
 162                 ++wkup_irq;
 163         }
 164
 165         return -ENOENT;
 166 }
 167
 168 static int exynos_cpu_do_idle(void)
 169 {
 170         /* issue the standby signal into the pm unit. */
 171         cpu_do_idle();
 172
 173         pr_info("Failed to suspend the system\n");
 174         return 1; /* Aborting suspend */
 175 }
 176 static void exynos_flush_cache_all(void)
 177 {
 178         flush_cache_all();
 179         outer_flush_all();
 180 }
 181
 182 static int exynos_cpu_suspend(unsigned long arg)
 183 {
 184         exynos_flush_cache_all();
 185         return exynos_cpu_do_idle();
 186 }
 187
 188 static int exynos3250_cpu_suspend(unsigned long arg)
 189 {
 190         flush_cache_all();
 191         return exynos_cpu_do_idle();
 192 }
 193
 194 static int exynos5420_cpu_suspend(unsigned long arg)
 195 {
 196         /* MCPM works with HW CPU identifiers */
 197         unsigned int mpidr = read_cpuid_mpidr();
 198         unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 199         unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 200
 201         __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
 202
 203         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
 204                 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
 205
 206                 /*
 207                  * Residency value passed to mcpm_cpu_suspend back-end
 208                  * has to be given clear semantics. Set to 0 as a
 209                  * temporary value.
 210                  */
 211                 mcpm_cpu_suspend(0);
 212         }
 213
 214         pr_info("Failed to suspend the system\n");
 215
 216         /* return value != 0 means failure */
 217         return 1;
 218 }
 219
 220 static void exynos_pm_set_wakeup_mask(void)
 221 {
 222         /* Set wake-up mask registers */
 223         pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
 224         pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 225 }
 226
 227 static void exynos_pm_enter_sleep_mode(void)
 228 {
 229         /* Set value of power down register for sleep mode */
 230         exynos_sys_powerdown_conf(SYS_SLEEP);
 231         pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 232 }
 233
 234 static void exynos_pm_prepare(void)
 235 {
 236         /* Set wake-up mask registers */
 237         exynos_pm_set_wakeup_mask();
 238
 239         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 240
 241         exynos_pm_enter_sleep_mode();
 242
 243         /* ensure at least INFORM0 has the resume address */
 244         pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 245 }
 246
 247 static void exynos3250_pm_prepare(void)
 248 {
 249         unsigned int tmp;
 250
 251         /* Set wake-up mask registers */
 252         exynos_pm_set_wakeup_mask();
 253
 254         tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
 255         tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 256         pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
 257
 258         exynos_pm_enter_sleep_mode();
 259
 260         /* ensure at least INFORM0 has the resume address */
 261         pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 262 }
 263
 264 static void exynos5420_pm_prepare(void)
 265 {
 266         unsigned int tmp;
 267
 268         /* Set wake-up mask registers */
 269         exynos_pm_set_wakeup_mask();
 270
 271         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 272
 273         exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
 274         /*
 275          * The cpu state needs to be saved and restored so that the
 276          * secondary CPUs will enter low power start. Though the U-Boot
 277          * is setting the cpu state with low power flag, the kernel
 278          * needs to restore it back in case, the primary cpu fails to
 279          * suspend for any reason.
 280          */
 281         exynos5420_cpu_state = __raw_readl(sysram_base_addr +
 282                                                 EXYNOS5420_CPU_STATE);
 283
 284         exynos_pm_enter_sleep_mode();
 285
 286         /* ensure at least INFORM0 has the resume address */
 287         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
 288                 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
 289
 290         tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
 291         tmp &= ~EXYNOS5_USE_RETENTION;
 292         pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
 293
 294         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
 295         tmp |= EXYNOS5420_UFS;
 296         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
 297
 298         tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
 299         tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
 300         pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
 301
 302         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
 303         tmp |= EXYNOS5420_EMULATION;
 304         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
 305
 306         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
 307         tmp |= EXYNOS5420_EMULATION;
 308         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
 309 }
 310
 311
 312 static int exynos_pm_suspend(void)
 313 {
 314         exynos_pm_central_suspend();
 315
 316         /* Setting SEQ_OPTION register */
 317         pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
 318                        S5P_CENTRAL_SEQ_OPTION);
 319
 320         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 321                 exynos_cpu_save_register();
 322
 323         return 0;
 324 }
 325
 326 static int exynos5420_pm_suspend(void)
 327 {
 328         u32 this_cluster;
 329
 330         exynos_pm_central_suspend();
 331
 332         /* Setting SEQ_OPTION register */
 333
 334         this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
 335         if (!this_cluster)
 336                 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
 337                                 S5P_CENTRAL_SEQ_OPTION);
 338         else
 339                 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
 340                                 S5P_CENTRAL_SEQ_OPTION);
 341         return 0;
 342 }
 343
 344 static void exynos_pm_release_retention(void)
 345 {
 346         unsigned int i;
 347
 348         for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++)
 349                 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR,
 350                                 pm_data->release_ret_regs[i]);
 351 }
 352
 353 static void exynos_pm_resume(void)
 354 {
 355         u32 cpuid = read_cpuid_part();
 356
 357         if (exynos_pm_central_resume())
 358                 goto early_wakeup;
 359
 360         /* For release retention */
 361         exynos_pm_release_retention();
 362
 363         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 364
 365         if (cpuid == ARM_CPU_PART_CORTEX_A9)
 366                 scu_enable(S5P_VA_SCU);
 367
 368         if (call_firmware_op(resume) == -ENOSYS
 369             && cpuid == ARM_CPU_PART_CORTEX_A9)
 370                 exynos_cpu_restore_register();
 371
 372 early_wakeup:
 373
 374         /* Clear SLEEP mode set in INFORM1 */
 375         pmu_raw_writel(0x0, S5P_INFORM1);
 376 }
 377
 378 static void exynos3250_pm_resume(void)
 379 {
 380         u32 cpuid = read_cpuid_part();
 381
 382         if (exynos_pm_central_resume())
 383                 goto early_wakeup;
 384
 385         /* For release retention */
 386         exynos_pm_release_retention();
 387
 388         pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
 389
 390         if (call_firmware_op(resume) == -ENOSYS
 391             && cpuid == ARM_CPU_PART_CORTEX_A9)
 392                 exynos_cpu_restore_register();
 393
 394 early_wakeup:
 395
 396         /* Clear SLEEP mode set in INFORM1 */
 397         pmu_raw_writel(0x0, S5P_INFORM1);
 398 }
 399
 400 static void exynos5420_prepare_pm_resume(void)
 401 {
 402         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
 403                 WARN_ON(mcpm_cpu_powered_up());
 404 }
 405
 406 static void exynos5420_pm_resume(void)
 407 {
 408         unsigned long tmp;
 409
 410         /* Restore the CPU0 low power state register */
 411         tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 412         pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
 413                 EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 414
 415         /* Restore the sysram cpu state register */
 416         __raw_writel(exynos5420_cpu_state,
 417                 sysram_base_addr + EXYNOS5420_CPU_STATE);
 418
 419         pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
 420                         S5P_CENTRAL_SEQ_OPTION);
 421
 422         if (exynos_pm_central_resume())
 423                 goto early_wakeup;
 424
 425         /* For release retention */
 426         exynos_pm_release_retention();
 427
 428         pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
 429
 430         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 431
 432 early_wakeup:
 433
 434         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
 435         tmp &= ~EXYNOS5420_UFS;
 436         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
 437
 438         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
 439         tmp &= ~EXYNOS5420_EMULATION;
 440         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
 441
 442         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
 443         tmp &= ~EXYNOS5420_EMULATION;
 444         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
 445
 446         /* Clear SLEEP mode set in INFORM1 */
 447         pmu_raw_writel(0x0, S5P_INFORM1);
 448 }
 449
 450 /*
 451  * Suspend Ops
 452  */
 453
 454 static int exynos_suspend_enter(suspend_state_t state)
 455 {
 456         int ret;
 457
 458         s3c_pm_debug_init();
 459
 460         S3C_PMDBG("%s: suspending the system...\n", __func__);
 461
 462         S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
 463                         exynos_irqwake_intmask, exynos_get_eint_wake_mask());
 464
 465         if (exynos_irqwake_intmask == -1U
 466             && exynos_get_eint_wake_mask() == -1U) {
 467                 pr_err("%s: No wake-up sources!\n", __func__);
 468                 pr_err("%s: Aborting sleep\n", __func__);
 469                 return -EINVAL;
 470         }
 471
 472         s3c_pm_save_uarts();
 473         if (pm_data->pm_prepare)
 474                 pm_data->pm_prepare();
 475         flush_cache_all();
 476         s3c_pm_check_store();
 477
 478         ret = call_firmware_op(suspend);
 479         if (ret == -ENOSYS)
 480                 ret = cpu_suspend(0, pm_data->cpu_suspend);
 481         if (ret)
 482                 return ret;
 483
 484         if (pm_data->pm_resume_prepare)
 485                 pm_data->pm_resume_prepare();
 486         s3c_pm_restore_uarts();
 487
 488         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
 489                         pmu_raw_readl(S5P_WAKEUP_STAT));
 490
 491         s3c_pm_check_restore();
 492
 493         S3C_PMDBG("%s: resuming the system...\n", __func__);
 494
 495         return 0;
 496 }
 497
 498 static int exynos_suspend_prepare(void)
 499 {
 500         int ret;
 501
 502         /*
 503          * REVISIT: It would be better if struct platform_suspend_ops
 504          * .prepare handler get the suspend_state_t as a parameter to
 505          * avoid hard-coding the suspend to mem state. It's safe to do
 506          * it now only because the suspend_valid_only_mem function is
 507          * used as the .valid callback used to check if a given state
 508          * is supported by the platform anyways.
 509          */
 510         ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
 511         if (ret) {
 512                 pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
 513                 return ret;
 514         }
 515
 516         s3c_pm_check_prepare();
 517
 518         return 0;
 519 }
 520
 521 static void exynos_suspend_finish(void)
 522 {
 523         int ret;
 524
 525         s3c_pm_check_cleanup();
 526
 527         ret = regulator_suspend_finish();
 528         if (ret)
 529                 pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
 530 }
 531
 532 static const struct platform_suspend_ops exynos_suspend_ops = {
 533         .enter          = exynos_suspend_enter,
 534         .prepare        = exynos_suspend_prepare,
 535         .finish         = exynos_suspend_finish,
 536         .valid          = suspend_valid_only_mem,
 537 };
 538
 539 static const struct exynos_pm_data exynos3250_pm_data = {
 540         .wkup_irq       = exynos3250_wkup_irq,
 541         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 542         .release_ret_regs = exynos3250_release_ret_regs,
 543         .pm_suspend     = exynos_pm_suspend,
 544         .pm_resume      = exynos3250_pm_resume,
 545         .pm_prepare     = exynos3250_pm_prepare,
 546         .cpu_suspend    = exynos3250_cpu_suspend,
 547 };
 548
 549 static const struct exynos_pm_data exynos4_pm_data = {
 550         .wkup_irq       = exynos4_wkup_irq,
 551         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 552         .release_ret_regs = exynos_release_ret_regs,
 553         .pm_suspend     = exynos_pm_suspend,
 554         .pm_resume      = exynos_pm_resume,
 555         .pm_prepare     = exynos_pm_prepare,
 556         .cpu_suspend    = exynos_cpu_suspend,
 557 };
 558
 559 static const struct exynos_pm_data exynos5250_pm_data = {
 560         .wkup_irq       = exynos5250_wkup_irq,
 561         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 562         .release_ret_regs = exynos_release_ret_regs,
 563         .pm_suspend     = exynos_pm_suspend,
 564         .pm_resume      = exynos_pm_resume,
 565         .pm_prepare     = exynos_pm_prepare,
 566         .cpu_suspend    = exynos_cpu_suspend,
 567 };
 568
 569 static const struct exynos_pm_data exynos5420_pm_data = {
 570         .wkup_irq       = exynos5250_wkup_irq,
 571         .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
 572         .release_ret_regs = exynos5420_release_ret_regs,
 573         .pm_resume_prepare = exynos5420_prepare_pm_resume,
 574         .pm_resume      = exynos5420_pm_resume,
 575         .pm_suspend     = exynos5420_pm_suspend,
 576         .pm_prepare     = exynos5420_pm_prepare,
 577         .cpu_suspend    = exynos5420_cpu_suspend,
 578 };
 579
 580 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
 581         {
 582                 .compatible = "samsung,exynos3250-pmu",
 583                 .data = &exynos3250_pm_data,
 584         }, {
 585                 .compatible = "samsung,exynos4210-pmu",
 586                 .data = &exynos4_pm_data,
 587         }, {
 588                 .compatible = "samsung,exynos4212-pmu",
 589                 .data = &exynos4_pm_data,
 590         }, {
 591                 .compatible = "samsung,exynos4412-pmu",
 592                 .data = &exynos4_pm_data,
 593         }, {
 594                 .compatible = "samsung,exynos5250-pmu",
 595                 .data = &exynos5250_pm_data,
 596         }, {
 597                 .compatible = "samsung,exynos5420-pmu",
 598                 .data = &exynos5420_pm_data,
 599         },
 600         { /*sentinel*/ },
 601 };
 602
 603 static struct syscore_ops exynos_pm_syscore_ops;
 604
 605 void __init exynos_pm_init(void)
 606 {
 607         const struct of_device_id *match;
 608         u32 tmp;
 609
 610         of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
 611         if (!match) {
 612                 pr_err("Failed to find PMU node\n");
 613                 return;
 614         }
 615         pm_data = (const struct exynos_pm_data *) match->data;
 616
 617         /* Platform-specific GIC callback */
 618         gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 619
 620         /* All wakeup disable */
 621         tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
 622         tmp |= pm_data->wake_disable_mask;
 623         pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
 624
 625         exynos_pm_syscore_ops.suspend   = pm_data->pm_suspend;
 626         exynos_pm_syscore_ops.resume    = pm_data->pm_resume;
 627
 628         register_syscore_ops(&exynos_pm_syscore_ops);
 629         suspend_set_ops(&exynos_suspend_ops);
 630 }