arch/arm/mach-imx/pm-imx6.c

   1 /*
   2  * Copyright 2011-2014 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/init.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/genalloc.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/regmap.h>
  24 #include <linux/suspend.h>
  25 #include <asm/cacheflush.h>
  26 #include <asm/fncpy.h>
  27 #include <asm/proc-fns.h>
  28 #include <asm/suspend.h>
  29 #include <asm/tlb.h>
  30
  31 #include "common.h"
  32 #include "hardware.h"
  33
  34 #define CCR                             0x0
  35 #define BM_CCR_WB_COUNT                 (0x7 << 16)
  36 #define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
  37 #define BM_CCR_RBC_EN                   (0x1 << 27)
  38
  39 #define CLPCR                           0x54
  40 #define BP_CLPCR_LPM                    0
  41 #define BM_CLPCR_LPM                    (0x3 << 0)
  42 #define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
  43 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
  44 #define BM_CLPCR_SBYOS                  (0x1 << 6)
  45 #define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
  46 #define BM_CLPCR_VSTBY                  (0x1 << 8)
  47 #define BP_CLPCR_STBY_COUNT             9
  48 #define BM_CLPCR_STBY_COUNT             (0x3 << 9)
  49 #define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
  50 #define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
  51 #define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
  52 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
  53 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
  54 #define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
  55 #define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
  56 #define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
  57 #define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
  58 #define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
  59 #define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
  60
  61 #define CGPR                            0x64
  62 #define BM_CGPR_INT_MEM_CLK_LPM         (0x1 << 17)
  63
  64 #define MX6Q_SUSPEND_OCRAM_SIZE         0x1000
  65 #define MX6_MAX_MMDC_IO_NUM             33
  66
  67 static void __iomem *ccm_base;
  68 static void __iomem *suspend_ocram_base;
  69 static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
  70
  71 /*
  72  * suspend ocram space layout:
  73  * ======================== high address ======================
  74  *                              .
  75  *                              .
  76  *                              .
  77  *                              ^
  78  *                              ^
  79  *                              ^
  80  *                      imx6_suspend code
  81  *              PM_INFO structure(imx6_cpu_pm_info)
  82  * ======================== low address =======================
  83  */
  84
  85 struct imx6_pm_base {
  86         phys_addr_t pbase;
  87         void __iomem *vbase;
  88 };
  89
  90 struct imx6_pm_socdata {
  91         u32 cpu_type;
  92         const char *mmdc_compat;
  93         const char *src_compat;
  94         const char *iomuxc_compat;
  95         const char *gpc_compat;
  96         const u32 mmdc_io_num;
  97         const u32 *mmdc_io_offset;
  98 };
  99
 100 static const u32 imx6q_mmdc_io_offset[] __initconst = {
 101         0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
 102         0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
 103         0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
 104         0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
 105         0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
 106         0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
 107         0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
 108         0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
 109         0x74c,                      /* GPR_ADDS */
 110 };
 111
 112 static const u32 imx6dl_mmdc_io_offset[] __initconst = {
 113         0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
 114         0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
 115         0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
 116         0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
 117         0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
 118         0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
 119         0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
 120         0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
 121         0x74c,                      /* GPR_ADDS */
 122 };
 123
 124 static const u32 imx6sl_mmdc_io_offset[] __initconst = {
 125         0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
 126         0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
 127         0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
 128         0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
 129         0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
 130 };
 131
 132 static const u32 imx6sx_mmdc_io_offset[] __initconst = {
 133         0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
 134         0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
 135         0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
 136         0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
 137         0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
 138 };
 139
 140 static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
 141         .cpu_type = MXC_CPU_IMX6Q,
 142         .mmdc_compat = "fsl,imx6q-mmdc",
 143         .src_compat = "fsl,imx6q-src",
 144         .iomuxc_compat = "fsl,imx6q-iomuxc",
 145         .gpc_compat = "fsl,imx6q-gpc",
 146         .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
 147         .mmdc_io_offset = imx6q_mmdc_io_offset,
 148 };
 149
 150 static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
 151         .cpu_type = MXC_CPU_IMX6DL,
 152         .mmdc_compat = "fsl,imx6q-mmdc",
 153         .src_compat = "fsl,imx6q-src",
 154         .iomuxc_compat = "fsl,imx6dl-iomuxc",
 155         .gpc_compat = "fsl,imx6q-gpc",
 156         .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
 157         .mmdc_io_offset = imx6dl_mmdc_io_offset,
 158 };
 159
 160 static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
 161         .cpu_type = MXC_CPU_IMX6SL,
 162         .mmdc_compat = "fsl,imx6sl-mmdc",
 163         .src_compat = "fsl,imx6sl-src",
 164         .iomuxc_compat = "fsl,imx6sl-iomuxc",
 165         .gpc_compat = "fsl,imx6sl-gpc",
 166         .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
 167         .mmdc_io_offset = imx6sl_mmdc_io_offset,
 168 };
 169
 170 static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
 171         .cpu_type = MXC_CPU_IMX6SX,
 172         .mmdc_compat = "fsl,imx6sx-mmdc",
 173         .src_compat = "fsl,imx6sx-src",
 174         .iomuxc_compat = "fsl,imx6sx-iomuxc",
 175         .gpc_compat = "fsl,imx6sx-gpc",
 176         .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
 177         .mmdc_io_offset = imx6sx_mmdc_io_offset,
 178 };
 179
 180 /*
 181  * This structure is for passing necessary data for low level ocram
 182  * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
 183  * definition is changed, the offset definition in
 184  * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
 185  * otherwise, the suspend to ocram function will be broken!
 186  */
 187 struct imx6_cpu_pm_info {
 188         phys_addr_t pbase; /* The physical address of pm_info. */
 189         phys_addr_t resume_addr; /* The physical resume address for asm code */
 190         u32 cpu_type;
 191         u32 pm_info_size; /* Size of pm_info. */
 192         struct imx6_pm_base mmdc_base;
 193         struct imx6_pm_base src_base;
 194         struct imx6_pm_base iomuxc_base;
 195         struct imx6_pm_base ccm_base;
 196         struct imx6_pm_base gpc_base;
 197         struct imx6_pm_base l2_base;
 198         u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
 199         u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
 200 } __aligned(8);
 201
 202 void imx6q_set_int_mem_clk_lpm(bool enable)
 203 {
 204         u32 val = readl_relaxed(ccm_base + CGPR);
 205
 206         val &= ~BM_CGPR_INT_MEM_CLK_LPM;
 207         if (enable)
 208                 val |= BM_CGPR_INT_MEM_CLK_LPM;
 209         writel_relaxed(val, ccm_base + CGPR);
 210 }
 211
 212 static void imx6q_enable_rbc(bool enable)
 213 {
 214         u32 val;
 215
 216         /*
 217          * need to mask all interrupts in GPC before
 218          * operating RBC configurations
 219          */
 220         imx_gpc_mask_all();
 221
 222         /* configure RBC enable bit */
 223         val = readl_relaxed(ccm_base + CCR);
 224         val &= ~BM_CCR_RBC_EN;
 225         val |= enable ? BM_CCR_RBC_EN : 0;
 226         writel_relaxed(val, ccm_base + CCR);
 227
 228         /* configure RBC count */
 229         val = readl_relaxed(ccm_base + CCR);
 230         val &= ~BM_CCR_RBC_BYPASS_COUNT;
 231         val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
 232         writel(val, ccm_base + CCR);
 233
 234         /*
 235          * need to delay at least 2 cycles of CKIL(32K)
 236          * due to hardware design requirement, which is
 237          * ~61us, here we use 65us for safe
 238          */
 239         udelay(65);
 240
 241         /* restore GPC interrupt mask settings */
 242         imx_gpc_restore_all();
 243 }
 244
 245 static void imx6q_enable_wb(bool enable)
 246 {
 247         u32 val;
 248
 249         /* configure well bias enable bit */
 250         val = readl_relaxed(ccm_base + CLPCR);
 251         val &= ~BM_CLPCR_WB_PER_AT_LPM;
 252         val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
 253         writel_relaxed(val, ccm_base + CLPCR);
 254
 255         /* configure well bias count */
 256         val = readl_relaxed(ccm_base + CCR);
 257         val &= ~BM_CCR_WB_COUNT;
 258         val |= enable ? BM_CCR_WB_COUNT : 0;
 259         writel_relaxed(val, ccm_base + CCR);
 260 }
 261
 262 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
 263 {
 264         u32 val = readl_relaxed(ccm_base + CLPCR);
 265
 266         val &= ~BM_CLPCR_LPM;
 267         switch (mode) {
 268         case WAIT_CLOCKED:
 269                 break;
 270         case WAIT_UNCLOCKED:
 271                 val |= 0x1 << BP_CLPCR_LPM;
 272                 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
 273                 break;
 274         case STOP_POWER_ON:
 275                 val |= 0x2 << BP_CLPCR_LPM;
 276                 val &= ~BM_CLPCR_VSTBY;
 277                 val &= ~BM_CLPCR_SBYOS;
 278                 if (cpu_is_imx6sl())
 279                         val |= BM_CLPCR_BYPASS_PMIC_READY;
 280                 if (cpu_is_imx6sl() || cpu_is_imx6sx())
 281                         val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
 282                 else
 283                         val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
 284                 break;
 285         case WAIT_UNCLOCKED_POWER_OFF:
 286                 val |= 0x1 << BP_CLPCR_LPM;
 287                 val &= ~BM_CLPCR_VSTBY;
 288                 val &= ~BM_CLPCR_SBYOS;
 289                 break;
 290         case STOP_POWER_OFF:
 291                 val |= 0x2 << BP_CLPCR_LPM;
 292                 val |= 0x3 << BP_CLPCR_STBY_COUNT;
 293                 val |= BM_CLPCR_VSTBY;
 294                 val |= BM_CLPCR_SBYOS;
 295                 if (cpu_is_imx6sl())
 296                         val |= BM_CLPCR_BYPASS_PMIC_READY;
 297                 if (cpu_is_imx6sl() || cpu_is_imx6sx())
 298                         val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
 299                 else
 300                         val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
 301                 break;
 302         default:
 303                 return -EINVAL;
 304         }
 305
 306         /*
 307          * ERR007265: CCM: When improper low-power sequence is used,
 308          * the SoC enters low power mode before the ARM core executes WFI.
 309          *
 310          * Software workaround:
 311          * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
 312          *    by setting IOMUX_GPR1_GINT.
 313          * 2) Software should then unmask IRQ #32 in GPC before setting CCM
 314          *    Low-Power mode.
 315          * 3) Software should mask IRQ #32 right after CCM Low-Power mode
 316          *    is set (set bits 0-1 of CCM_CLPCR).
 317          */
 318         imx_gpc_hwirq_unmask(32);
 319         writel_relaxed(val, ccm_base + CLPCR);
 320         imx_gpc_hwirq_mask(32);
 321
 322         return 0;
 323 }
 324
 325 static int imx6q_suspend_finish(unsigned long val)
 326 {
 327         if (!imx6_suspend_in_ocram_fn) {
 328                 cpu_do_idle();
 329         } else {
 330                 /*
 331                  * call low level suspend function in ocram,
 332                  * as we need to float DDR IO.
 333                  */
 334                 local_flush_tlb_all();
 335                 imx6_suspend_in_ocram_fn(suspend_ocram_base);
 336         }
 337
 338         return 0;
 339 }
 340
 341 static int imx6q_pm_enter(suspend_state_t state)
 342 {
 343         switch (state) {
 344         case PM_SUSPEND_STANDBY:
 345                 imx6q_set_lpm(STOP_POWER_ON);
 346                 imx6q_set_int_mem_clk_lpm(true);
 347                 imx_gpc_pre_suspend(false);
 348                 if (cpu_is_imx6sl())
 349                         imx6sl_set_wait_clk(true);
 350                 /* Zzz ... */
 351                 cpu_do_idle();
 352                 if (cpu_is_imx6sl())
 353                         imx6sl_set_wait_clk(false);
 354                 imx_gpc_post_resume();
 355                 imx6q_set_lpm(WAIT_CLOCKED);
 356                 break;
 357         case PM_SUSPEND_MEM:
 358                 imx6q_set_lpm(STOP_POWER_OFF);
 359                 imx6q_set_int_mem_clk_lpm(false);
 360                 imx6q_enable_wb(true);
 361                 /*
 362                  * For suspend into ocram, asm code already take care of
 363                  * RBC setting, so we do NOT need to do that here.
 364                  */
 365                 if (!imx6_suspend_in_ocram_fn)
 366                         imx6q_enable_rbc(true);
 367                 imx_gpc_pre_suspend(true);
 368                 imx_anatop_pre_suspend();
 369                 imx_set_cpu_jump(0, v7_cpu_resume);
 370                 /* Zzz ... */
 371                 cpu_suspend(0, imx6q_suspend_finish);
 372                 if (cpu_is_imx6q() || cpu_is_imx6dl())
 373                         imx_smp_prepare();
 374                 imx_anatop_post_resume();
 375                 imx_gpc_post_resume();
 376                 imx6q_enable_rbc(false);
 377                 imx6q_enable_wb(false);
 378                 imx6q_set_int_mem_clk_lpm(true);
 379                 imx6q_set_lpm(WAIT_CLOCKED);
 380                 break;
 381         default:
 382                 return -EINVAL;
 383         }
 384
 385         return 0;
 386 }
 387
 388 static int imx6q_pm_valid(suspend_state_t state)
 389 {
 390         return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
 391 }
 392
 393 static const struct platform_suspend_ops imx6q_pm_ops = {
 394         .enter = imx6q_pm_enter,
 395         .valid = imx6q_pm_valid,
 396 };
 397
 398 void __init imx6q_pm_set_ccm_base(void __iomem *base)
 399 {
 400         ccm_base = base;
 401 }
 402
 403 static int __init imx6_pm_get_base(struct imx6_pm_base *base,
 404                                 const char *compat)
 405 {
 406         struct device_node *node;
 407         struct resource res;
 408         int ret = 0;
 409
 410         node = of_find_compatible_node(NULL, NULL, compat);
 411         if (!node) {
 412                 ret = -ENODEV;
 413                 goto out;
 414         }
 415
 416         ret = of_address_to_resource(node, 0, &res);
 417         if (ret)
 418                 goto put_node;
 419
 420         base->pbase = res.start;
 421         base->vbase = ioremap(res.start, resource_size(&res));
 422         if (!base->vbase)
 423                 ret = -ENOMEM;
 424
 425 put_node:
 426         of_node_put(node);
 427 out:
 428         return ret;
 429 }
 430
 431 static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
 432 {
 433         phys_addr_t ocram_pbase;
 434         struct device_node *node;
 435         struct platform_device *pdev;
 436         struct imx6_cpu_pm_info *pm_info;
 437         struct gen_pool *ocram_pool;
 438         unsigned long ocram_base;
 439         int i, ret = 0;
 440         const u32 *mmdc_offset_array;
 441
 442         suspend_set_ops(&imx6q_pm_ops);
 443
 444         if (!socdata) {
 445                 pr_warn("%s: invalid argument!\n", __func__);
 446                 return -EINVAL;
 447         }
 448
 449         node = of_find_compatible_node(NULL, NULL, "mmio-sram");
 450         if (!node) {
 451                 pr_warn("%s: failed to find ocram node!\n", __func__);
 452                 return -ENODEV;
 453         }
 454
 455         pdev = of_find_device_by_node(node);
 456         if (!pdev) {
 457                 pr_warn("%s: failed to find ocram device!\n", __func__);
 458                 ret = -ENODEV;
 459                 goto put_node;
 460         }
 461
 462         ocram_pool = dev_get_gen_pool(&pdev->dev);
 463         if (!ocram_pool) {
 464                 pr_warn("%s: ocram pool unavailable!\n", __func__);
 465                 ret = -ENODEV;
 466                 goto put_node;
 467         }
 468
 469         ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
 470         if (!ocram_base) {
 471                 pr_warn("%s: unable to alloc ocram!\n", __func__);
 472                 ret = -ENOMEM;
 473                 goto put_node;
 474         }
 475
 476         ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
 477
 478         suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
 479                 MX6Q_SUSPEND_OCRAM_SIZE, false);
 480
 481         pm_info = suspend_ocram_base;
 482         pm_info->pbase = ocram_pbase;
 483         pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
 484         pm_info->pm_info_size = sizeof(*pm_info);
 485
 486         /*
 487          * ccm physical address is not used by asm code currently,
 488          * so get ccm virtual address directly, as we already have
 489          * it from ccm driver.
 490          */
 491         pm_info->ccm_base.vbase = ccm_base;
 492
 493         ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
 494         if (ret) {
 495                 pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
 496                 goto put_node;
 497         }
 498
 499         ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
 500         if (ret) {
 501                 pr_warn("%s: failed to get src base %d!\n", __func__, ret);
 502                 goto src_map_failed;
 503         }
 504
 505         ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
 506         if (ret) {
 507                 pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
 508                 goto iomuxc_map_failed;
 509         }
 510
 511         ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
 512         if (ret) {
 513                 pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
 514                 goto gpc_map_failed;
 515         }
 516
 517         ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache");
 518         if (ret) {
 519                 pr_warn("%s: failed to get pl310-cache base %d!\n",
 520                         __func__, ret);
 521                 goto pl310_cache_map_failed;
 522         }
 523
 524         pm_info->cpu_type = socdata->cpu_type;
 525         pm_info->mmdc_io_num = socdata->mmdc_io_num;
 526         mmdc_offset_array = socdata->mmdc_io_offset;
 527
 528         for (i = 0; i < pm_info->mmdc_io_num; i++) {
 529                 pm_info->mmdc_io_val[i][0] =
 530                         mmdc_offset_array[i];
 531                 pm_info->mmdc_io_val[i][1] =
 532                         readl_relaxed(pm_info->iomuxc_base.vbase +
 533                         mmdc_offset_array[i]);
 534         }
 535
 536         imx6_suspend_in_ocram_fn = fncpy(
 537                 suspend_ocram_base + sizeof(*pm_info),
 538                 &imx6_suspend,
 539                 MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
 540
 541         goto put_node;
 542
 543 pl310_cache_map_failed:
 544         iounmap(&pm_info->gpc_base.vbase);
 545 gpc_map_failed:
 546         iounmap(&pm_info->iomuxc_base.vbase);
 547 iomuxc_map_failed:
 548         iounmap(&pm_info->src_base.vbase);
 549 src_map_failed:
 550         iounmap(&pm_info->mmdc_base.vbase);
 551 put_node:
 552         of_node_put(node);
 553
 554         return ret;
 555 }
 556
 557 static void __init imx6_pm_common_init(const struct imx6_pm_socdata
 558                                         *socdata)
 559 {
 560         struct regmap *gpr;
 561         int ret;
 562
 563         WARN_ON(!ccm_base);
 564
 565         if (IS_ENABLED(CONFIG_SUSPEND)) {
 566                 ret = imx6q_suspend_init(socdata);
 567                 if (ret)
 568                         pr_warn("%s: No DDR LPM support with suspend %d!\n",
 569                                 __func__, ret);
 570         }
 571
 572         /*
 573          * This is for SW workaround step #1 of ERR007265, see comments
 574          * in imx6q_set_lpm for details of this errata.
 575          * Force IOMUXC irq pending, so that the interrupt to GPC can be
 576          * used to deassert dsm_request signal when the signal gets
 577          * asserted unexpectedly.
 578          */
 579         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 580         if (!IS_ERR(gpr))
 581                 regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
 582                                    IMX6Q_GPR1_GINT);
 583 }
 584
 585 void __init imx6q_pm_init(void)
 586 {
 587         imx6_pm_common_init(&imx6q_pm_data);
 588 }
 589
 590 void __init imx6dl_pm_init(void)
 591 {
 592         imx6_pm_common_init(&imx6dl_pm_data);
 593 }
 594
 595 void __init imx6sl_pm_init(void)
 596 {
 597         imx6_pm_common_init(&imx6sl_pm_data);
 598 }
 599
 600 void __init imx6sx_pm_init(void)
 601 {
 602         imx6_pm_common_init(&imx6sx_pm_data);
 603 }