2 * arch/arm/mach-kirkwood/pcie.c
4 * PCIe functions for Marvell Kirkwood SoCs
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
14 #include <linux/clk.h>
15 #include <video/vga.h>
17 #include <asm/mach/pci.h>
18 #include <plat/pcie.h>
19 #include <mach/bridge-regs.h>
20 #include <plat/addr-map.h>
23 static void kirkwood_enable_pcie_clk(const char *port)
27 clk = clk_get_sys("pcie", port);
29 pr_err("PCIE clock %s missing\n", port);
32 clk_prepare_enable(clk);
36 /* This function is called very early in the boot when probing the
37 hardware to determine what we actually are, and what rate tclk is
38 ticking at. Hence calling kirkwood_enable_pcie_clk() is not
39 possible since the clk tree has not been created yet. */
40 void kirkwood_enable_pcie(void)
42 u32 curr = readl(CLOCK_GATING_CTRL);
43 if (!(curr & CGC_PEX0))
44 writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
47 void kirkwood_pcie_id(u32 *dev, u32 *rev)
49 kirkwood_enable_pcie();
50 *dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
51 *rev = orion_pcie_rev(PCIE_VIRT_BASE);
62 static int pcie_port_map[2];
63 static int num_pcie_ports;
65 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
68 * Don't go out when trying to access --
69 * 1. nonexisting device on local bus
70 * 2. where there's no device connected (no link)
72 if (bus == pp->root_bus_nr && dev == 0)
75 if (!orion_pcie_link_up(pp->base))
78 if (bus == pp->root_bus_nr && dev != 1)
86 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
87 * and then reading the PCIE_CONF_DATA register. Need to make sure these
88 * transactions are atomic.
91 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
94 struct pci_sys_data *sys = bus->sysdata;
95 struct pcie_port *pp = sys->private_data;
99 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
101 return PCIBIOS_DEVICE_NOT_FOUND;
104 spin_lock_irqsave(&pp->conf_lock, flags);
105 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
106 spin_unlock_irqrestore(&pp->conf_lock, flags);
111 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
112 int where, int size, u32 val)
114 struct pci_sys_data *sys = bus->sysdata;
115 struct pcie_port *pp = sys->private_data;
119 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
120 return PCIBIOS_DEVICE_NOT_FOUND;
122 spin_lock_irqsave(&pp->conf_lock, flags);
123 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
124 spin_unlock_irqrestore(&pp->conf_lock, flags);
129 static struct pci_ops pcie_ops = {
130 .read = pcie_rd_conf,
131 .write = pcie_wr_conf,
134 static void __init pcie0_ioresources_init(struct pcie_port *pp)
136 pp->base = PCIE_VIRT_BASE;
137 pp->irq = IRQ_KIRKWOOD_PCIE;
142 pp->res.name = "PCIe 0 MEM";
143 pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
144 pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
145 pp->res.flags = IORESOURCE_MEM;
148 static void __init pcie1_ioresources_init(struct pcie_port *pp)
150 pp->base = PCIE1_VIRT_BASE;
151 pp->irq = IRQ_KIRKWOOD_PCIE1;
156 pp->res.name = "PCIe 1 MEM";
157 pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
158 pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
159 pp->res.flags = IORESOURCE_MEM;
162 static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
164 struct pcie_port *pp;
167 if (nr >= num_pcie_ports)
170 index = pcie_port_map[nr];
171 pr_info("PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
173 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
175 panic("PCIe: failed to allocate pcie_port data");
176 sys->private_data = pp;
177 pp->root_bus_nr = sys->busnr;
178 spin_lock_init(&pp->conf_lock);
182 kirkwood_enable_pcie_clk("0");
183 pcie0_ioresources_init(pp);
184 pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
187 kirkwood_enable_pcie_clk("1");
188 pcie1_ioresources_init(pp);
189 pci_ioremap_io(SZ_64K * sys->busnr,
190 KIRKWOOD_PCIE1_IO_PHYS_BASE);
193 panic("PCIe setup: invalid controller %d", index);
196 if (request_resource(&iomem_resource, &pp->res))
197 panic("Request PCIe%d Memory resource failed\n", index);
199 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
202 * Generic PCIe unit setup.
204 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
206 orion_pcie_setup(pp->base);
211 static void __devinit rc_pci_fixup(struct pci_dev *dev)
214 * Prevent enumeration of root complex.
216 if (dev->bus->parent == NULL && dev->devfn == 0) {
219 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
220 dev->resource[i].start = 0;
221 dev->resource[i].end = 0;
222 dev->resource[i].flags = 0;
226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
228 static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
231 struct pci_sys_data *sys = dev->sysdata;
232 struct pcie_port *pp = sys->private_data;
237 static struct hw_pci kirkwood_pci __initdata = {
238 .setup = kirkwood_pcie_setup,
239 .map_irq = kirkwood_pcie_map_irq,
243 static void __init add_pcie_port(int index, void __iomem *base)
245 pr_info("Kirkwood PCIe port %d: ", index);
247 if (orion_pcie_link_up(base)) {
248 pr_info("link up\n");
249 pcie_port_map[num_pcie_ports++] = index;
251 pr_info("link down, ignoring\n");
254 void __init kirkwood_pcie_init(unsigned int portmask)
256 vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
258 if (portmask & KW_PCIE0)
259 add_pcie_port(0, PCIE_VIRT_BASE);
261 if (portmask & KW_PCIE1)
262 add_pcie_port(1, PCIE1_VIRT_BASE);
264 kirkwood_pci.nr_controllers = num_pcie_ports;
265 pci_common_init(&kirkwood_pci);