arch/arm/mach-omap2/gpmc-nand.c

   1 /*
   2  * gpmc-nand.c
   3  *
   4  * Copyright (C) 2009 Texas Instruments
   5  * Vimal Singh <vimalsingh@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/io.h>
  15 #include <linux/mtd/nand.h>
  16 #include <linux/platform_data/mtd-nand-omap2.h>
  17
  18 #include <asm/mach/flash.h>
  19
  20 #include "gpmc.h"
  21 #include "soc.h"
  22 #include "gpmc-nand.h"
  23
  24 /* minimum size for IO mapping */
  25 #define NAND_IO_SIZE    4
  26
  27 static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
  28 {
  29         /* platforms which support all ECC schemes */
  30         if (soc_is_am33xx() || soc_is_am43xx() || cpu_is_omap44xx() ||
  31                  soc_is_omap54xx() || soc_is_dra7xx())
  32                 return 1;
  33
  34         if (ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW ||
  35                  ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW) {
  36                 if (cpu_is_omap24xx())
  37                         return 0;
  38                 else if (cpu_is_omap3630() && (GET_OMAP_REVISION() == 0))
  39                         return 0;
  40                 else
  41                         return 1;
  42         }
  43
  44         /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes
  45          * which require H/W based ECC error detection */
  46         if ((cpu_is_omap34xx() || cpu_is_omap3630()) &&
  47             ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
  48                  (ecc_opt == OMAP_ECC_BCH8_CODE_HW)))
  49                 return 0;
  50
  51         /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
  52         if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
  53                 return 1;
  54         else
  55                 return 0;
  56 }
  57
  58 /* This function will go away once the device-tree convertion is complete */
  59 static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data,
  60                             struct gpmc_settings *s)
  61 {
  62         /* Enable RD PIN Monitoring Reg */
  63         if (gpmc_nand_data->dev_ready) {
  64                 s->wait_on_read = true;
  65                 s->wait_on_write = true;
  66         }
  67
  68         if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
  69                 s->device_width = GPMC_DEVWIDTH_16BIT;
  70         else
  71                 s->device_width = GPMC_DEVWIDTH_8BIT;
  72 }
  73
  74 int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
  75                    struct gpmc_timings *gpmc_t)
  76 {
  77         int err = 0;
  78         struct gpmc_settings s;
  79         struct platform_device *pdev;
  80         struct resource gpmc_nand_res[] = {
  81                 { .flags = IORESOURCE_MEM, },
  82                 { .flags = IORESOURCE_IRQ, },
  83                 { .flags = IORESOURCE_IRQ, },
  84         };
  85
  86         BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM);
  87
  88         err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
  89                               (unsigned long *)&gpmc_nand_res[0].start);
  90         if (err < 0) {
  91                 pr_err("omap2-gpmc: Cannot request GPMC CS %d, error %d\n",
  92                        gpmc_nand_data->cs, err);
  93                 return err;
  94         }
  95         gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1;
  96         gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
  97         gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
  98
  99         if (gpmc_t) {
 100                 err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
 101                 if (err < 0) {
 102                         pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n", err);
 103                         return err;
 104                 }
 105         }
 106
 107         memset(&s, 0, sizeof(struct gpmc_settings));
 108         if (gpmc_nand_data->of_node)
 109                 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
 110         else
 111                 gpmc_set_legacy(gpmc_nand_data, &s);
 112
 113         s.device_nand = true;
 114         err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
 115         if (err < 0)
 116                 goto out_free_cs;
 117
 118         err = gpmc_configure(GPMC_CONFIG_WP, 0);
 119         if (err < 0)
 120                 goto out_free_cs;
 121
 122         gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
 123
 124         if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
 125                 pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n");
 126                 err = -EINVAL;
 127                 goto out_free_cs;
 128         }
 129
 130
 131         pdev = platform_device_alloc("omap2-nand", gpmc_nand_data->cs);
 132         if (pdev) {
 133                 err = platform_device_add_resources(pdev, gpmc_nand_res,
 134                                                     ARRAY_SIZE(gpmc_nand_res));
 135                 if (!err)
 136                         pdev->dev.platform_data = gpmc_nand_data;
 137         } else {
 138                 err = -ENOMEM;
 139         }
 140         if (err)
 141                 goto out_free_pdev;
 142
 143         err = platform_device_add(pdev);
 144         if (err) {
 145                 dev_err(&pdev->dev, "Unable to register NAND device\n");
 146                 goto out_free_pdev;
 147         }
 148
 149         return 0;
 150
 151 out_free_pdev:
 152         platform_device_put(pdev);
 153 out_free_cs:
 154         gpmc_cs_free(gpmc_nand_data->cs);
 155
 156         return err;
 157 }