arch/arm/mach-omap2/omap-mpuss-lowpower.c

   1 /*
   2  * OMAP MPUSS low power code
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   6  *
   7  * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
   8  * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
   9  * CPU0 and CPU1 LPRM modules.
  10  * CPU0, CPU1 and MPUSS each have there own power domain and
  11  * hence multiple low power combinations of MPUSS are possible.
  12  *
  13  * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
  14  * because the mode is not supported by hw constraints of dormant
  15  * mode. While waking up from the dormant mode, a reset  signal
  16  * to the Cortex-A9 processor must be asserted by the external
  17  * power controller.
  18  *
  19  * With architectural inputs and hardware recommendations, only
  20  * below modes are supported from power gain vs latency point of view.
  21  *
  22  *      CPU0            CPU1            MPUSS
  23  *      ----------------------------------------------
  24  *      ON              ON              ON
  25  *      ON(Inactive)    OFF             ON(Inactive)
  26  *      OFF             OFF             CSWR
  27  *      OFF             OFF             OSWR
  28  *      OFF             OFF             OFF(Device OFF *TBD)
  29  *      ----------------------------------------------
  30  *
  31  * Note: CPU0 is the master core and it is the last CPU to go down
  32  * and first to wake-up when MPUSS low power states are excercised
  33  *
  34  *
  35  * This program is free software; you can redistribute it and/or modify
  36  * it under the terms of the GNU General Public License version 2 as
  37  * published by the Free Software Foundation.
  38  */
  39
  40 #include <linux/kernel.h>
  41 #include <linux/io.h>
  42 #include <linux/errno.h>
  43 #include <linux/linkage.h>
  44 #include <linux/smp.h>
  45
  46 #include <asm/cacheflush.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/smp_scu.h>
  49 #include <asm/pgalloc.h>
  50 #include <asm/suspend.h>
  51 #include <asm/hardware/cache-l2x0.h>
  52
  53 #include "soc.h"
  54 #include "common.h"
  55 #include "omap44xx.h"
  56 #include "omap4-sar-layout.h"
  57 #include "pm.h"
  58 #include "prcm_mpu44xx.h"
  59 #include "prminst44xx.h"
  60 #include "prcm44xx.h"
  61 #include "prm44xx.h"
  62 #include "prm-regbits-44xx.h"
  63
  64 #ifdef CONFIG_SMP
  65
  66 struct omap4_cpu_pm_info {
  67         struct powerdomain *pwrdm;
  68         void __iomem *scu_sar_addr;
  69         void __iomem *wkup_sar_addr;
  70         void __iomem *l2x0_sar_addr;
  71         void (*secondary_startup)(void);
  72 };
  73
  74 /**
  75  * struct cpu_pm_ops - CPU pm operations
  76  * @finish_suspend:     CPU suspend finisher function pointer
  77  * @resume:             CPU resume function pointer
  78  * @scu_prepare:        CPU Snoop Control program function pointer
  79  *
  80  * Structure holds functions pointer for CPU low power operations like
  81  * suspend, resume and scu programming.
  82  */
  83 struct cpu_pm_ops {
  84         int (*finish_suspend)(unsigned long cpu_state);
  85         void (*resume)(void);
  86         void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
  87 };
  88
  89 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
  90 static struct powerdomain *mpuss_pd;
  91 static void __iomem *sar_base;
  92
  93 static int default_finish_suspend(unsigned long cpu_state)
  94 {
  95         omap_do_wfi();
  96         return 0;
  97 }
  98
  99 static void dummy_cpu_resume(void)
 100 {}
 101
 102 static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
 103 {}
 104
 105 struct cpu_pm_ops omap_pm_ops = {
 106         .finish_suspend         = default_finish_suspend,
 107         .resume                 = dummy_cpu_resume,
 108         .scu_prepare            = dummy_scu_prepare,
 109 };
 110
 111 /*
 112  * Program the wakeup routine address for the CPU0 and CPU1
 113  * used for OFF or DORMANT wakeup.
 114  */
 115 static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
 116 {
 117         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 118
 119         __raw_writel(addr, pm_info->wkup_sar_addr);
 120 }
 121
 122 /*
 123  * Store the SCU power status value to scratchpad memory
 124  */
 125 static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
 126 {
 127         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 128         u32 scu_pwr_st;
 129
 130         switch (cpu_state) {
 131         case PWRDM_POWER_RET:
 132                 scu_pwr_st = SCU_PM_DORMANT;
 133                 break;
 134         case PWRDM_POWER_OFF:
 135                 scu_pwr_st = SCU_PM_POWEROFF;
 136                 break;
 137         case PWRDM_POWER_ON:
 138         case PWRDM_POWER_INACTIVE:
 139         default:
 140                 scu_pwr_st = SCU_PM_NORMAL;
 141                 break;
 142         }
 143
 144         __raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
 145 }
 146
 147 /* Helper functions for MPUSS OSWR */
 148 static inline void mpuss_clear_prev_logic_pwrst(void)
 149 {
 150         u32 reg;
 151
 152         reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 153                 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
 154         omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
 155                 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
 156 }
 157
 158 static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
 159 {
 160         u32 reg;
 161
 162         if (cpu_id) {
 163                 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
 164                                         OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
 165                 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
 166                                         OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
 167         } else {
 168                 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
 169                                         OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
 170                 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
 171                                         OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
 172         }
 173 }
 174
 175 /*
 176  * Store the CPU cluster state for L2X0 low power operations.
 177  */
 178 static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
 179 {
 180         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 181
 182         __raw_writel(save_state, pm_info->l2x0_sar_addr);
 183 }
 184
 185 /*
 186  * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
 187  * in every restore MPUSS OFF path.
 188  */
 189 #ifdef CONFIG_CACHE_L2X0
 190 static void save_l2x0_context(void)
 191 {
 192         u32 val;
 193         void __iomem *l2x0_base = omap4_get_l2cache_base();
 194         if (l2x0_base) {
 195                 val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
 196                 __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
 197                 val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
 198                 __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
 199         }
 200 }
 201 #else
 202 static void save_l2x0_context(void)
 203 {}
 204 #endif
 205
 206 /**
 207  * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
 208  * The purpose of this function is to manage low power programming
 209  * of OMAP4 MPUSS subsystem
 210  * @cpu : CPU ID
 211  * @power_state: Low power state.
 212  *
 213  * MPUSS states for the context save:
 214  * save_state =
 215  *      0 - Nothing lost and no need to save: MPUSS INACTIVE
 216  *      1 - CPUx L1 and logic lost: MPUSS CSWR
 217  *      2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
 218  *      3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
 219  */
 220 int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 221 {
 222         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
 223         unsigned int save_state = 0;
 224         unsigned int wakeup_cpu;
 225
 226         if (omap_rev() == OMAP4430_REV_ES1_0)
 227                 return -ENXIO;
 228
 229         switch (power_state) {
 230         case PWRDM_POWER_ON:
 231         case PWRDM_POWER_INACTIVE:
 232                 save_state = 0;
 233                 break;
 234         case PWRDM_POWER_OFF:
 235                 save_state = 1;
 236                 break;
 237         case PWRDM_POWER_RET:
 238         default:
 239                 /*
 240                  * CPUx CSWR is invalid hardware state. Also CPUx OSWR
 241                  * doesn't make much scense, since logic is lost and $L1
 242                  * needs to be cleaned because of coherency. This makes
 243                  * CPUx OSWR equivalent to CPUX OFF and hence not supported
 244                  */
 245                 WARN_ON(1);
 246                 return -ENXIO;
 247         }
 248
 249         pwrdm_pre_transition(NULL);
 250
 251         /*
 252          * Check MPUSS next state and save interrupt controller if needed.
 253          * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
 254          */
 255         mpuss_clear_prev_logic_pwrst();
 256         if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
 257                 (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
 258                 save_state = 2;
 259
 260         cpu_clear_prev_logic_pwrst(cpu);
 261         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
 262         set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
 263         omap_pm_ops.scu_prepare(cpu, power_state);
 264         l2x0_pwrst_prepare(cpu, save_state);
 265
 266         /*
 267          * Call low level function  with targeted low power state.
 268          */
 269         if (save_state)
 270                 cpu_suspend(save_state, omap_pm_ops.finish_suspend);
 271         else
 272                 omap_pm_ops.finish_suspend(save_state);
 273
 274         if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
 275                 gic_dist_enable();
 276
 277         /*
 278          * Restore the CPUx power state to ON otherwise CPUx
 279          * power domain can transitions to programmed low power
 280          * state while doing WFI outside the low powe code. On
 281          * secure devices, CPUx does WFI which can result in
 282          * domain transition
 283          */
 284         wakeup_cpu = smp_processor_id();
 285         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 286
 287         pwrdm_post_transition(NULL);
 288
 289         return 0;
 290 }
 291
 292 /**
 293  * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
 294  * @cpu : CPU ID
 295  * @power_state: CPU low power state.
 296  */
 297 int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 298 {
 299         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
 300         unsigned int cpu_state = 0;
 301
 302         if (omap_rev() == OMAP4430_REV_ES1_0)
 303                 return -ENXIO;
 304
 305         if (power_state == PWRDM_POWER_OFF)
 306                 cpu_state = 1;
 307
 308         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 309         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
 310         set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
 311         omap_pm_ops.scu_prepare(cpu, power_state);
 312
 313         /*
 314          * CPU never retuns back if targeted power state is OFF mode.
 315          * CPU ONLINE follows normal CPU ONLINE ptah via
 316          * omap4_secondary_startup().
 317          */
 318         omap_pm_ops.finish_suspend(cpu_state);
 319
 320         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 321         return 0;
 322 }
 323
 324
 325 /*
 326  * Initialise OMAP4 MPUSS
 327  */
 328 int __init omap4_mpuss_init(void)
 329 {
 330         struct omap4_cpu_pm_info *pm_info;
 331
 332         if (omap_rev() == OMAP4430_REV_ES1_0) {
 333                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
 334                 return -ENODEV;
 335         }
 336
 337         sar_base = omap4_get_sar_ram_base();
 338
 339         /* Initilaise per CPU PM information */
 340         pm_info = &per_cpu(omap4_pm_info, 0x0);
 341         pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
 342         pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
 343         pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
 344         pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
 345         if (!pm_info->pwrdm) {
 346                 pr_err("Lookup failed for CPU0 pwrdm\n");
 347                 return -ENODEV;
 348         }
 349
 350         /* Clear CPU previous power domain state */
 351         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 352         cpu_clear_prev_logic_pwrst(0);
 353
 354         /* Initialise CPU0 power domain state to ON */
 355         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 356
 357         pm_info = &per_cpu(omap4_pm_info, 0x1);
 358         pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
 359         pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
 360         pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
 361         if (cpu_is_omap446x())
 362                 pm_info->secondary_startup = omap4460_secondary_startup;
 363         else
 364                 pm_info->secondary_startup = omap4_secondary_startup;
 365
 366         pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
 367         if (!pm_info->pwrdm) {
 368                 pr_err("Lookup failed for CPU1 pwrdm\n");
 369                 return -ENODEV;
 370         }
 371
 372         /* Clear CPU previous power domain state */
 373         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 374         cpu_clear_prev_logic_pwrst(1);
 375
 376         /* Initialise CPU1 power domain state to ON */
 377         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 378
 379         mpuss_pd = pwrdm_lookup("mpu_pwrdm");
 380         if (!mpuss_pd) {
 381                 pr_err("Failed to lookup MPUSS power domain\n");
 382                 return -ENODEV;
 383         }
 384         pwrdm_clear_all_prev_pwrst(mpuss_pd);
 385         mpuss_clear_prev_logic_pwrst();
 386
 387         /* Save device type on scratchpad for low level code to use */
 388         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 389                 __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
 390         else
 391                 __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
 392
 393         save_l2x0_context();
 394
 395         if (cpu_is_omap44xx()) {
 396                 omap_pm_ops.finish_suspend = omap4_finish_suspend;
 397                 omap_pm_ops.resume = omap4_cpu_resume;
 398                 omap_pm_ops.scu_prepare = scu_pwrst_prepare;
 399         }
 400
 401         return 0;
 402 }
 403
 404 #endif