arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Hwmod common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_data/gpio-omap.h>
  18 #include <linux/platform_data/hsmmc-omap.h>
  19 #include <linux/platform_data/spi-omap2-mcspi.h>
  20 #include "omap_hwmod.h"
  21 #include "i2c.h"
  22 #include "wd_timer.h"
  23 #include "cm33xx.h"
  24 #include "prm33xx.h"
  25 #include "omap_hwmod_33xx_43xx_common_data.h"
  26 #include "prcm43xx.h"
  27 #include "common.h"
  28
  29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
  30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
  31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
  32
  33 /*
  34  * 'l3' class
  35  * instance(s): l3_main, l3_s, l3_instr
  36  */
  37 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  38         .name           = "l3",
  39 };
  40
  41 struct omap_hwmod am33xx_l3_main_hwmod = {
  42         .name           = "l3_main",
  43         .class          = &am33xx_l3_hwmod_class,
  44         .clkdm_name     = "l3_clkdm",
  45         .flags          = HWMOD_INIT_NO_IDLE,
  46         .main_clk       = "l3_gclk",
  47         .prcm           = {
  48                 .omap4  = {
  49                         .modulemode     = MODULEMODE_SWCTRL,
  50                 },
  51         },
  52 };
  53
  54 /* l3_s */
  55 struct omap_hwmod am33xx_l3_s_hwmod = {
  56         .name           = "l3_s",
  57         .class          = &am33xx_l3_hwmod_class,
  58         .clkdm_name     = "l3s_clkdm",
  59 };
  60
  61 /* l3_instr */
  62 struct omap_hwmod am33xx_l3_instr_hwmod = {
  63         .name           = "l3_instr",
  64         .class          = &am33xx_l3_hwmod_class,
  65         .clkdm_name     = "l3_clkdm",
  66         .flags          = HWMOD_INIT_NO_IDLE,
  67         .main_clk       = "l3_gclk",
  68         .prcm           = {
  69                 .omap4  = {
  70                         .modulemode     = MODULEMODE_SWCTRL,
  71                 },
  72         },
  73 };
  74
  75 /*
  76  * 'l4' class
  77  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  78  */
  79 struct omap_hwmod_class am33xx_l4_hwmod_class = {
  80         .name           = "l4",
  81 };
  82
  83 /* l4_ls */
  84 struct omap_hwmod am33xx_l4_ls_hwmod = {
  85         .name           = "l4_ls",
  86         .class          = &am33xx_l4_hwmod_class,
  87         .clkdm_name     = "l4ls_clkdm",
  88         .flags          = HWMOD_INIT_NO_IDLE,
  89         .main_clk       = "l4ls_gclk",
  90         .prcm           = {
  91                 .omap4  = {
  92                         .modulemode     = MODULEMODE_SWCTRL,
  93                 },
  94         },
  95 };
  96
  97 /* l4_wkup */
  98 struct omap_hwmod am33xx_l4_wkup_hwmod = {
  99         .name           = "l4_wkup",
 100         .class          = &am33xx_l4_hwmod_class,
 101         .clkdm_name     = "l4_wkup_clkdm",
 102         .flags          = HWMOD_INIT_NO_IDLE,
 103         .prcm           = {
 104                 .omap4  = {
 105                         .modulemode     = MODULEMODE_SWCTRL,
 106                 },
 107         },
 108 };
 109
 110 /*
 111  * 'mpu' class
 112  */
 113 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 114         .name   = "mpu",
 115 };
 116
 117 struct omap_hwmod am33xx_mpu_hwmod = {
 118         .name           = "mpu",
 119         .class          = &am33xx_mpu_hwmod_class,
 120         .clkdm_name     = "mpu_clkdm",
 121         .flags          = HWMOD_INIT_NO_IDLE,
 122         .main_clk       = "dpll_mpu_m2_ck",
 123         .prcm           = {
 124                 .omap4  = {
 125                         .modulemode     = MODULEMODE_SWCTRL,
 126                 },
 127         },
 128 };
 129
 130 /*
 131  * 'wakeup m3' class
 132  * Wakeup controller sub-system under wakeup domain
 133  */
 134 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 135         .name           = "wkup_m3",
 136 };
 137
 138 /*
 139  * 'pru-icss' class
 140  * Programmable Real-Time Unit and Industrial Communication Subsystem
 141  */
 142 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 143         .name   = "pruss",
 144 };
 145
 146 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 147         { .name = "pruss", .rst_shift = 1 },
 148 };
 149
 150 /* pru-icss */
 151 /* Pseudo hwmod for reset control purpose only */
 152 struct omap_hwmod am33xx_pruss_hwmod = {
 153         .name           = "pruss",
 154         .class          = &am33xx_pruss_hwmod_class,
 155         .clkdm_name     = "pruss_ocp_clkdm",
 156         .main_clk       = "pruss_ocp_gclk",
 157         .prcm           = {
 158                 .omap4  = {
 159                         .modulemode     = MODULEMODE_SWCTRL,
 160                 },
 161         },
 162         .rst_lines      = am33xx_pruss_resets,
 163         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 164 };
 165
 166 /* gfx */
 167 /* Pseudo hwmod for reset control purpose only */
 168 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 169         .name   = "gfx",
 170 };
 171
 172 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 173         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 174 };
 175
 176 struct omap_hwmod am33xx_gfx_hwmod = {
 177         .name           = "gfx",
 178         .class          = &am33xx_gfx_hwmod_class,
 179         .clkdm_name     = "gfx_l3_clkdm",
 180         .main_clk       = "gfx_fck_div_ck",
 181         .prcm           = {
 182                 .omap4  = {
 183                         .modulemode     = MODULEMODE_SWCTRL,
 184                 },
 185         },
 186         .rst_lines      = am33xx_gfx_resets,
 187         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 188 };
 189
 190 /*
 191  * 'prcm' class
 192  * power and reset manager (whole prcm infrastructure)
 193  */
 194 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 195         .name   = "prcm",
 196 };
 197
 198 /* prcm */
 199 struct omap_hwmod am33xx_prcm_hwmod = {
 200         .name           = "prcm",
 201         .class          = &am33xx_prcm_hwmod_class,
 202         .clkdm_name     = "l4_wkup_clkdm",
 203 };
 204
 205 /*
 206  * 'emif' class
 207  * instance(s): emif
 208  */
 209 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
 210         .rev_offs       = 0x0000,
 211 };
 212
 213 struct omap_hwmod_class am33xx_emif_hwmod_class = {
 214         .name           = "emif",
 215         .sysc           = &am33xx_emif_sysc,
 216 };
 217
 218 /*
 219  * 'aes0' class
 220  */
 221 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 222         .rev_offs       = 0x80,
 223         .sysc_offs      = 0x84,
 224         .syss_offs      = 0x88,
 225         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 226 };
 227
 228 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 229         .name           = "aes0",
 230         .sysc           = &am33xx_aes0_sysc,
 231 };
 232
 233 struct omap_hwmod am33xx_aes0_hwmod = {
 234         .name           = "aes",
 235         .class          = &am33xx_aes0_hwmod_class,
 236         .clkdm_name     = "l3_clkdm",
 237         .main_clk       = "aes0_fck",
 238         .prcm           = {
 239                 .omap4  = {
 240                         .modulemode     = MODULEMODE_SWCTRL,
 241                 },
 242         },
 243 };
 244
 245 /* sha0 HIB2 (the 'P' (public) device) */
 246 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 247         .rev_offs       = 0x100,
 248         .sysc_offs      = 0x110,
 249         .syss_offs      = 0x114,
 250         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 251 };
 252
 253 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 254         .name           = "sha0",
 255         .sysc           = &am33xx_sha0_sysc,
 256 };
 257
 258 struct omap_hwmod am33xx_sha0_hwmod = {
 259         .name           = "sham",
 260         .class          = &am33xx_sha0_hwmod_class,
 261         .clkdm_name     = "l3_clkdm",
 262         .main_clk       = "l3_gclk",
 263         .prcm           = {
 264                 .omap4  = {
 265                         .modulemode     = MODULEMODE_SWCTRL,
 266                 },
 267         },
 268 };
 269
 270 /* ocmcram */
 271 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 272         .name = "ocmcram",
 273 };
 274
 275 struct omap_hwmod am33xx_ocmcram_hwmod = {
 276         .name           = "ocmcram",
 277         .class          = &am33xx_ocmcram_hwmod_class,
 278         .clkdm_name     = "l3_clkdm",
 279         .flags          = HWMOD_INIT_NO_IDLE,
 280         .main_clk       = "l3_gclk",
 281         .prcm           = {
 282                 .omap4  = {
 283                         .modulemode     = MODULEMODE_SWCTRL,
 284                 },
 285         },
 286 };
 287
 288 /* 'smartreflex' class */
 289 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 290         .name           = "smartreflex",
 291 };
 292
 293 /* smartreflex0 */
 294 struct omap_hwmod am33xx_smartreflex0_hwmod = {
 295         .name           = "smartreflex0",
 296         .class          = &am33xx_smartreflex_hwmod_class,
 297         .clkdm_name     = "l4_wkup_clkdm",
 298         .main_clk       = "smartreflex0_fck",
 299         .prcm           = {
 300                 .omap4  = {
 301                         .modulemode     = MODULEMODE_SWCTRL,
 302                 },
 303         },
 304 };
 305
 306 /* smartreflex1 */
 307 struct omap_hwmod am33xx_smartreflex1_hwmod = {
 308         .name           = "smartreflex1",
 309         .class          = &am33xx_smartreflex_hwmod_class,
 310         .clkdm_name     = "l4_wkup_clkdm",
 311         .main_clk       = "smartreflex1_fck",
 312         .prcm           = {
 313                 .omap4  = {
 314                         .modulemode     = MODULEMODE_SWCTRL,
 315                 },
 316         },
 317 };
 318
 319 /*
 320  * 'control' module class
 321  */
 322 struct omap_hwmod_class am33xx_control_hwmod_class = {
 323         .name           = "control",
 324 };
 325
 326 /*
 327  * 'cpgmac' class
 328  * cpsw/cpgmac sub system
 329  */
 330 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
 331         .rev_offs       = 0x0,
 332         .sysc_offs      = 0x8,
 333         .syss_offs      = 0x4,
 334         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 335                            SYSS_HAS_RESET_STATUS),
 336         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 337                            MSTANDBY_NO),
 338         .sysc_fields    = &omap_hwmod_sysc_type3,
 339 };
 340
 341 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 342         .name           = "cpgmac0",
 343         .sysc           = &am33xx_cpgmac_sysc,
 344 };
 345
 346 struct omap_hwmod am33xx_cpgmac0_hwmod = {
 347         .name           = "cpgmac0",
 348         .class          = &am33xx_cpgmac0_hwmod_class,
 349         .clkdm_name     = "cpsw_125mhz_clkdm",
 350         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 351         .main_clk       = "cpsw_125mhz_gclk",
 352         .mpu_rt_idx     = 1,
 353         .prcm           = {
 354                 .omap4  = {
 355                         .modulemode     = MODULEMODE_SWCTRL,
 356                 },
 357         },
 358 };
 359
 360 /*
 361  * mdio class
 362  */
 363 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
 364         .name           = "davinci_mdio",
 365 };
 366
 367 struct omap_hwmod am33xx_mdio_hwmod = {
 368         .name           = "davinci_mdio",
 369         .class          = &am33xx_mdio_hwmod_class,
 370         .clkdm_name     = "cpsw_125mhz_clkdm",
 371         .main_clk       = "cpsw_125mhz_gclk",
 372 };
 373
 374 /*
 375  * dcan class
 376  */
 377 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 378         .name = "d_can",
 379 };
 380
 381 /* dcan0 */
 382 struct omap_hwmod am33xx_dcan0_hwmod = {
 383         .name           = "d_can0",
 384         .class          = &am33xx_dcan_hwmod_class,
 385         .clkdm_name     = "l4ls_clkdm",
 386         .main_clk       = "dcan0_fck",
 387         .prcm           = {
 388                 .omap4  = {
 389                         .modulemode     = MODULEMODE_SWCTRL,
 390                 },
 391         },
 392 };
 393
 394 /* dcan1 */
 395 struct omap_hwmod am33xx_dcan1_hwmod = {
 396         .name           = "d_can1",
 397         .class          = &am33xx_dcan_hwmod_class,
 398         .clkdm_name     = "l4ls_clkdm",
 399         .main_clk       = "dcan1_fck",
 400         .prcm           = {
 401                 .omap4  = {
 402                         .modulemode     = MODULEMODE_SWCTRL,
 403                 },
 404         },
 405 };
 406
 407 /* elm */
 408 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 409         .rev_offs       = 0x0000,
 410         .sysc_offs      = 0x0010,
 411         .syss_offs      = 0x0014,
 412         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 413                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 414                         SYSS_HAS_RESET_STATUS),
 415         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 416         .sysc_fields    = &omap_hwmod_sysc_type1,
 417 };
 418
 419 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 420         .name           = "elm",
 421         .sysc           = &am33xx_elm_sysc,
 422 };
 423
 424 struct omap_hwmod am33xx_elm_hwmod = {
 425         .name           = "elm",
 426         .class          = &am33xx_elm_hwmod_class,
 427         .clkdm_name     = "l4ls_clkdm",
 428         .main_clk       = "l4ls_gclk",
 429         .prcm           = {
 430                 .omap4  = {
 431                         .modulemode     = MODULEMODE_SWCTRL,
 432                 },
 433         },
 434 };
 435
 436 /* pwmss  */
 437 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 438         .rev_offs       = 0x0,
 439         .sysc_offs      = 0x4,
 440         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 441         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 442                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 443                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 444         .sysc_fields    = &omap_hwmod_sysc_type2,
 445 };
 446
 447 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 448         .name           = "epwmss",
 449         .sysc           = &am33xx_epwmss_sysc,
 450 };
 451
 452 /* epwmss0 */
 453 struct omap_hwmod am33xx_epwmss0_hwmod = {
 454         .name           = "epwmss0",
 455         .class          = &am33xx_epwmss_hwmod_class,
 456         .clkdm_name     = "l4ls_clkdm",
 457         .main_clk       = "l4ls_gclk",
 458         .prcm           = {
 459                 .omap4  = {
 460                         .modulemode     = MODULEMODE_SWCTRL,
 461                 },
 462         },
 463 };
 464
 465 /* epwmss1 */
 466 struct omap_hwmod am33xx_epwmss1_hwmod = {
 467         .name           = "epwmss1",
 468         .class          = &am33xx_epwmss_hwmod_class,
 469         .clkdm_name     = "l4ls_clkdm",
 470         .main_clk       = "l4ls_gclk",
 471         .prcm           = {
 472                 .omap4  = {
 473                         .modulemode     = MODULEMODE_SWCTRL,
 474                 },
 475         },
 476 };
 477
 478 /* epwmss2 */
 479 struct omap_hwmod am33xx_epwmss2_hwmod = {
 480         .name           = "epwmss2",
 481         .class          = &am33xx_epwmss_hwmod_class,
 482         .clkdm_name     = "l4ls_clkdm",
 483         .main_clk       = "l4ls_gclk",
 484         .prcm           = {
 485                 .omap4  = {
 486                         .modulemode     = MODULEMODE_SWCTRL,
 487                 },
 488         },
 489 };
 490
 491 /*
 492  * 'gpio' class: for gpio 0,1,2,3
 493  */
 494 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
 495         .rev_offs       = 0x0000,
 496         .sysc_offs      = 0x0010,
 497         .syss_offs      = 0x0114,
 498         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 499                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 500                           SYSS_HAS_RESET_STATUS),
 501         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 502                           SIDLE_SMART_WKUP),
 503         .sysc_fields    = &omap_hwmod_sysc_type1,
 504 };
 505
 506 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
 507         .name           = "gpio",
 508         .sysc           = &am33xx_gpio_sysc,
 509         .rev            = 2,
 510 };
 511
 512 struct omap_gpio_dev_attr gpio_dev_attr = {
 513         .bank_width     = 32,
 514         .dbck_flag      = true,
 515 };
 516
 517 /* gpio1 */
 518 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 519         { .role = "dbclk", .clk = "gpio1_dbclk" },
 520 };
 521
 522 struct omap_hwmod am33xx_gpio1_hwmod = {
 523         .name           = "gpio2",
 524         .class          = &am33xx_gpio_hwmod_class,
 525         .clkdm_name     = "l4ls_clkdm",
 526         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 527         .main_clk       = "l4ls_gclk",
 528         .prcm           = {
 529                 .omap4  = {
 530                         .modulemode     = MODULEMODE_SWCTRL,
 531                 },
 532         },
 533         .opt_clks       = gpio1_opt_clks,
 534         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 535         .dev_attr       = &gpio_dev_attr,
 536 };
 537
 538 /* gpio2 */
 539 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 540         { .role = "dbclk", .clk = "gpio2_dbclk" },
 541 };
 542
 543 struct omap_hwmod am33xx_gpio2_hwmod = {
 544         .name           = "gpio3",
 545         .class          = &am33xx_gpio_hwmod_class,
 546         .clkdm_name     = "l4ls_clkdm",
 547         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 548         .main_clk       = "l4ls_gclk",
 549         .prcm           = {
 550                 .omap4  = {
 551                         .modulemode     = MODULEMODE_SWCTRL,
 552                 },
 553         },
 554         .opt_clks       = gpio2_opt_clks,
 555         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 556         .dev_attr       = &gpio_dev_attr,
 557 };
 558
 559 /* gpio3 */
 560 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 561         { .role = "dbclk", .clk = "gpio3_dbclk" },
 562 };
 563
 564 struct omap_hwmod am33xx_gpio3_hwmod = {
 565         .name           = "gpio4",
 566         .class          = &am33xx_gpio_hwmod_class,
 567         .clkdm_name     = "l4ls_clkdm",
 568         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 569         .main_clk       = "l4ls_gclk",
 570         .prcm           = {
 571                 .omap4  = {
 572                         .modulemode     = MODULEMODE_SWCTRL,
 573                 },
 574         },
 575         .opt_clks       = gpio3_opt_clks,
 576         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 577         .dev_attr       = &gpio_dev_attr,
 578 };
 579
 580 /* gpmc */
 581 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 582         .rev_offs       = 0x0,
 583         .sysc_offs      = 0x10,
 584         .syss_offs      = 0x14,
 585         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 586                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 587         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 588         .sysc_fields    = &omap_hwmod_sysc_type1,
 589 };
 590
 591 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 592         .name           = "gpmc",
 593         .sysc           = &gpmc_sysc,
 594 };
 595
 596 struct omap_hwmod am33xx_gpmc_hwmod = {
 597         .name           = "gpmc",
 598         .class          = &am33xx_gpmc_hwmod_class,
 599         .clkdm_name     = "l3s_clkdm",
 600         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 601         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 602         .main_clk       = "l3s_gclk",
 603         .prcm           = {
 604                 .omap4  = {
 605                         .modulemode     = MODULEMODE_SWCTRL,
 606                 },
 607         },
 608 };
 609
 610 /* 'i2c' class */
 611 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
 612         .sysc_offs      = 0x0010,
 613         .syss_offs      = 0x0090,
 614         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 615                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 616                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 617         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 618                           SIDLE_SMART_WKUP),
 619         .sysc_fields    = &omap_hwmod_sysc_type1,
 620 };
 621
 622 static struct omap_hwmod_class i2c_class = {
 623         .name           = "i2c",
 624         .sysc           = &am33xx_i2c_sysc,
 625         .rev            = OMAP_I2C_IP_VERSION_2,
 626         .reset          = &omap_i2c_reset,
 627 };
 628
 629 static struct omap_i2c_dev_attr i2c_dev_attr = {
 630         .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 631 };
 632
 633 /* i2c1 */
 634 struct omap_hwmod am33xx_i2c1_hwmod = {
 635         .name           = "i2c1",
 636         .class          = &i2c_class,
 637         .clkdm_name     = "l4_wkup_clkdm",
 638         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 639         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
 640         .prcm           = {
 641                 .omap4  = {
 642                         .modulemode     = MODULEMODE_SWCTRL,
 643                 },
 644         },
 645         .dev_attr       = &i2c_dev_attr,
 646 };
 647
 648 /* i2c1 */
 649 struct omap_hwmod am33xx_i2c2_hwmod = {
 650         .name           = "i2c2",
 651         .class          = &i2c_class,
 652         .clkdm_name     = "l4ls_clkdm",
 653         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 654         .main_clk       = "dpll_per_m2_div4_ck",
 655         .prcm           = {
 656                 .omap4 = {
 657                         .modulemode     = MODULEMODE_SWCTRL,
 658                 },
 659         },
 660         .dev_attr       = &i2c_dev_attr,
 661 };
 662
 663 /* i2c3 */
 664 struct omap_hwmod am33xx_i2c3_hwmod = {
 665         .name           = "i2c3",
 666         .class          = &i2c_class,
 667         .clkdm_name     = "l4ls_clkdm",
 668         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 669         .main_clk       = "dpll_per_m2_div4_ck",
 670         .prcm           = {
 671                 .omap4  = {
 672                         .modulemode     = MODULEMODE_SWCTRL,
 673                 },
 674         },
 675         .dev_attr       = &i2c_dev_attr,
 676 };
 677
 678 /*
 679  * 'mailbox' class
 680  * mailbox module allowing communication between the on-chip processors using a
 681  * queued mailbox-interrupt mechanism.
 682  */
 683 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
 684         .rev_offs       = 0x0000,
 685         .sysc_offs      = 0x0010,
 686         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 687                           SYSC_HAS_SOFTRESET),
 688         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 689         .sysc_fields    = &omap_hwmod_sysc_type2,
 690 };
 691
 692 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
 693         .name   = "mailbox",
 694         .sysc   = &am33xx_mailbox_sysc,
 695 };
 696
 697 struct omap_hwmod am33xx_mailbox_hwmod = {
 698         .name           = "mailbox",
 699         .class          = &am33xx_mailbox_hwmod_class,
 700         .clkdm_name     = "l4ls_clkdm",
 701         .main_clk       = "l4ls_gclk",
 702         .prcm = {
 703                 .omap4 = {
 704                         .modulemode     = MODULEMODE_SWCTRL,
 705                 },
 706         },
 707 };
 708
 709 /*
 710  * 'mcasp' class
 711  */
 712 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
 713         .rev_offs       = 0x0,
 714         .sysc_offs      = 0x4,
 715         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 716         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 717         .sysc_fields    = &omap_hwmod_sysc_type3,
 718 };
 719
 720 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 721         .name           = "mcasp",
 722         .sysc           = &am33xx_mcasp_sysc,
 723 };
 724
 725 /* mcasp0 */
 726 struct omap_hwmod am33xx_mcasp0_hwmod = {
 727         .name           = "mcasp0",
 728         .class          = &am33xx_mcasp_hwmod_class,
 729         .clkdm_name     = "l3s_clkdm",
 730         .main_clk       = "mcasp0_fck",
 731         .prcm           = {
 732                 .omap4  = {
 733                         .modulemode     = MODULEMODE_SWCTRL,
 734                 },
 735         },
 736 };
 737
 738 /* mcasp1 */
 739 struct omap_hwmod am33xx_mcasp1_hwmod = {
 740         .name           = "mcasp1",
 741         .class          = &am33xx_mcasp_hwmod_class,
 742         .clkdm_name     = "l3s_clkdm",
 743         .main_clk       = "mcasp1_fck",
 744         .prcm           = {
 745                 .omap4  = {
 746                         .modulemode     = MODULEMODE_SWCTRL,
 747                 },
 748         },
 749 };
 750
 751 /* 'mmc' class */
 752 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
 753         .rev_offs       = 0x1fc,
 754         .sysc_offs      = 0x10,
 755         .syss_offs      = 0x14,
 756         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 757                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 758                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 759         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 760         .sysc_fields    = &omap_hwmod_sysc_type1,
 761 };
 762
 763 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
 764         .name           = "mmc",
 765         .sysc           = &am33xx_mmc_sysc,
 766 };
 767
 768 /* mmc0 */
 769 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
 770         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 771 };
 772
 773 struct omap_hwmod am33xx_mmc0_hwmod = {
 774         .name           = "mmc1",
 775         .class          = &am33xx_mmc_hwmod_class,
 776         .clkdm_name     = "l4ls_clkdm",
 777         .main_clk       = "mmc_clk",
 778         .prcm           = {
 779                 .omap4  = {
 780                         .modulemode     = MODULEMODE_SWCTRL,
 781                 },
 782         },
 783         .dev_attr       = &am33xx_mmc0_dev_attr,
 784 };
 785
 786 /* mmc1 */
 787 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
 788         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 789 };
 790
 791 struct omap_hwmod am33xx_mmc1_hwmod = {
 792         .name           = "mmc2",
 793         .class          = &am33xx_mmc_hwmod_class,
 794         .clkdm_name     = "l4ls_clkdm",
 795         .main_clk       = "mmc_clk",
 796         .prcm           = {
 797                 .omap4  = {
 798                         .modulemode     = MODULEMODE_SWCTRL,
 799                 },
 800         },
 801         .dev_attr       = &am33xx_mmc1_dev_attr,
 802 };
 803
 804 /* mmc2 */
 805 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
 806         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 807 };
 808 struct omap_hwmod am33xx_mmc2_hwmod = {
 809         .name           = "mmc3",
 810         .class          = &am33xx_mmc_hwmod_class,
 811         .clkdm_name     = "l3s_clkdm",
 812         .main_clk       = "mmc_clk",
 813         .prcm           = {
 814                 .omap4  = {
 815                         .modulemode     = MODULEMODE_SWCTRL,
 816                 },
 817         },
 818         .dev_attr       = &am33xx_mmc2_dev_attr,
 819 };
 820
 821 /*
 822  * 'rtc' class
 823  * rtc subsystem
 824  */
 825 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
 826         .rev_offs       = 0x0074,
 827         .sysc_offs      = 0x0078,
 828         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 829         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
 830                           SIDLE_SMART | SIDLE_SMART_WKUP),
 831         .sysc_fields    = &omap_hwmod_sysc_type3,
 832 };
 833
 834 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 835         .name           = "rtc",
 836         .sysc           = &am33xx_rtc_sysc,
 837         .unlock         = &omap_hwmod_rtc_unlock,
 838         .lock           = &omap_hwmod_rtc_lock,
 839 };
 840
 841 struct omap_hwmod am33xx_rtc_hwmod = {
 842         .name           = "rtc",
 843         .class          = &am33xx_rtc_hwmod_class,
 844         .clkdm_name     = "l4_rtc_clkdm",
 845         .main_clk       = "clk_32768_ck",
 846         .prcm           = {
 847                 .omap4  = {
 848                         .modulemode     = MODULEMODE_SWCTRL,
 849                 },
 850         },
 851 };
 852
 853 /* 'spi' class */
 854 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
 855         .rev_offs       = 0x0000,
 856         .sysc_offs      = 0x0110,
 857         .syss_offs      = 0x0114,
 858         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 859                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 860                           SYSS_HAS_RESET_STATUS),
 861         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 862         .sysc_fields    = &omap_hwmod_sysc_type1,
 863 };
 864
 865 struct omap_hwmod_class am33xx_spi_hwmod_class = {
 866         .name           = "mcspi",
 867         .sysc           = &am33xx_mcspi_sysc,
 868         .rev            = OMAP4_MCSPI_REV,
 869 };
 870
 871 /* spi0 */
 872 struct omap2_mcspi_dev_attr mcspi_attrib = {
 873         .num_chipselect = 2,
 874 };
 875 struct omap_hwmod am33xx_spi0_hwmod = {
 876         .name           = "spi0",
 877         .class          = &am33xx_spi_hwmod_class,
 878         .clkdm_name     = "l4ls_clkdm",
 879         .main_clk       = "dpll_per_m2_div4_ck",
 880         .prcm           = {
 881                 .omap4  = {
 882                         .modulemode     = MODULEMODE_SWCTRL,
 883                 },
 884         },
 885         .dev_attr       = &mcspi_attrib,
 886 };
 887
 888 /* spi1 */
 889 struct omap_hwmod am33xx_spi1_hwmod = {
 890         .name           = "spi1",
 891         .class          = &am33xx_spi_hwmod_class,
 892         .clkdm_name     = "l4ls_clkdm",
 893         .main_clk       = "dpll_per_m2_div4_ck",
 894         .prcm           = {
 895                 .omap4  = {
 896                         .modulemode     = MODULEMODE_SWCTRL,
 897                 },
 898         },
 899         .dev_attr       = &mcspi_attrib,
 900 };
 901
 902 /*
 903  * 'spinlock' class
 904  * spinlock provides hardware assistance for synchronizing the
 905  * processes running on multiple processors
 906  */
 907
 908 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
 909         .rev_offs       = 0x0000,
 910         .sysc_offs      = 0x0010,
 911         .syss_offs      = 0x0014,
 912         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 913                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 914                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 915         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 916         .sysc_fields    = &omap_hwmod_sysc_type1,
 917 };
 918
 919 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
 920         .name           = "spinlock",
 921         .sysc           = &am33xx_spinlock_sysc,
 922 };
 923
 924 struct omap_hwmod am33xx_spinlock_hwmod = {
 925         .name           = "spinlock",
 926         .class          = &am33xx_spinlock_hwmod_class,
 927         .clkdm_name     = "l4ls_clkdm",
 928         .main_clk       = "l4ls_gclk",
 929         .prcm           = {
 930                 .omap4  = {
 931                         .modulemode     = MODULEMODE_SWCTRL,
 932                 },
 933         },
 934 };
 935
 936 /* 'timer 2-7' class */
 937 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
 938         .rev_offs       = 0x0000,
 939         .sysc_offs      = 0x0010,
 940         .syss_offs      = 0x0014,
 941         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 942         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 943                           SIDLE_SMART_WKUP),
 944         .sysc_fields    = &omap_hwmod_sysc_type2,
 945 };
 946
 947 struct omap_hwmod_class am33xx_timer_hwmod_class = {
 948         .name           = "timer",
 949         .sysc           = &am33xx_timer_sysc,
 950 };
 951
 952 /* timer1 1ms */
 953 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
 954         .rev_offs       = 0x0000,
 955         .sysc_offs      = 0x0010,
 956         .syss_offs      = 0x0014,
 957         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 958                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 959                         SYSS_HAS_RESET_STATUS),
 960         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 961         .sysc_fields    = &omap_hwmod_sysc_type1,
 962 };
 963
 964 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
 965         .name           = "timer",
 966         .sysc           = &am33xx_timer1ms_sysc,
 967 };
 968
 969 struct omap_hwmod am33xx_timer1_hwmod = {
 970         .name           = "timer1",
 971         .class          = &am33xx_timer1ms_hwmod_class,
 972         .clkdm_name     = "l4_wkup_clkdm",
 973         .main_clk       = "timer1_fck",
 974         .prcm           = {
 975                 .omap4  = {
 976                         .modulemode     = MODULEMODE_SWCTRL,
 977                 },
 978         },
 979 };
 980
 981 struct omap_hwmod am33xx_timer2_hwmod = {
 982         .name           = "timer2",
 983         .class          = &am33xx_timer_hwmod_class,
 984         .clkdm_name     = "l4ls_clkdm",
 985         .main_clk       = "timer2_fck",
 986         .prcm           = {
 987                 .omap4  = {
 988                         .modulemode     = MODULEMODE_SWCTRL,
 989                 },
 990         },
 991 };
 992
 993 struct omap_hwmod am33xx_timer3_hwmod = {
 994         .name           = "timer3",
 995         .class          = &am33xx_timer_hwmod_class,
 996         .clkdm_name     = "l4ls_clkdm",
 997         .main_clk       = "timer3_fck",
 998         .prcm           = {
 999                 .omap4  = {
1000                         .modulemode     = MODULEMODE_SWCTRL,
1001                 },
1002         },
1003 };
1004
1005 struct omap_hwmod am33xx_timer4_hwmod = {
1006         .name           = "timer4",
1007         .class          = &am33xx_timer_hwmod_class,
1008         .clkdm_name     = "l4ls_clkdm",
1009         .main_clk       = "timer4_fck",
1010         .prcm           = {
1011                 .omap4  = {
1012                         .modulemode     = MODULEMODE_SWCTRL,
1013                 },
1014         },
1015 };
1016
1017 struct omap_hwmod am33xx_timer5_hwmod = {
1018         .name           = "timer5",
1019         .class          = &am33xx_timer_hwmod_class,
1020         .clkdm_name     = "l4ls_clkdm",
1021         .main_clk       = "timer5_fck",
1022         .prcm           = {
1023                 .omap4  = {
1024                         .modulemode     = MODULEMODE_SWCTRL,
1025                 },
1026         },
1027 };
1028
1029 struct omap_hwmod am33xx_timer6_hwmod = {
1030         .name           = "timer6",
1031         .class          = &am33xx_timer_hwmod_class,
1032         .clkdm_name     = "l4ls_clkdm",
1033         .main_clk       = "timer6_fck",
1034         .prcm           = {
1035                 .omap4  = {
1036                         .modulemode     = MODULEMODE_SWCTRL,
1037                 },
1038         },
1039 };
1040
1041 struct omap_hwmod am33xx_timer7_hwmod = {
1042         .name           = "timer7",
1043         .class          = &am33xx_timer_hwmod_class,
1044         .clkdm_name     = "l4ls_clkdm",
1045         .main_clk       = "timer7_fck",
1046         .prcm           = {
1047                 .omap4  = {
1048                         .modulemode     = MODULEMODE_SWCTRL,
1049                 },
1050         },
1051 };
1052
1053 /* tpcc */
1054 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1055         .name           = "tpcc",
1056 };
1057
1058 struct omap_hwmod am33xx_tpcc_hwmod = {
1059         .name           = "tpcc",
1060         .class          = &am33xx_tpcc_hwmod_class,
1061         .clkdm_name     = "l3_clkdm",
1062         .main_clk       = "l3_gclk",
1063         .prcm           = {
1064                 .omap4  = {
1065                         .modulemode     = MODULEMODE_SWCTRL,
1066                 },
1067         },
1068 };
1069
1070 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1071         .rev_offs       = 0x0,
1072         .sysc_offs      = 0x10,
1073         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1074                           SYSC_HAS_MIDLEMODE),
1075         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1076         .sysc_fields    = &omap_hwmod_sysc_type2,
1077 };
1078
1079 /* 'tptc' class */
1080 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1081         .name           = "tptc",
1082         .sysc           = &am33xx_tptc_sysc,
1083 };
1084
1085 /* tptc0 */
1086 struct omap_hwmod am33xx_tptc0_hwmod = {
1087         .name           = "tptc0",
1088         .class          = &am33xx_tptc_hwmod_class,
1089         .clkdm_name     = "l3_clkdm",
1090         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1091         .main_clk       = "l3_gclk",
1092         .prcm           = {
1093                 .omap4  = {
1094                         .modulemode     = MODULEMODE_SWCTRL,
1095                 },
1096         },
1097 };
1098
1099 /* tptc1 */
1100 struct omap_hwmod am33xx_tptc1_hwmod = {
1101         .name           = "tptc1",
1102         .class          = &am33xx_tptc_hwmod_class,
1103         .clkdm_name     = "l3_clkdm",
1104         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1105         .main_clk       = "l3_gclk",
1106         .prcm           = {
1107                 .omap4  = {
1108                         .modulemode     = MODULEMODE_SWCTRL,
1109                 },
1110         },
1111 };
1112
1113 /* tptc2 */
1114 struct omap_hwmod am33xx_tptc2_hwmod = {
1115         .name           = "tptc2",
1116         .class          = &am33xx_tptc_hwmod_class,
1117         .clkdm_name     = "l3_clkdm",
1118         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1119         .main_clk       = "l3_gclk",
1120         .prcm           = {
1121                 .omap4  = {
1122                         .modulemode     = MODULEMODE_SWCTRL,
1123                 },
1124         },
1125 };
1126
1127 /* 'uart' class */
1128 static struct omap_hwmod_class_sysconfig uart_sysc = {
1129         .rev_offs       = 0x50,
1130         .sysc_offs      = 0x54,
1131         .syss_offs      = 0x58,
1132         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1133                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1134         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1135                           SIDLE_SMART_WKUP),
1136         .sysc_fields    = &omap_hwmod_sysc_type1,
1137 };
1138
1139 static struct omap_hwmod_class uart_class = {
1140         .name           = "uart",
1141         .sysc           = &uart_sysc,
1142 };
1143
1144 struct omap_hwmod am33xx_uart1_hwmod = {
1145         .name           = "uart1",
1146         .class          = &uart_class,
1147         .clkdm_name     = "l4_wkup_clkdm",
1148         .flags          = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1149         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1150         .prcm           = {
1151                 .omap4  = {
1152                         .modulemode     = MODULEMODE_SWCTRL,
1153                 },
1154         },
1155 };
1156
1157 struct omap_hwmod am33xx_uart2_hwmod = {
1158         .name           = "uart2",
1159         .class          = &uart_class,
1160         .clkdm_name     = "l4ls_clkdm",
1161         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1162         .main_clk       = "dpll_per_m2_div4_ck",
1163         .prcm           = {
1164                 .omap4  = {
1165                         .modulemode     = MODULEMODE_SWCTRL,
1166                 },
1167         },
1168 };
1169
1170 /* uart3 */
1171 struct omap_hwmod am33xx_uart3_hwmod = {
1172         .name           = "uart3",
1173         .class          = &uart_class,
1174         .clkdm_name     = "l4ls_clkdm",
1175         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1176         .main_clk       = "dpll_per_m2_div4_ck",
1177         .prcm           = {
1178                 .omap4  = {
1179                         .modulemode     = MODULEMODE_SWCTRL,
1180                 },
1181         },
1182 };
1183
1184 struct omap_hwmod am33xx_uart4_hwmod = {
1185         .name           = "uart4",
1186         .class          = &uart_class,
1187         .clkdm_name     = "l4ls_clkdm",
1188         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1189         .main_clk       = "dpll_per_m2_div4_ck",
1190         .prcm           = {
1191                 .omap4  = {
1192                         .modulemode     = MODULEMODE_SWCTRL,
1193                 },
1194         },
1195 };
1196
1197 struct omap_hwmod am33xx_uart5_hwmod = {
1198         .name           = "uart5",
1199         .class          = &uart_class,
1200         .clkdm_name     = "l4ls_clkdm",
1201         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1202         .main_clk       = "dpll_per_m2_div4_ck",
1203         .prcm           = {
1204                 .omap4  = {
1205                         .modulemode     = MODULEMODE_SWCTRL,
1206                 },
1207         },
1208 };
1209
1210 struct omap_hwmod am33xx_uart6_hwmod = {
1211         .name           = "uart6",
1212         .class          = &uart_class,
1213         .clkdm_name     = "l4ls_clkdm",
1214         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1215         .main_clk       = "dpll_per_m2_div4_ck",
1216         .prcm           = {
1217                 .omap4  = {
1218                         .modulemode     = MODULEMODE_SWCTRL,
1219                 },
1220         },
1221 };
1222
1223 /* 'wd_timer' class */
1224 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1225         .rev_offs       = 0x0,
1226         .sysc_offs      = 0x10,
1227         .syss_offs      = 0x14,
1228         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1229                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1230         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1231                         SIDLE_SMART_WKUP),
1232         .sysc_fields    = &omap_hwmod_sysc_type1,
1233 };
1234
1235 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1236         .name           = "wd_timer",
1237         .sysc           = &wdt_sysc,
1238         .pre_shutdown   = &omap2_wd_timer_disable,
1239 };
1240
1241 /*
1242  * XXX: device.c file uses hardcoded name for watchdog timer
1243  * driver "wd_timer2, so we are also using same name as of now...
1244  */
1245 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1246         .name           = "wd_timer2",
1247         .class          = &am33xx_wd_timer_hwmod_class,
1248         .clkdm_name     = "l4_wkup_clkdm",
1249         .flags          = HWMOD_SWSUP_SIDLE,
1250         .main_clk       = "wdt1_fck",
1251         .prcm           = {
1252                 .omap4  = {
1253                         .modulemode     = MODULEMODE_SWCTRL,
1254                 },
1255         },
1256 };
1257
1258 static void omap_hwmod_am33xx_clkctrl(void)
1259 {
1260         CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1261         CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1262         CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1263         CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1264         CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1265         CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1266         CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1267         CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1268         CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1269         CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1270         CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1271         CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1272         CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1273         CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1274         CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1275         CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1276         CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1277         CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1278         CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1279         CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1280         CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1281         CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1282         CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1283         CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1284         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1285         CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1286         CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1287         CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1288         CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1289         CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1290         CLKCTRL(am33xx_smartreflex0_hwmod,
1291                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1292         CLKCTRL(am33xx_smartreflex1_hwmod,
1293                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1294         CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1295         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1296         CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1297         CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1298         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1299         CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1300         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1301         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1302         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1303         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1304         CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1305         CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1306         CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1307         CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1308         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1309         CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1310         CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1311         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1312         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1313         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1314         CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1315         CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1316 }
1317
1318 static void omap_hwmod_am33xx_rst(void)
1319 {
1320         RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1321         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1322         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1323 }
1324
1325 void omap_hwmod_am33xx_reg(void)
1326 {
1327         omap_hwmod_am33xx_clkctrl();
1328         omap_hwmod_am33xx_rst();
1329 }
1330
1331 static void omap_hwmod_am43xx_clkctrl(void)
1332 {
1333         CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1334         CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1335         CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1336         CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1337         CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1338         CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1339         CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1340         CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1341         CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1342         CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1343         CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1344         CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1345         CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1346         CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1347         CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1348         CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1349         CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1350         CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1351         CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1352         CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1353         CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1354         CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1355         CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1356         CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1357         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1358         CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1359         CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1360         CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1361         CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1362         CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1363         CLKCTRL(am33xx_smartreflex0_hwmod,
1364                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1365         CLKCTRL(am33xx_smartreflex1_hwmod,
1366                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1367         CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1368         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1369         CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1370         CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1371         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1372         CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1373         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1374         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1375         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1376         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1377         CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1378         CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1379         CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1380         CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1381         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1382         CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1383         CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1384         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1385         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1386         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1387         CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1388         CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1389 }
1390
1391 static void omap_hwmod_am43xx_rst(void)
1392 {
1393         RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1394         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1395         RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1396         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1397 }
1398
1399 void omap_hwmod_am43xx_reg(void)
1400 {
1401         omap_hwmod_am43xx_clkctrl();
1402         omap_hwmod_am43xx_rst();
1403 }