2 * linux/arch/arm/mach-sa1100/irq.c
4 * Copyright (C) 1999-2001 Nicolas Pitre
6 * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/ioport.h>
19 #include <linux/syscore_ops.h>
21 #include <mach/hardware.h>
22 #include <mach/irqs.h>
23 #include <asm/mach/irq.h>
24 #include <asm/exception.h>
30 * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
31 * this is for internal IRQs i.e. from IRQ LCD to RTCAlrm.
33 static void sa1100_mask_irq(struct irq_data *d)
35 ICMR &= ~BIT(d->hwirq);
38 static void sa1100_unmask_irq(struct irq_data *d)
40 ICMR |= BIT(d->hwirq);
44 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
46 static int sa1100_set_wake(struct irq_data *d, unsigned int on)
48 if (BIT(d->hwirq) == IC_RTCAlrm) {
58 static struct irq_chip sa1100_normal_chip = {
60 .irq_ack = sa1100_mask_irq,
61 .irq_mask = sa1100_mask_irq,
62 .irq_unmask = sa1100_unmask_irq,
63 .irq_set_wake = sa1100_set_wake,
66 static int sa1100_normal_irqdomain_map(struct irq_domain *d,
67 unsigned int irq, irq_hw_number_t hwirq)
69 irq_set_chip_and_handler(irq, &sa1100_normal_chip,
71 set_irq_flags(irq, IRQF_VALID);
76 static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
77 .map = sa1100_normal_irqdomain_map,
78 .xlate = irq_domain_xlate_onetwocell,
81 static struct irq_domain *sa1100_normal_irqdomain;
84 * SA1100 GPIO edge detection for IRQs:
85 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
86 * Use this instead of directly setting GRER/GFER.
88 static int GPIO_IRQ_rising_edge;
89 static int GPIO_IRQ_falling_edge;
90 static int GPIO_IRQ_mask = (1 << 11) - 1;
92 static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
98 if (type == IRQ_TYPE_PROBE) {
99 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
101 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
104 if (type & IRQ_TYPE_EDGE_RISING) {
105 GPIO_IRQ_rising_edge |= mask;
107 GPIO_IRQ_rising_edge &= ~mask;
108 if (type & IRQ_TYPE_EDGE_FALLING) {
109 GPIO_IRQ_falling_edge |= mask;
111 GPIO_IRQ_falling_edge &= ~mask;
113 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
114 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
120 * GPIO IRQs must be acknowledged.
122 static void sa1100_gpio_ack(struct irq_data *d)
124 GEDR = BIT(d->hwirq);
127 static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
130 PWER |= BIT(d->hwirq);
132 PWER &= ~BIT(d->hwirq);
137 * This is for IRQs from 0 to 10.
139 static struct irq_chip sa1100_low_gpio_chip = {
141 .irq_ack = sa1100_gpio_ack,
142 .irq_mask = sa1100_mask_irq,
143 .irq_unmask = sa1100_unmask_irq,
144 .irq_set_type = sa1100_gpio_type,
145 .irq_set_wake = sa1100_gpio_wake,
148 static int sa1100_low_gpio_irqdomain_map(struct irq_domain *d,
149 unsigned int irq, irq_hw_number_t hwirq)
151 irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
153 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
158 static struct irq_domain_ops sa1100_low_gpio_irqdomain_ops = {
159 .map = sa1100_low_gpio_irqdomain_map,
160 .xlate = irq_domain_xlate_onetwocell,
163 static struct irq_domain *sa1100_low_gpio_irqdomain;
166 * IRQ11 (GPIO11 through 27) handler. We enter here with the
167 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
168 * and call the handler.
171 sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
175 mask = GEDR & 0xfffff800;
178 * clear down all currently active IRQ sources.
179 * We will be processing them all.
187 generic_handle_irq(irq);
192 mask = GEDR & 0xfffff800;
197 * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
198 * In addition, the IRQs are all collected up into one bit in the
199 * interrupt controller registers.
201 static void sa1100_high_gpio_mask(struct irq_data *d)
203 unsigned int mask = BIT(d->hwirq);
205 GPIO_IRQ_mask &= ~mask;
211 static void sa1100_high_gpio_unmask(struct irq_data *d)
213 unsigned int mask = BIT(d->hwirq);
215 GPIO_IRQ_mask |= mask;
217 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
218 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
221 static struct irq_chip sa1100_high_gpio_chip = {
223 .irq_ack = sa1100_gpio_ack,
224 .irq_mask = sa1100_high_gpio_mask,
225 .irq_unmask = sa1100_high_gpio_unmask,
226 .irq_set_type = sa1100_gpio_type,
227 .irq_set_wake = sa1100_gpio_wake,
230 static int sa1100_high_gpio_irqdomain_map(struct irq_domain *d,
231 unsigned int irq, irq_hw_number_t hwirq)
233 irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
235 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
240 static struct irq_domain_ops sa1100_high_gpio_irqdomain_ops = {
241 .map = sa1100_high_gpio_irqdomain_map,
242 .xlate = irq_domain_xlate_onetwocell,
245 static struct irq_domain *sa1100_high_gpio_irqdomain;
247 static struct resource irq_resource =
248 DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
250 static struct sa1100irq_state {
257 static int sa1100irq_suspend(void)
259 struct sa1100irq_state *st = &sa1100irq_state;
267 * Disable all GPIO-based interrupts.
269 ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
270 IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
274 * Set the appropriate edges for wakeup.
276 GRER = PWER & GPIO_IRQ_rising_edge;
277 GFER = PWER & GPIO_IRQ_falling_edge;
280 * Clear any pending GPIO interrupts.
287 static void sa1100irq_resume(void)
289 struct sa1100irq_state *st = &sa1100irq_state;
295 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
296 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
302 static struct syscore_ops sa1100irq_syscore_ops = {
303 .suspend = sa1100irq_suspend,
304 .resume = sa1100irq_resume,
307 static int __init sa1100irq_init_devicefs(void)
309 register_syscore_ops(&sa1100irq_syscore_ops);
313 device_initcall(sa1100irq_init_devicefs);
315 static asmlinkage void __exception_irq_entry
316 sa1100_handle_irq(struct pt_regs *regs)
318 uint32_t icip, icmr, mask;
328 handle_IRQ(ffs(mask) - 1 + IRQ_GPIO0, regs);
332 void __init sa1100_init_irq(void)
334 request_resource(&iomem_resource, &irq_resource);
336 /* disable all IRQs */
339 /* all IRQs are IRQ, not FIQ */
342 /* clear all GPIO edge detects */
348 * Whatever the doc says, this has to be set for the wait-on-irq
349 * instruction to work... on a SA1100 rev 9 at least.
353 sa1100_low_gpio_irqdomain = irq_domain_add_legacy(NULL,
355 &sa1100_low_gpio_irqdomain_ops, NULL);
357 sa1100_normal_irqdomain = irq_domain_add_legacy(NULL,
358 21, IRQ_GPIO11_27, 11,
359 &sa1100_normal_irqdomain_ops, NULL);
361 sa1100_high_gpio_irqdomain = irq_domain_add_legacy(NULL,
363 &sa1100_high_gpio_irqdomain_ops, NULL);
366 * Install handler for GPIO 11-27 edge detect interrupts
368 irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
370 set_handle_irq(sa1100_handle_irq);