arch/arm/mach-shmobile/setup-r8a7740.c

   1 /*
   2  * R8A7740 processor support
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/irqchip.h>
  26 #include <linux/irqchip/arm-gic.h>
  27 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/platform_data/sh_ipmmu.h>
  34
  35 #include <asm/mach-types.h>
  36 #include <asm/mach/map.h>
  37 #include <asm/mach/arch.h>
  38 #include <asm/mach/time.h>
  39 #include <asm/hardware/cache-l2x0.h>
  40
  41 #include "common.h"
  42 #include "dma-register.h"
  43 #include "irqs.h"
  44 #include "pm-rmobile.h"
  45 #include "r8a7740.h"
  46
  47 static struct map_desc r8a7740_io_desc[] __initdata = {
  48          /*
  49           * for CPGA/INTC/PFC
  50           * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
  51           */
  52         {
  53                 .virtual        = 0xe6000000,
  54                 .pfn            = __phys_to_pfn(0xe6000000),
  55                 .length         = 160 << 20,
  56                 .type           = MT_DEVICE_NONSHARED
  57         },
  58 #ifdef CONFIG_CACHE_L2X0
  59         /*
  60          * for l2x0_init()
  61          * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
  62          */
  63         {
  64                 .virtual        = 0xf0002000,
  65                 .pfn            = __phys_to_pfn(0xf0100000),
  66                 .length         = PAGE_SIZE,
  67                 .type           = MT_DEVICE_NONSHARED
  68         },
  69 #endif
  70 };
  71
  72 void __init r8a7740_map_io(void)
  73 {
  74         debug_ll_io_init();
  75         iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
  76 }
  77
  78 /* PFC */
  79 static const struct resource pfc_resources[] = {
  80         DEFINE_RES_MEM(0xe6050000, 0x8000),
  81         DEFINE_RES_MEM(0xe605800c, 0x0020),
  82 };
  83
  84 void __init r8a7740_pinmux_init(void)
  85 {
  86         platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
  87                                         ARRAY_SIZE(pfc_resources));
  88 }
  89
  90 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
  91         .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
  92 };
  93
  94 static struct resource irqpin0_resources[] = {
  95         DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
  96         DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
  97         DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
  98         DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
  99         DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
 100         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
 101         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
 102         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
 103         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
 104         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
 105         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
 106         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
 107         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
 108 };
 109
 110 static struct platform_device irqpin0_device = {
 111         .name           = "renesas_intc_irqpin",
 112         .id             = 0,
 113         .resource       = irqpin0_resources,
 114         .num_resources  = ARRAY_SIZE(irqpin0_resources),
 115         .dev            = {
 116                 .platform_data  = &irqpin0_platform_data,
 117         },
 118 };
 119
 120 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
 121         .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
 122 };
 123
 124 static struct resource irqpin1_resources[] = {
 125         DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
 126         DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
 127         DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
 128         DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
 129         DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
 130         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
 131         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
 132         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
 133         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
 134         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
 135         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
 136         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
 137         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
 138 };
 139
 140 static struct platform_device irqpin1_device = {
 141         .name           = "renesas_intc_irqpin",
 142         .id             = 1,
 143         .resource       = irqpin1_resources,
 144         .num_resources  = ARRAY_SIZE(irqpin1_resources),
 145         .dev            = {
 146                 .platform_data  = &irqpin1_platform_data,
 147         },
 148 };
 149
 150 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
 151         .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
 152 };
 153
 154 static struct resource irqpin2_resources[] = {
 155         DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
 156         DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
 157         DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
 158         DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
 159         DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
 160         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
 161         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
 162         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
 163         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
 164         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
 165         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
 166         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
 167         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
 168 };
 169
 170 static struct platform_device irqpin2_device = {
 171         .name           = "renesas_intc_irqpin",
 172         .id             = 2,
 173         .resource       = irqpin2_resources,
 174         .num_resources  = ARRAY_SIZE(irqpin2_resources),
 175         .dev            = {
 176                 .platform_data  = &irqpin2_platform_data,
 177         },
 178 };
 179
 180 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
 181         .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
 182 };
 183
 184 static struct resource irqpin3_resources[] = {
 185         DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
 186         DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
 187         DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
 188         DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
 189         DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
 190         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
 191         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
 192         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
 193         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
 194         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
 195         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
 196         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
 197         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
 198 };
 199
 200 static struct platform_device irqpin3_device = {
 201         .name           = "renesas_intc_irqpin",
 202         .id             = 3,
 203         .resource       = irqpin3_resources,
 204         .num_resources  = ARRAY_SIZE(irqpin3_resources),
 205         .dev            = {
 206                 .platform_data  = &irqpin3_platform_data,
 207         },
 208 };
 209
 210 /* SCIF */
 211 #define R8A7740_SCIF(scif_type, index, baseaddr, irq)           \
 212 static struct plat_sci_port scif##index##_platform_data = {     \
 213         .type           = scif_type,                            \
 214         .flags          = UPF_BOOT_AUTOCONF,                    \
 215         .scscr          = SCSCR_RE | SCSCR_TE,                  \
 216 };                                                              \
 217                                                                 \
 218 static struct resource scif##index##_resources[] = {            \
 219         DEFINE_RES_MEM(baseaddr, 0x100),                        \
 220         DEFINE_RES_IRQ(irq),                                    \
 221 };                                                              \
 222                                                                 \
 223 static struct platform_device scif##index##_device = {          \
 224         .name           = "sh-sci",                             \
 225         .id             = index,                                \
 226         .resource       = scif##index##_resources,              \
 227         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 228         .dev            = {                                     \
 229                 .platform_data  = &scif##index##_platform_data, \
 230         },                                                      \
 231 }
 232
 233 R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
 234 R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
 235 R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
 236 R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
 237 R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
 238 R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
 239 R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
 240 R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
 241 R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
 242
 243 /* CMT */
 244 static struct sh_timer_config cmt1_platform_data = {
 245         .channels_mask = 0x3f,
 246 };
 247
 248 static struct resource cmt1_resources[] = {
 249         DEFINE_RES_MEM(0xe6138000, 0x170),
 250         DEFINE_RES_IRQ(gic_spi(58)),
 251 };
 252
 253 static struct platform_device cmt1_device = {
 254         .name           = "sh-cmt-48",
 255         .id             = 1,
 256         .dev = {
 257                 .platform_data  = &cmt1_platform_data,
 258         },
 259         .resource       = cmt1_resources,
 260         .num_resources  = ARRAY_SIZE(cmt1_resources),
 261 };
 262
 263 /* TMU */
 264 static struct sh_timer_config tmu0_platform_data = {
 265         .channels_mask = 7,
 266 };
 267
 268 static struct resource tmu0_resources[] = {
 269         DEFINE_RES_MEM(0xfff80000, 0x2c),
 270         DEFINE_RES_IRQ(gic_spi(198)),
 271         DEFINE_RES_IRQ(gic_spi(199)),
 272         DEFINE_RES_IRQ(gic_spi(200)),
 273 };
 274
 275 static struct platform_device tmu0_device = {
 276         .name           = "sh-tmu",
 277         .id             = 0,
 278         .dev = {
 279                 .platform_data  = &tmu0_platform_data,
 280         },
 281         .resource       = tmu0_resources,
 282         .num_resources  = ARRAY_SIZE(tmu0_resources),
 283 };
 284
 285 /* IPMMUI (an IPMMU module for ICB/LMB) */
 286 static struct resource ipmmu_resources[] = {
 287         [0] = {
 288                 .name   = "IPMMUI",
 289                 .start  = 0xfe951000,
 290                 .end    = 0xfe9510ff,
 291                 .flags  = IORESOURCE_MEM,
 292         },
 293 };
 294
 295 static const char * const ipmmu_dev_names[] = {
 296         "sh_mobile_lcdc_fb.0",
 297         "sh_mobile_lcdc_fb.1",
 298         "sh_mobile_ceu.0",
 299 };
 300
 301 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 302         .dev_names = ipmmu_dev_names,
 303         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 304 };
 305
 306 static struct platform_device ipmmu_device = {
 307         .name           = "ipmmu",
 308         .id             = -1,
 309         .dev = {
 310                 .platform_data = &ipmmu_platform_data,
 311         },
 312         .resource       = ipmmu_resources,
 313         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 314 };
 315
 316 static struct platform_device *r8a7740_early_devices[] __initdata = {
 317         &scif0_device,
 318         &scif1_device,
 319         &scif2_device,
 320         &scif3_device,
 321         &scif4_device,
 322         &scif5_device,
 323         &scif6_device,
 324         &scif7_device,
 325         &scif8_device,
 326         &irqpin0_device,
 327         &irqpin1_device,
 328         &irqpin2_device,
 329         &irqpin3_device,
 330         &tmu0_device,
 331         &ipmmu_device,
 332         &cmt1_device,
 333 };
 334
 335 /* DMA */
 336 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
 337         {
 338                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 339                 .addr           = 0xe6850030,
 340                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 341                 .mid_rid        = 0xc1,
 342         }, {
 343                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 344                 .addr           = 0xe6850030,
 345                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 346                 .mid_rid        = 0xc2,
 347         }, {
 348                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 349                 .addr           = 0xe6860030,
 350                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 351                 .mid_rid        = 0xc9,
 352         }, {
 353                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 354                 .addr           = 0xe6860030,
 355                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 356                 .mid_rid        = 0xca,
 357         }, {
 358                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 359                 .addr           = 0xe6870030,
 360                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 361                 .mid_rid        = 0xcd,
 362         }, {
 363                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 364                 .addr           = 0xe6870030,
 365                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 366                 .mid_rid        = 0xce,
 367         }, {
 368                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 369                 .addr           = 0xfe1f0024,
 370                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 371                 .mid_rid        = 0xb1,
 372         }, {
 373                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 374                 .addr           = 0xfe1f0020,
 375                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 376                 .mid_rid        = 0xb2,
 377         }, {
 378                 .slave_id       = SHDMA_SLAVE_FSIB_TX,
 379                 .addr           = 0xfe1f0064,
 380                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 381                 .mid_rid        = 0xb5,
 382         }, {
 383                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 384                 .addr           = 0xe6bd0034,
 385                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 386                 .mid_rid        = 0xd1,
 387         }, {
 388                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 389                 .addr           = 0xe6bd0034,
 390                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 391                 .mid_rid        = 0xd2,
 392         },
 393 };
 394
 395 #define DMA_CHANNEL(a, b, c)                    \
 396 {                                               \
 397         .offset         = a,                    \
 398         .dmars          = b,                    \
 399         .dmars_bit      = c,                    \
 400         .chclr_offset   = (0x220 - 0x20) + a    \
 401 }
 402
 403 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
 404         DMA_CHANNEL(0x00, 0, 0),
 405         DMA_CHANNEL(0x10, 0, 8),
 406         DMA_CHANNEL(0x20, 4, 0),
 407         DMA_CHANNEL(0x30, 4, 8),
 408         DMA_CHANNEL(0x50, 8, 0),
 409         DMA_CHANNEL(0x60, 8, 8),
 410 };
 411
 412 static struct sh_dmae_pdata dma_platform_data = {
 413         .slave          = r8a7740_dmae_slaves,
 414         .slave_num      = ARRAY_SIZE(r8a7740_dmae_slaves),
 415         .channel        = r8a7740_dmae_channels,
 416         .channel_num    = ARRAY_SIZE(r8a7740_dmae_channels),
 417         .ts_low_shift   = TS_LOW_SHIFT,
 418         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 419         .ts_high_shift  = TS_HI_SHIFT,
 420         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 421         .ts_shift       = dma_ts_shift,
 422         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 423         .dmaor_init     = DMAOR_DME,
 424         .chclr_present  = 1,
 425 };
 426
 427 /* Resource order important! */
 428 static struct resource r8a7740_dmae0_resources[] = {
 429         {
 430                 /* Channel registers and DMAOR */
 431                 .start  = 0xfe008020,
 432                 .end    = 0xfe00828f,
 433                 .flags  = IORESOURCE_MEM,
 434         },
 435         {
 436                 /* DMARSx */
 437                 .start  = 0xfe009000,
 438                 .end    = 0xfe00900b,
 439                 .flags  = IORESOURCE_MEM,
 440         },
 441         {
 442                 .name   = "error_irq",
 443                 .start  = gic_spi(34),
 444                 .end    = gic_spi(34),
 445                 .flags  = IORESOURCE_IRQ,
 446         },
 447         {
 448                 /* IRQ for channels 0-5 */
 449                 .start  = gic_spi(28),
 450                 .end    = gic_spi(33),
 451                 .flags  = IORESOURCE_IRQ,
 452         },
 453 };
 454
 455 /* Resource order important! */
 456 static struct resource r8a7740_dmae1_resources[] = {
 457         {
 458                 /* Channel registers and DMAOR */
 459                 .start  = 0xfe018020,
 460                 .end    = 0xfe01828f,
 461                 .flags  = IORESOURCE_MEM,
 462         },
 463         {
 464                 /* DMARSx */
 465                 .start  = 0xfe019000,
 466                 .end    = 0xfe01900b,
 467                 .flags  = IORESOURCE_MEM,
 468         },
 469         {
 470                 .name   = "error_irq",
 471                 .start  = gic_spi(41),
 472                 .end    = gic_spi(41),
 473                 .flags  = IORESOURCE_IRQ,
 474         },
 475         {
 476                 /* IRQ for channels 0-5 */
 477                 .start  = gic_spi(35),
 478                 .end    = gic_spi(40),
 479                 .flags  = IORESOURCE_IRQ,
 480         },
 481 };
 482
 483 /* Resource order important! */
 484 static struct resource r8a7740_dmae2_resources[] = {
 485         {
 486                 /* Channel registers and DMAOR */
 487                 .start  = 0xfe028020,
 488                 .end    = 0xfe02828f,
 489                 .flags  = IORESOURCE_MEM,
 490         },
 491         {
 492                 /* DMARSx */
 493                 .start  = 0xfe029000,
 494                 .end    = 0xfe02900b,
 495                 .flags  = IORESOURCE_MEM,
 496         },
 497         {
 498                 .name   = "error_irq",
 499                 .start  = gic_spi(48),
 500                 .end    = gic_spi(48),
 501                 .flags  = IORESOURCE_IRQ,
 502         },
 503         {
 504                 /* IRQ for channels 0-5 */
 505                 .start  = gic_spi(42),
 506                 .end    = gic_spi(47),
 507                 .flags  = IORESOURCE_IRQ,
 508         },
 509 };
 510
 511 static struct platform_device dma0_device = {
 512         .name           = "sh-dma-engine",
 513         .id             = 0,
 514         .resource       = r8a7740_dmae0_resources,
 515         .num_resources  = ARRAY_SIZE(r8a7740_dmae0_resources),
 516         .dev            = {
 517                 .platform_data  = &dma_platform_data,
 518         },
 519 };
 520
 521 static struct platform_device dma1_device = {
 522         .name           = "sh-dma-engine",
 523         .id             = 1,
 524         .resource       = r8a7740_dmae1_resources,
 525         .num_resources  = ARRAY_SIZE(r8a7740_dmae1_resources),
 526         .dev            = {
 527                 .platform_data  = &dma_platform_data,
 528         },
 529 };
 530
 531 static struct platform_device dma2_device = {
 532         .name           = "sh-dma-engine",
 533         .id             = 2,
 534         .resource       = r8a7740_dmae2_resources,
 535         .num_resources  = ARRAY_SIZE(r8a7740_dmae2_resources),
 536         .dev            = {
 537                 .platform_data  = &dma_platform_data,
 538         },
 539 };
 540
 541 /* USB-DMAC */
 542 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
 543         {
 544                 .offset = 0,
 545         }, {
 546                 .offset = 0x20,
 547         },
 548 };
 549
 550 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
 551         {
 552                 .slave_id       = SHDMA_SLAVE_USBHS_TX,
 553                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 554         }, {
 555                 .slave_id       = SHDMA_SLAVE_USBHS_RX,
 556                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 557         },
 558 };
 559
 560 static struct sh_dmae_pdata usb_dma_platform_data = {
 561         .slave          = r8a7740_usb_dma_slaves,
 562         .slave_num      = ARRAY_SIZE(r8a7740_usb_dma_slaves),
 563         .channel        = r8a7740_usb_dma_channels,
 564         .channel_num    = ARRAY_SIZE(r8a7740_usb_dma_channels),
 565         .ts_low_shift   = USBTS_LOW_SHIFT,
 566         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 567         .ts_high_shift  = USBTS_HI_SHIFT,
 568         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 569         .ts_shift       = dma_usbts_shift,
 570         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 571         .dmaor_init     = DMAOR_DME,
 572         .chcr_offset    = 0x14,
 573         .chcr_ie_bit    = 1 << 5,
 574         .dmaor_is_32bit = 1,
 575         .needs_tend_set = 1,
 576         .no_dmars       = 1,
 577         .slave_only     = 1,
 578 };
 579
 580 static struct resource r8a7740_usb_dma_resources[] = {
 581         {
 582                 /* Channel registers and DMAOR */
 583                 .start  = 0xe68a0020,
 584                 .end    = 0xe68a0064 - 1,
 585                 .flags  = IORESOURCE_MEM,
 586         },
 587         {
 588                 /* VCR/SWR/DMICR */
 589                 .start  = 0xe68a0000,
 590                 .end    = 0xe68a0014 - 1,
 591                 .flags  = IORESOURCE_MEM,
 592         },
 593         {
 594                 /* IRQ for channels */
 595                 .start  = gic_spi(49),
 596                 .end    = gic_spi(49),
 597                 .flags  = IORESOURCE_IRQ,
 598         },
 599 };
 600
 601 static struct platform_device usb_dma_device = {
 602         .name           = "sh-dma-engine",
 603         .id             = 3,
 604         .resource       = r8a7740_usb_dma_resources,
 605         .num_resources  = ARRAY_SIZE(r8a7740_usb_dma_resources),
 606         .dev            = {
 607                 .platform_data  = &usb_dma_platform_data,
 608         },
 609 };
 610
 611 /* I2C */
 612 static struct resource i2c0_resources[] = {
 613         [0] = {
 614                 .name   = "IIC0",
 615                 .start  = 0xfff20000,
 616                 .end    = 0xfff20425 - 1,
 617                 .flags  = IORESOURCE_MEM,
 618         },
 619         [1] = {
 620                 .start  = gic_spi(201),
 621                 .end    = gic_spi(204),
 622                 .flags  = IORESOURCE_IRQ,
 623         },
 624 };
 625
 626 static struct resource i2c1_resources[] = {
 627         [0] = {
 628                 .name   = "IIC1",
 629                 .start  = 0xe6c20000,
 630                 .end    = 0xe6c20425 - 1,
 631                 .flags  = IORESOURCE_MEM,
 632         },
 633         [1] = {
 634                 .start  = gic_spi(70), /* IIC1_ALI1 */
 635                 .end    = gic_spi(73), /* IIC1_DTEI1 */
 636                 .flags  = IORESOURCE_IRQ,
 637         },
 638 };
 639
 640 static struct platform_device i2c0_device = {
 641         .name           = "i2c-sh_mobile",
 642         .id             = 0,
 643         .resource       = i2c0_resources,
 644         .num_resources  = ARRAY_SIZE(i2c0_resources),
 645 };
 646
 647 static struct platform_device i2c1_device = {
 648         .name           = "i2c-sh_mobile",
 649         .id             = 1,
 650         .resource       = i2c1_resources,
 651         .num_resources  = ARRAY_SIZE(i2c1_resources),
 652 };
 653
 654 static struct resource pmu_resources[] = {
 655         [0] = {
 656                 .start  = gic_spi(83),
 657                 .end    = gic_spi(83),
 658                 .flags  = IORESOURCE_IRQ,
 659         },
 660 };
 661
 662 static struct platform_device pmu_device = {
 663         .name   = "arm-pmu",
 664         .id     = -1,
 665         .num_resources = ARRAY_SIZE(pmu_resources),
 666         .resource = pmu_resources,
 667 };
 668
 669 static struct platform_device *r8a7740_late_devices[] __initdata = {
 670         &i2c0_device,
 671         &i2c1_device,
 672         &dma0_device,
 673         &dma1_device,
 674         &dma2_device,
 675         &usb_dma_device,
 676         &pmu_device,
 677 };
 678
 679 /*
 680  * r8a7740 chip has lasting errata on MERAM buffer.
 681  * this is work-around for it.
 682  * see
 683  *      "Media RAM (MERAM)" on r8a7740 documentation
 684  */
 685 #define MEBUFCNTR       0xFE950098
 686 void __init r8a7740_meram_workaround(void)
 687 {
 688         void __iomem *reg;
 689
 690         reg = ioremap_nocache(MEBUFCNTR, 4);
 691         if (reg) {
 692                 iowrite32(0x01600164, reg);
 693                 iounmap(reg);
 694         }
 695 }
 696
 697 #define ICCR    0x0004
 698 #define ICSTART 0x0070
 699
 700 #define i2c_read(reg, offset)           ioread8(reg + offset)
 701 #define i2c_write(reg, offset, data)    iowrite8(data, reg + offset)
 702
 703 /*
 704  * r8a7740 chip has lasting errata on I2C I/O pad reset.
 705  * this is work-around for it.
 706  */
 707 static void r8a7740_i2c_workaround(struct platform_device *pdev)
 708 {
 709         struct resource *res;
 710         void __iomem *reg;
 711
 712         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 713         if (unlikely(!res)) {
 714                 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
 715                 return;
 716         }
 717
 718         reg = ioremap(res->start, resource_size(res));
 719         if (unlikely(!reg)) {
 720                 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
 721                 return;
 722         }
 723
 724         i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
 725         i2c_read(reg, ICCR); /* dummy read */
 726
 727         i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
 728         i2c_read(reg, ICSTART); /* dummy read */
 729
 730         udelay(10);
 731
 732         i2c_write(reg, ICCR, 0x01);
 733         i2c_write(reg, ICSTART, 0x00);
 734
 735         udelay(10);
 736
 737         i2c_write(reg, ICCR, 0x10);
 738         udelay(10);
 739         i2c_write(reg, ICCR, 0x00);
 740         udelay(10);
 741         i2c_write(reg, ICCR, 0x10);
 742         udelay(10);
 743
 744         iounmap(reg);
 745 }
 746
 747 void __init r8a7740_add_standard_devices(void)
 748 {
 749         static struct pm_domain_device domain_devices[] __initdata = {
 750                 { "A3SP", &scif0_device },
 751                 { "A3SP", &scif1_device },
 752                 { "A3SP", &scif2_device },
 753                 { "A3SP", &scif3_device },
 754                 { "A3SP", &scif4_device },
 755                 { "A3SP", &scif5_device },
 756                 { "A3SP", &scif6_device },
 757                 { "A3SP", &scif7_device },
 758                 { "A3SP", &scif8_device },
 759                 { "A3SP", &i2c1_device },
 760         };
 761
 762         /* I2C work-around */
 763         r8a7740_i2c_workaround(&i2c0_device);
 764         r8a7740_i2c_workaround(&i2c1_device);
 765
 766         r8a7740_init_pm_domains();
 767
 768         /* add devices */
 769         platform_add_devices(r8a7740_early_devices,
 770                             ARRAY_SIZE(r8a7740_early_devices));
 771         platform_add_devices(r8a7740_late_devices,
 772                              ARRAY_SIZE(r8a7740_late_devices));
 773
 774         /* add devices to PM domain  */
 775         rmobile_add_devices_to_domains(domain_devices,
 776                                        ARRAY_SIZE(domain_devices));
 777 }
 778
 779 void __init r8a7740_add_early_devices(void)
 780 {
 781         early_platform_add_devices(r8a7740_early_devices,
 782                                    ARRAY_SIZE(r8a7740_early_devices));
 783
 784         /* setup early console here as well */
 785         shmobile_setup_console();
 786 }
 787
 788 #ifdef CONFIG_USE_OF
 789
 790 void __init r8a7740_init_irq_of(void)
 791 {
 792         void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
 793         void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
 794         void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
 795
 796 #ifdef CONFIG_ARCH_SHMOBILE_LEGACY
 797         void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
 798         void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
 799
 800         gic_init(0, 29, gic_dist_base, gic_cpu_base);
 801 #else
 802         irqchip_init();
 803 #endif
 804
 805         /* route signals to GIC */
 806         iowrite32(0x0, pfc_inta_ctrl);
 807
 808         /*
 809          * To mask the shared interrupt to SPI 149 we must ensure to set
 810          * PRIO *and* MASK. Else we run into IRQ floods when registering
 811          * the intc_irqpin devices
 812          */
 813         iowrite32(0x0, intc_prio_base + 0x0);
 814         iowrite32(0x0, intc_prio_base + 0x4);
 815         iowrite32(0x0, intc_prio_base + 0x8);
 816         iowrite32(0x0, intc_prio_base + 0xc);
 817         iowrite8(0xff, intc_msk_base + 0x0);
 818         iowrite8(0xff, intc_msk_base + 0x4);
 819         iowrite8(0xff, intc_msk_base + 0x8);
 820         iowrite8(0xff, intc_msk_base + 0xc);
 821
 822         iounmap(intc_prio_base);
 823         iounmap(intc_msk_base);
 824         iounmap(pfc_inta_ctrl);
 825 }
 826
 827 static void __init r8a7740_generic_init(void)
 828 {
 829         r8a7740_meram_workaround();
 830
 831 #ifdef CONFIG_CACHE_L2X0
 832         /* Shared attribute override enable, 32K*8way */
 833         l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
 834 #endif
 835         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 836 }
 837
 838 #define RESCNT2 IOMEM(0xe6188020)
 839 static void r8a7740_restart(enum reboot_mode mode, const char *cmd)
 840 {
 841         /* Do soft power on reset */
 842         writel(1 << 31, RESCNT2);
 843 }
 844
 845 static const char *r8a7740_boards_compat_dt[] __initdata = {
 846         "renesas,r8a7740",
 847         NULL,
 848 };
 849
 850 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
 851         .map_io         = r8a7740_map_io,
 852         .init_early     = shmobile_init_delay,
 853         .init_irq       = r8a7740_init_irq_of,
 854         .init_machine   = r8a7740_generic_init,
 855         .init_late      = shmobile_init_late,
 856         .dt_compat      = r8a7740_boards_compat_dt,
 857         .restart        = r8a7740_restart,
 858 MACHINE_END
 859
 860 #endif /* CONFIG_USE_OF */