arch/arm/mach-shmobile/setup-r8a7740.c

   1 /*
   2  * R8A7740 processor support
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/io.h>
  21 #include <linux/irqchip.h>
  22 #include <linux/irqchip/arm-gic.h>
  23 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/serial_sci.h>
  27 #include <linux/sh_dma.h>
  28 #include <linux/sh_timer.h>
  29 #include <linux/platform_data/sh_ipmmu.h>
  30
  31 #include <asm/mach-types.h>
  32 #include <asm/mach/map.h>
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/time.h>
  35 #include <asm/hardware/cache-l2x0.h>
  36
  37 #include "common.h"
  38 #include "dma-register.h"
  39 #include "irqs.h"
  40 #include "pm-rmobile.h"
  41 #include "r8a7740.h"
  42
  43 static struct map_desc r8a7740_io_desc[] __initdata = {
  44          /*
  45           * for CPGA/INTC/PFC
  46           * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
  47           */
  48         {
  49                 .virtual        = 0xe6000000,
  50                 .pfn            = __phys_to_pfn(0xe6000000),
  51                 .length         = 160 << 20,
  52                 .type           = MT_DEVICE_NONSHARED
  53         },
  54 #ifdef CONFIG_CACHE_L2X0
  55         /*
  56          * for l2x0_init()
  57          * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
  58          */
  59         {
  60                 .virtual        = 0xf0002000,
  61                 .pfn            = __phys_to_pfn(0xf0100000),
  62                 .length         = PAGE_SIZE,
  63                 .type           = MT_DEVICE_NONSHARED
  64         },
  65 #endif
  66 };
  67
  68 void __init r8a7740_map_io(void)
  69 {
  70         iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
  71 }
  72
  73 /* PFC */
  74 static const struct resource pfc_resources[] = {
  75         DEFINE_RES_MEM(0xe6050000, 0x8000),
  76         DEFINE_RES_MEM(0xe605800c, 0x0020),
  77 };
  78
  79 void __init r8a7740_pinmux_init(void)
  80 {
  81         platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
  82                                         ARRAY_SIZE(pfc_resources));
  83 }
  84
  85 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
  86         .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
  87 };
  88
  89 static struct resource irqpin0_resources[] = {
  90         DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
  91         DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
  92         DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
  93         DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
  94         DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
  95         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
  96         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
  97         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
  98         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
  99         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
 100         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
 101         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
 102         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
 103 };
 104
 105 static struct platform_device irqpin0_device = {
 106         .name           = "renesas_intc_irqpin",
 107         .id             = 0,
 108         .resource       = irqpin0_resources,
 109         .num_resources  = ARRAY_SIZE(irqpin0_resources),
 110         .dev            = {
 111                 .platform_data  = &irqpin0_platform_data,
 112         },
 113 };
 114
 115 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
 116         .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
 117 };
 118
 119 static struct resource irqpin1_resources[] = {
 120         DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
 121         DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
 122         DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
 123         DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
 124         DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
 125         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
 126         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
 127         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
 128         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
 129         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
 130         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
 131         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
 132         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
 133 };
 134
 135 static struct platform_device irqpin1_device = {
 136         .name           = "renesas_intc_irqpin",
 137         .id             = 1,
 138         .resource       = irqpin1_resources,
 139         .num_resources  = ARRAY_SIZE(irqpin1_resources),
 140         .dev            = {
 141                 .platform_data  = &irqpin1_platform_data,
 142         },
 143 };
 144
 145 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
 146         .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
 147 };
 148
 149 static struct resource irqpin2_resources[] = {
 150         DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
 151         DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
 152         DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
 153         DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
 154         DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
 155         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
 156         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
 157         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
 158         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
 159         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
 160         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
 161         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
 162         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
 163 };
 164
 165 static struct platform_device irqpin2_device = {
 166         .name           = "renesas_intc_irqpin",
 167         .id             = 2,
 168         .resource       = irqpin2_resources,
 169         .num_resources  = ARRAY_SIZE(irqpin2_resources),
 170         .dev            = {
 171                 .platform_data  = &irqpin2_platform_data,
 172         },
 173 };
 174
 175 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
 176         .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
 177 };
 178
 179 static struct resource irqpin3_resources[] = {
 180         DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
 181         DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
 182         DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
 183         DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
 184         DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
 185         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
 186         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
 187         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
 188         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
 189         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
 190         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
 191         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
 192         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
 193 };
 194
 195 static struct platform_device irqpin3_device = {
 196         .name           = "renesas_intc_irqpin",
 197         .id             = 3,
 198         .resource       = irqpin3_resources,
 199         .num_resources  = ARRAY_SIZE(irqpin3_resources),
 200         .dev            = {
 201                 .platform_data  = &irqpin3_platform_data,
 202         },
 203 };
 204
 205 /* SCIF */
 206 #define R8A7740_SCIF(scif_type, index, baseaddr, irq)           \
 207 static struct plat_sci_port scif##index##_platform_data = {     \
 208         .type           = scif_type,                            \
 209         .flags          = UPF_BOOT_AUTOCONF,                    \
 210         .scscr          = SCSCR_RE | SCSCR_TE,                  \
 211 };                                                              \
 212                                                                 \
 213 static struct resource scif##index##_resources[] = {            \
 214         DEFINE_RES_MEM(baseaddr, 0x100),                        \
 215         DEFINE_RES_IRQ(irq),                                    \
 216 };                                                              \
 217                                                                 \
 218 static struct platform_device scif##index##_device = {          \
 219         .name           = "sh-sci",                             \
 220         .id             = index,                                \
 221         .resource       = scif##index##_resources,              \
 222         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 223         .dev            = {                                     \
 224                 .platform_data  = &scif##index##_platform_data, \
 225         },                                                      \
 226 }
 227
 228 R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
 229 R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
 230 R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
 231 R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
 232 R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
 233 R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
 234 R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
 235 R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
 236 R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
 237
 238 /* CMT */
 239 static struct sh_timer_config cmt1_platform_data = {
 240         .channels_mask = 0x3f,
 241 };
 242
 243 static struct resource cmt1_resources[] = {
 244         DEFINE_RES_MEM(0xe6138000, 0x170),
 245         DEFINE_RES_IRQ(gic_spi(58)),
 246 };
 247
 248 static struct platform_device cmt1_device = {
 249         .name           = "sh-cmt-48",
 250         .id             = 1,
 251         .dev = {
 252                 .platform_data  = &cmt1_platform_data,
 253         },
 254         .resource       = cmt1_resources,
 255         .num_resources  = ARRAY_SIZE(cmt1_resources),
 256 };
 257
 258 /* TMU */
 259 static struct sh_timer_config tmu0_platform_data = {
 260         .channels_mask = 7,
 261 };
 262
 263 static struct resource tmu0_resources[] = {
 264         DEFINE_RES_MEM(0xfff80000, 0x2c),
 265         DEFINE_RES_IRQ(gic_spi(198)),
 266         DEFINE_RES_IRQ(gic_spi(199)),
 267         DEFINE_RES_IRQ(gic_spi(200)),
 268 };
 269
 270 static struct platform_device tmu0_device = {
 271         .name           = "sh-tmu",
 272         .id             = 0,
 273         .dev = {
 274                 .platform_data  = &tmu0_platform_data,
 275         },
 276         .resource       = tmu0_resources,
 277         .num_resources  = ARRAY_SIZE(tmu0_resources),
 278 };
 279
 280 /* IPMMUI (an IPMMU module for ICB/LMB) */
 281 static struct resource ipmmu_resources[] = {
 282         [0] = {
 283                 .name   = "IPMMUI",
 284                 .start  = 0xfe951000,
 285                 .end    = 0xfe9510ff,
 286                 .flags  = IORESOURCE_MEM,
 287         },
 288 };
 289
 290 static const char * const ipmmu_dev_names[] = {
 291         "sh_mobile_lcdc_fb.0",
 292         "sh_mobile_lcdc_fb.1",
 293         "sh_mobile_ceu.0",
 294 };
 295
 296 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 297         .dev_names = ipmmu_dev_names,
 298         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 299 };
 300
 301 static struct platform_device ipmmu_device = {
 302         .name           = "ipmmu",
 303         .id             = -1,
 304         .dev = {
 305                 .platform_data = &ipmmu_platform_data,
 306         },
 307         .resource       = ipmmu_resources,
 308         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 309 };
 310
 311 static struct platform_device *r8a7740_early_devices[] __initdata = {
 312         &scif0_device,
 313         &scif1_device,
 314         &scif2_device,
 315         &scif3_device,
 316         &scif4_device,
 317         &scif5_device,
 318         &scif6_device,
 319         &scif7_device,
 320         &scif8_device,
 321         &irqpin0_device,
 322         &irqpin1_device,
 323         &irqpin2_device,
 324         &irqpin3_device,
 325         &tmu0_device,
 326         &ipmmu_device,
 327         &cmt1_device,
 328 };
 329
 330 /* DMA */
 331 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
 332         {
 333                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 334                 .addr           = 0xe6850030,
 335                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 336                 .mid_rid        = 0xc1,
 337         }, {
 338                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 339                 .addr           = 0xe6850030,
 340                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 341                 .mid_rid        = 0xc2,
 342         }, {
 343                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 344                 .addr           = 0xe6860030,
 345                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 346                 .mid_rid        = 0xc9,
 347         }, {
 348                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 349                 .addr           = 0xe6860030,
 350                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 351                 .mid_rid        = 0xca,
 352         }, {
 353                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 354                 .addr           = 0xe6870030,
 355                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 356                 .mid_rid        = 0xcd,
 357         }, {
 358                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 359                 .addr           = 0xe6870030,
 360                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 361                 .mid_rid        = 0xce,
 362         }, {
 363                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 364                 .addr           = 0xfe1f0024,
 365                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 366                 .mid_rid        = 0xb1,
 367         }, {
 368                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 369                 .addr           = 0xfe1f0020,
 370                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 371                 .mid_rid        = 0xb2,
 372         }, {
 373                 .slave_id       = SHDMA_SLAVE_FSIB_TX,
 374                 .addr           = 0xfe1f0064,
 375                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 376                 .mid_rid        = 0xb5,
 377         }, {
 378                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 379                 .addr           = 0xe6bd0034,
 380                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 381                 .mid_rid        = 0xd1,
 382         }, {
 383                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 384                 .addr           = 0xe6bd0034,
 385                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 386                 .mid_rid        = 0xd2,
 387         },
 388 };
 389
 390 #define DMA_CHANNEL(a, b, c)                    \
 391 {                                               \
 392         .offset         = a,                    \
 393         .dmars          = b,                    \
 394         .dmars_bit      = c,                    \
 395         .chclr_offset   = (0x220 - 0x20) + a    \
 396 }
 397
 398 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
 399         DMA_CHANNEL(0x00, 0, 0),
 400         DMA_CHANNEL(0x10, 0, 8),
 401         DMA_CHANNEL(0x20, 4, 0),
 402         DMA_CHANNEL(0x30, 4, 8),
 403         DMA_CHANNEL(0x50, 8, 0),
 404         DMA_CHANNEL(0x60, 8, 8),
 405 };
 406
 407 static struct sh_dmae_pdata dma_platform_data = {
 408         .slave          = r8a7740_dmae_slaves,
 409         .slave_num      = ARRAY_SIZE(r8a7740_dmae_slaves),
 410         .channel        = r8a7740_dmae_channels,
 411         .channel_num    = ARRAY_SIZE(r8a7740_dmae_channels),
 412         .ts_low_shift   = TS_LOW_SHIFT,
 413         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 414         .ts_high_shift  = TS_HI_SHIFT,
 415         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 416         .ts_shift       = dma_ts_shift,
 417         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 418         .dmaor_init     = DMAOR_DME,
 419         .chclr_present  = 1,
 420 };
 421
 422 /* Resource order important! */
 423 static struct resource r8a7740_dmae0_resources[] = {
 424         {
 425                 /* Channel registers and DMAOR */
 426                 .start  = 0xfe008020,
 427                 .end    = 0xfe00828f,
 428                 .flags  = IORESOURCE_MEM,
 429         },
 430         {
 431                 /* DMARSx */
 432                 .start  = 0xfe009000,
 433                 .end    = 0xfe00900b,
 434                 .flags  = IORESOURCE_MEM,
 435         },
 436         {
 437                 .name   = "error_irq",
 438                 .start  = gic_spi(34),
 439                 .end    = gic_spi(34),
 440                 .flags  = IORESOURCE_IRQ,
 441         },
 442         {
 443                 /* IRQ for channels 0-5 */
 444                 .start  = gic_spi(28),
 445                 .end    = gic_spi(33),
 446                 .flags  = IORESOURCE_IRQ,
 447         },
 448 };
 449
 450 /* Resource order important! */
 451 static struct resource r8a7740_dmae1_resources[] = {
 452         {
 453                 /* Channel registers and DMAOR */
 454                 .start  = 0xfe018020,
 455                 .end    = 0xfe01828f,
 456                 .flags  = IORESOURCE_MEM,
 457         },
 458         {
 459                 /* DMARSx */
 460                 .start  = 0xfe019000,
 461                 .end    = 0xfe01900b,
 462                 .flags  = IORESOURCE_MEM,
 463         },
 464         {
 465                 .name   = "error_irq",
 466                 .start  = gic_spi(41),
 467                 .end    = gic_spi(41),
 468                 .flags  = IORESOURCE_IRQ,
 469         },
 470         {
 471                 /* IRQ for channels 0-5 */
 472                 .start  = gic_spi(35),
 473                 .end    = gic_spi(40),
 474                 .flags  = IORESOURCE_IRQ,
 475         },
 476 };
 477
 478 /* Resource order important! */
 479 static struct resource r8a7740_dmae2_resources[] = {
 480         {
 481                 /* Channel registers and DMAOR */
 482                 .start  = 0xfe028020,
 483                 .end    = 0xfe02828f,
 484                 .flags  = IORESOURCE_MEM,
 485         },
 486         {
 487                 /* DMARSx */
 488                 .start  = 0xfe029000,
 489                 .end    = 0xfe02900b,
 490                 .flags  = IORESOURCE_MEM,
 491         },
 492         {
 493                 .name   = "error_irq",
 494                 .start  = gic_spi(48),
 495                 .end    = gic_spi(48),
 496                 .flags  = IORESOURCE_IRQ,
 497         },
 498         {
 499                 /* IRQ for channels 0-5 */
 500                 .start  = gic_spi(42),
 501                 .end    = gic_spi(47),
 502                 .flags  = IORESOURCE_IRQ,
 503         },
 504 };
 505
 506 static struct platform_device dma0_device = {
 507         .name           = "sh-dma-engine",
 508         .id             = 0,
 509         .resource       = r8a7740_dmae0_resources,
 510         .num_resources  = ARRAY_SIZE(r8a7740_dmae0_resources),
 511         .dev            = {
 512                 .platform_data  = &dma_platform_data,
 513         },
 514 };
 515
 516 static struct platform_device dma1_device = {
 517         .name           = "sh-dma-engine",
 518         .id             = 1,
 519         .resource       = r8a7740_dmae1_resources,
 520         .num_resources  = ARRAY_SIZE(r8a7740_dmae1_resources),
 521         .dev            = {
 522                 .platform_data  = &dma_platform_data,
 523         },
 524 };
 525
 526 static struct platform_device dma2_device = {
 527         .name           = "sh-dma-engine",
 528         .id             = 2,
 529         .resource       = r8a7740_dmae2_resources,
 530         .num_resources  = ARRAY_SIZE(r8a7740_dmae2_resources),
 531         .dev            = {
 532                 .platform_data  = &dma_platform_data,
 533         },
 534 };
 535
 536 /* USB-DMAC */
 537 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
 538         {
 539                 .offset = 0,
 540         }, {
 541                 .offset = 0x20,
 542         },
 543 };
 544
 545 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
 546         {
 547                 .slave_id       = SHDMA_SLAVE_USBHS_TX,
 548                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 549         }, {
 550                 .slave_id       = SHDMA_SLAVE_USBHS_RX,
 551                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 552         },
 553 };
 554
 555 static struct sh_dmae_pdata usb_dma_platform_data = {
 556         .slave          = r8a7740_usb_dma_slaves,
 557         .slave_num      = ARRAY_SIZE(r8a7740_usb_dma_slaves),
 558         .channel        = r8a7740_usb_dma_channels,
 559         .channel_num    = ARRAY_SIZE(r8a7740_usb_dma_channels),
 560         .ts_low_shift   = USBTS_LOW_SHIFT,
 561         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 562         .ts_high_shift  = USBTS_HI_SHIFT,
 563         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 564         .ts_shift       = dma_usbts_shift,
 565         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 566         .dmaor_init     = DMAOR_DME,
 567         .chcr_offset    = 0x14,
 568         .chcr_ie_bit    = 1 << 5,
 569         .dmaor_is_32bit = 1,
 570         .needs_tend_set = 1,
 571         .no_dmars       = 1,
 572         .slave_only     = 1,
 573 };
 574
 575 static struct resource r8a7740_usb_dma_resources[] = {
 576         {
 577                 /* Channel registers and DMAOR */
 578                 .start  = 0xe68a0020,
 579                 .end    = 0xe68a0064 - 1,
 580                 .flags  = IORESOURCE_MEM,
 581         },
 582         {
 583                 /* VCR/SWR/DMICR */
 584                 .start  = 0xe68a0000,
 585                 .end    = 0xe68a0014 - 1,
 586                 .flags  = IORESOURCE_MEM,
 587         },
 588         {
 589                 /* IRQ for channels */
 590                 .start  = gic_spi(49),
 591                 .end    = gic_spi(49),
 592                 .flags  = IORESOURCE_IRQ,
 593         },
 594 };
 595
 596 static struct platform_device usb_dma_device = {
 597         .name           = "sh-dma-engine",
 598         .id             = 3,
 599         .resource       = r8a7740_usb_dma_resources,
 600         .num_resources  = ARRAY_SIZE(r8a7740_usb_dma_resources),
 601         .dev            = {
 602                 .platform_data  = &usb_dma_platform_data,
 603         },
 604 };
 605
 606 /* I2C */
 607 static struct resource i2c0_resources[] = {
 608         [0] = {
 609                 .name   = "IIC0",
 610                 .start  = 0xfff20000,
 611                 .end    = 0xfff20425 - 1,
 612                 .flags  = IORESOURCE_MEM,
 613         },
 614         [1] = {
 615                 .start  = gic_spi(201),
 616                 .end    = gic_spi(204),
 617                 .flags  = IORESOURCE_IRQ,
 618         },
 619 };
 620
 621 static struct resource i2c1_resources[] = {
 622         [0] = {
 623                 .name   = "IIC1",
 624                 .start  = 0xe6c20000,
 625                 .end    = 0xe6c20425 - 1,
 626                 .flags  = IORESOURCE_MEM,
 627         },
 628         [1] = {
 629                 .start  = gic_spi(70), /* IIC1_ALI1 */
 630                 .end    = gic_spi(73), /* IIC1_DTEI1 */
 631                 .flags  = IORESOURCE_IRQ,
 632         },
 633 };
 634
 635 static struct platform_device i2c0_device = {
 636         .name           = "i2c-sh_mobile",
 637         .id             = 0,
 638         .resource       = i2c0_resources,
 639         .num_resources  = ARRAY_SIZE(i2c0_resources),
 640 };
 641
 642 static struct platform_device i2c1_device = {
 643         .name           = "i2c-sh_mobile",
 644         .id             = 1,
 645         .resource       = i2c1_resources,
 646         .num_resources  = ARRAY_SIZE(i2c1_resources),
 647 };
 648
 649 static struct resource pmu_resources[] = {
 650         [0] = {
 651                 .start  = gic_spi(83),
 652                 .end    = gic_spi(83),
 653                 .flags  = IORESOURCE_IRQ,
 654         },
 655 };
 656
 657 static struct platform_device pmu_device = {
 658         .name   = "arm-pmu",
 659         .id     = -1,
 660         .num_resources = ARRAY_SIZE(pmu_resources),
 661         .resource = pmu_resources,
 662 };
 663
 664 static struct platform_device *r8a7740_late_devices[] __initdata = {
 665         &i2c0_device,
 666         &i2c1_device,
 667         &dma0_device,
 668         &dma1_device,
 669         &dma2_device,
 670         &usb_dma_device,
 671         &pmu_device,
 672 };
 673
 674 /*
 675  * r8a7740 chip has lasting errata on MERAM buffer.
 676  * this is work-around for it.
 677  * see
 678  *      "Media RAM (MERAM)" on r8a7740 documentation
 679  */
 680 #define MEBUFCNTR       0xFE950098
 681 void __init r8a7740_meram_workaround(void)
 682 {
 683         void __iomem *reg;
 684
 685         reg = ioremap_nocache(MEBUFCNTR, 4);
 686         if (reg) {
 687                 iowrite32(0x01600164, reg);
 688                 iounmap(reg);
 689         }
 690 }
 691
 692 #define ICCR    0x0004
 693 #define ICSTART 0x0070
 694
 695 #define i2c_read(reg, offset)           ioread8(reg + offset)
 696 #define i2c_write(reg, offset, data)    iowrite8(data, reg + offset)
 697
 698 /*
 699  * r8a7740 chip has lasting errata on I2C I/O pad reset.
 700  * this is work-around for it.
 701  */
 702 static void r8a7740_i2c_workaround(struct platform_device *pdev)
 703 {
 704         struct resource *res;
 705         void __iomem *reg;
 706
 707         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 708         if (unlikely(!res)) {
 709                 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
 710                 return;
 711         }
 712
 713         reg = ioremap(res->start, resource_size(res));
 714         if (unlikely(!reg)) {
 715                 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
 716                 return;
 717         }
 718
 719         i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
 720         i2c_read(reg, ICCR); /* dummy read */
 721
 722         i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
 723         i2c_read(reg, ICSTART); /* dummy read */
 724
 725         udelay(10);
 726
 727         i2c_write(reg, ICCR, 0x01);
 728         i2c_write(reg, ICSTART, 0x00);
 729
 730         udelay(10);
 731
 732         i2c_write(reg, ICCR, 0x10);
 733         udelay(10);
 734         i2c_write(reg, ICCR, 0x00);
 735         udelay(10);
 736         i2c_write(reg, ICCR, 0x10);
 737         udelay(10);
 738
 739         iounmap(reg);
 740 }
 741
 742 void __init r8a7740_add_standard_devices(void)
 743 {
 744         static struct pm_domain_device domain_devices[] __initdata = {
 745                 { "A3SP", &scif0_device },
 746                 { "A3SP", &scif1_device },
 747                 { "A3SP", &scif2_device },
 748                 { "A3SP", &scif3_device },
 749                 { "A3SP", &scif4_device },
 750                 { "A3SP", &scif5_device },
 751                 { "A3SP", &scif6_device },
 752                 { "A3SP", &scif7_device },
 753                 { "A3SP", &scif8_device },
 754                 { "A3SP", &i2c1_device },
 755         };
 756
 757         /* I2C work-around */
 758         r8a7740_i2c_workaround(&i2c0_device);
 759         r8a7740_i2c_workaround(&i2c1_device);
 760
 761         r8a7740_init_pm_domains();
 762
 763         /* add devices */
 764         platform_add_devices(r8a7740_early_devices,
 765                             ARRAY_SIZE(r8a7740_early_devices));
 766         platform_add_devices(r8a7740_late_devices,
 767                              ARRAY_SIZE(r8a7740_late_devices));
 768
 769         /* add devices to PM domain  */
 770         rmobile_add_devices_to_domains(domain_devices,
 771                                        ARRAY_SIZE(domain_devices));
 772 }
 773
 774 void __init r8a7740_add_early_devices(void)
 775 {
 776         early_platform_add_devices(r8a7740_early_devices,
 777                                    ARRAY_SIZE(r8a7740_early_devices));
 778
 779         /* setup early console here as well */
 780         shmobile_setup_console();
 781 }
 782
 783 #ifdef CONFIG_USE_OF
 784
 785 void __init r8a7740_init_irq_of(void)
 786 {
 787         void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
 788         void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
 789         void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
 790
 791         irqchip_init();
 792
 793         /* route signals to GIC */
 794         iowrite32(0x0, pfc_inta_ctrl);
 795
 796         /*
 797          * To mask the shared interrupt to SPI 149 we must ensure to set
 798          * PRIO *and* MASK. Else we run into IRQ floods when registering
 799          * the intc_irqpin devices
 800          */
 801         iowrite32(0x0, intc_prio_base + 0x0);
 802         iowrite32(0x0, intc_prio_base + 0x4);
 803         iowrite32(0x0, intc_prio_base + 0x8);
 804         iowrite32(0x0, intc_prio_base + 0xc);
 805         iowrite8(0xff, intc_msk_base + 0x0);
 806         iowrite8(0xff, intc_msk_base + 0x4);
 807         iowrite8(0xff, intc_msk_base + 0x8);
 808         iowrite8(0xff, intc_msk_base + 0xc);
 809
 810         iounmap(intc_prio_base);
 811         iounmap(intc_msk_base);
 812         iounmap(pfc_inta_ctrl);
 813 }
 814
 815 static void __init r8a7740_generic_init(void)
 816 {
 817         r8a7740_meram_workaround();
 818
 819 #ifdef CONFIG_CACHE_L2X0
 820         /* Shared attribute override enable, 32K*8way */
 821         l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
 822 #endif
 823         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 824 }
 825
 826 #define RESCNT2 IOMEM(0xe6188020)
 827 static void r8a7740_restart(enum reboot_mode mode, const char *cmd)
 828 {
 829         /* Do soft power on reset */
 830         writel(1 << 31, RESCNT2);
 831 }
 832
 833 static const char *r8a7740_boards_compat_dt[] __initdata = {
 834         "renesas,r8a7740",
 835         NULL,
 836 };
 837
 838 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
 839         .map_io         = r8a7740_map_io,
 840         .init_early     = shmobile_init_delay,
 841         .init_irq       = r8a7740_init_irq_of,
 842         .init_machine   = r8a7740_generic_init,
 843         .init_late      = shmobile_init_late,
 844         .dt_compat      = r8a7740_boards_compat_dt,
 845         .restart        = r8a7740_restart,
 846 MACHINE_END
 847
 848 #endif /* CONFIG_USE_OF */