arch/arm/mach-shmobile/setup-r8a7778.c

   1 /*
   2  * r8a7778 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/irqchip/arm-gic.h>
  25 #include <linux/of.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/platform_data/dma-rcar-hpbdma.h>
  28 #include <linux/platform_data/gpio-rcar.h>
  29 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/irqchip.h>
  32 #include <linux/serial_sci.h>
  33 #include <linux/sh_timer.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/usb/phy.h>
  36 #include <linux/usb/hcd.h>
  37 #include <linux/usb/ehci_pdriver.h>
  38 #include <linux/usb/ohci_pdriver.h>
  39 #include <linux/dma-mapping.h>
  40 #include <mach/irqs.h>
  41 #include <mach/r8a7778.h>
  42 #include <mach/common.h>
  43 #include <asm/mach/arch.h>
  44 #include <asm/hardware/cache-l2x0.h>
  45
  46 /* SCIF */
  47 #define R8A7778_SCIF(index, baseaddr, irq)                      \
  48 static struct plat_sci_port scif##index##_platform_data = {     \
  49         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
  50         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,     \
  51         .type           = PORT_SCIF,                            \
  52 };                                                              \
  53                                                                 \
  54 static struct resource scif##index##_resources[] = {            \
  55         DEFINE_RES_MEM(baseaddr, 0x100),                        \
  56         DEFINE_RES_IRQ(irq),                                    \
  57 }
  58
  59 R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
  60 R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
  61 R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
  62 R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
  63 R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
  64 R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
  65
  66 #define r8a7778_register_scif(index)                                           \
  67         platform_device_register_resndata(NULL, "sh-sci", index,               \
  68                                           scif##index##_resources,             \
  69                                           ARRAY_SIZE(scif##index##_resources), \
  70                                           &scif##index##_platform_data,        \
  71                                           sizeof(scif##index##_platform_data))
  72
  73 /* TMU */
  74 static struct sh_timer_config sh_tmu0_platform_data = {
  75         .channels_mask = 7,
  76 };
  77
  78 static struct resource sh_tmu0_resources[] = {
  79         DEFINE_RES_MEM(0xffd80000, 0x30),
  80         DEFINE_RES_IRQ(gic_iid(0x40)),
  81         DEFINE_RES_IRQ(gic_iid(0x41)),
  82         DEFINE_RES_IRQ(gic_iid(0x42)),
  83 };
  84
  85 #define r8a7778_register_tmu(idx)                       \
  86         platform_device_register_resndata(              \
  87                 NULL, "sh-tmu", idx,                    \
  88                 sh_tmu##idx##_resources,                \
  89                 ARRAY_SIZE(sh_tmu##idx##_resources),    \
  90                 &sh_tmu##idx##_platform_data,           \
  91                 sizeof(sh_tmu##idx##_platform_data))
  92
  93 int r8a7778_usb_phy_power(bool enable)
  94 {
  95         static struct usb_phy *phy = NULL;
  96         int ret = 0;
  97
  98         if (!phy)
  99                 phy = usb_get_phy(USB_PHY_TYPE_USB2);
 100
 101         if (IS_ERR(phy)) {
 102                 pr_err("kernel doesn't have usb phy driver\n");
 103                 return PTR_ERR(phy);
 104         }
 105
 106         if (enable)
 107                 ret = usb_phy_init(phy);
 108         else
 109                 usb_phy_shutdown(phy);
 110
 111         return ret;
 112 }
 113
 114 /* USB */
 115 static int usb_power_on(struct platform_device *pdev)
 116 {
 117         int ret = r8a7778_usb_phy_power(true);
 118
 119         if (ret)
 120                 return ret;
 121
 122         pm_runtime_enable(&pdev->dev);
 123         pm_runtime_get_sync(&pdev->dev);
 124
 125         return 0;
 126 }
 127
 128 static void usb_power_off(struct platform_device *pdev)
 129 {
 130         if (r8a7778_usb_phy_power(false))
 131                 return;
 132
 133         pm_runtime_put_sync(&pdev->dev);
 134         pm_runtime_disable(&pdev->dev);
 135 }
 136
 137 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
 138 {
 139         /*
 140          * Below are recommended values from the datasheet;
 141          * see [USB :: Setting of EHCI Internal Buffer].
 142          */
 143         /* EHCI IP internal buffer setting */
 144         iowrite32(0x00ff0040, hcd->regs + 0x0094);
 145         /* EHCI IP internal buffer enable */
 146         iowrite32(0x00000001, hcd->regs + 0x009C);
 147
 148         return 0;
 149 }
 150
 151 static struct usb_ehci_pdata ehci_pdata __initdata = {
 152         .power_on       = usb_power_on,
 153         .power_off      = usb_power_off,
 154         .power_suspend  = usb_power_off,
 155         .pre_setup      = ehci_init_internal_buffer,
 156 };
 157
 158 static struct resource ehci_resources[] __initdata = {
 159         DEFINE_RES_MEM(0xffe70000, 0x400),
 160         DEFINE_RES_IRQ(gic_iid(0x4c)),
 161 };
 162
 163 static struct usb_ohci_pdata ohci_pdata __initdata = {
 164         .power_on       = usb_power_on,
 165         .power_off      = usb_power_off,
 166         .power_suspend  = usb_power_off,
 167 };
 168
 169 static struct resource ohci_resources[] __initdata = {
 170         DEFINE_RES_MEM(0xffe70400, 0x400),
 171         DEFINE_RES_IRQ(gic_iid(0x4c)),
 172 };
 173
 174 #define USB_PLATFORM_INFO(hci)                                  \
 175 static struct platform_device_info hci##_info __initdata = {    \
 176         .name           = #hci "-platform",                     \
 177         .id             = -1,                                   \
 178         .res            = hci##_resources,                      \
 179         .num_res        = ARRAY_SIZE(hci##_resources),          \
 180         .data           = &hci##_pdata,                         \
 181         .size_data      = sizeof(hci##_pdata),                  \
 182         .dma_mask       = DMA_BIT_MASK(32),                     \
 183 }
 184
 185 USB_PLATFORM_INFO(ehci);
 186 USB_PLATFORM_INFO(ohci);
 187
 188 /* PFC/GPIO */
 189 static struct resource pfc_resources[] __initdata = {
 190         DEFINE_RES_MEM(0xfffc0000, 0x118),
 191 };
 192
 193 #define R8A7778_GPIO(idx)                                               \
 194 static struct resource r8a7778_gpio##idx##_resources[] __initdata = {   \
 195         DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),              \
 196         DEFINE_RES_IRQ(gic_iid(0x87)),                                  \
 197 };                                                                      \
 198                                                                         \
 199 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
 200         .gpio_base      = 32 * (idx),                                   \
 201         .irq_base       = GPIO_IRQ_BASE(idx),                           \
 202         .number_of_pins = 32,                                           \
 203         .pctl_name      = "pfc-r8a7778",                                \
 204 }
 205
 206 R8A7778_GPIO(0);
 207 R8A7778_GPIO(1);
 208 R8A7778_GPIO(2);
 209 R8A7778_GPIO(3);
 210 R8A7778_GPIO(4);
 211
 212 #define r8a7778_register_gpio(idx)                              \
 213         platform_device_register_resndata(                      \
 214                 NULL, "gpio_rcar", idx,                         \
 215                 r8a7778_gpio##idx##_resources,                  \
 216                 ARRAY_SIZE(r8a7778_gpio##idx##_resources),      \
 217                 &r8a7778_gpio##idx##_platform_data,             \
 218                 sizeof(r8a7778_gpio##idx##_platform_data))
 219
 220 void __init r8a7778_pinmux_init(void)
 221 {
 222         platform_device_register_simple(
 223                 "pfc-r8a7778", -1,
 224                 pfc_resources,
 225                 ARRAY_SIZE(pfc_resources));
 226
 227         r8a7778_register_gpio(0);
 228         r8a7778_register_gpio(1);
 229         r8a7778_register_gpio(2);
 230         r8a7778_register_gpio(3);
 231         r8a7778_register_gpio(4);
 232 };
 233
 234 /* I2C */
 235 static struct resource i2c_resources[] __initdata = {
 236         /* I2C0 */
 237         DEFINE_RES_MEM(0xffc70000, 0x1000),
 238         DEFINE_RES_IRQ(gic_iid(0x63)),
 239         /* I2C1 */
 240         DEFINE_RES_MEM(0xffc71000, 0x1000),
 241         DEFINE_RES_IRQ(gic_iid(0x6e)),
 242         /* I2C2 */
 243         DEFINE_RES_MEM(0xffc72000, 0x1000),
 244         DEFINE_RES_IRQ(gic_iid(0x6c)),
 245         /* I2C3 */
 246         DEFINE_RES_MEM(0xffc73000, 0x1000),
 247         DEFINE_RES_IRQ(gic_iid(0x6d)),
 248 };
 249
 250 static void __init r8a7778_register_i2c(int id)
 251 {
 252         BUG_ON(id < 0 || id > 3);
 253
 254         platform_device_register_simple(
 255                 "i2c-rcar", id,
 256                 i2c_resources + (2 * id), 2);
 257 }
 258
 259 /* HSPI */
 260 static struct resource hspi_resources[] __initdata = {
 261         /* HSPI0 */
 262         DEFINE_RES_MEM(0xfffc7000, 0x18),
 263         DEFINE_RES_IRQ(gic_iid(0x5f)),
 264         /* HSPI1 */
 265         DEFINE_RES_MEM(0xfffc8000, 0x18),
 266         DEFINE_RES_IRQ(gic_iid(0x74)),
 267         /* HSPI2 */
 268         DEFINE_RES_MEM(0xfffc6000, 0x18),
 269         DEFINE_RES_IRQ(gic_iid(0x75)),
 270 };
 271
 272 static void __init r8a7778_register_hspi(int id)
 273 {
 274         BUG_ON(id < 0 || id > 2);
 275
 276         platform_device_register_simple(
 277                 "sh-hspi", id,
 278                 hspi_resources + (2 * id), 2);
 279 }
 280
 281 void __init r8a7778_add_dt_devices(void)
 282 {
 283 #ifdef CONFIG_CACHE_L2X0
 284         void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
 285         if (base) {
 286                 /*
 287                  * Shared attribute override enable, 64K*16way
 288                  * don't call iounmap(base)
 289                  */
 290                 l2x0_init(base, 0x00400000, 0xc20f0fff);
 291         }
 292 #endif
 293
 294         r8a7778_register_scif(0);
 295         r8a7778_register_scif(1);
 296         r8a7778_register_scif(2);
 297         r8a7778_register_scif(3);
 298         r8a7778_register_scif(4);
 299         r8a7778_register_scif(5);
 300         r8a7778_register_tmu(0);
 301 }
 302
 303 /* HPB-DMA */
 304
 305 /* Asynchronous mode register (ASYNCMDR) bits */
 306 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK   BIT(2)  /* SDHI0 */
 307 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2)  /* SDHI0 */
 308 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI  0       /* SDHI0 */
 309 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK   BIT(1)  /* SDHI0 */
 310 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1)  /* SDHI0 */
 311 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI  0       /* SDHI0 */
 312
 313 #define HPBDMA_SSI(_id)                         \
 314 {                                               \
 315         .id     = HPBDMA_SLAVE_SSI## _id ##_TX, \
 316         .addr   = 0xffd91008 + (_id * 0x40),    \
 317         .dcr    = HPB_DMAE_DCR_CT |             \
 318                   HPB_DMAE_DCR_DIP |            \
 319                   HPB_DMAE_DCR_SPDS_32BIT |     \
 320                   HPB_DMAE_DCR_DMDL |           \
 321                   HPB_DMAE_DCR_DPDS_32BIT,      \
 322         .port   = _id + (_id << 8),             \
 323         .dma_ch = (28 + _id),                   \
 324 }, {                                            \
 325         .id     = HPBDMA_SLAVE_SSI## _id ##_RX, \
 326         .addr   = 0xffd9100c + (_id * 0x40),    \
 327         .dcr    = HPB_DMAE_DCR_CT |             \
 328                   HPB_DMAE_DCR_DIP |            \
 329                   HPB_DMAE_DCR_SMDL |           \
 330                   HPB_DMAE_DCR_SPDS_32BIT |     \
 331                   HPB_DMAE_DCR_DPDS_32BIT,      \
 332         .port   = _id + (_id << 8),             \
 333         .dma_ch = (28 + _id),                   \
 334 }
 335
 336 #define HPBDMA_HPBIF(_id)                               \
 337 {                                                       \
 338         .id     = HPBDMA_SLAVE_HPBIF## _id ##_TX,       \
 339         .addr   = 0xffda0000 + (_id * 0x1000),          \
 340         .dcr    = HPB_DMAE_DCR_CT |                     \
 341                   HPB_DMAE_DCR_DIP |                    \
 342                   HPB_DMAE_DCR_SPDS_32BIT |             \
 343                   HPB_DMAE_DCR_DMDL |                   \
 344                   HPB_DMAE_DCR_DPDS_32BIT,              \
 345         .port   = 0x1111,                               \
 346         .dma_ch = (28 + _id),                           \
 347 }, {                                                    \
 348         .id     = HPBDMA_SLAVE_HPBIF## _id ##_RX,       \
 349         .addr   = 0xffda0000 + (_id * 0x1000),          \
 350         .dcr    = HPB_DMAE_DCR_CT |                     \
 351                   HPB_DMAE_DCR_DIP |                    \
 352                   HPB_DMAE_DCR_SMDL |                   \
 353                   HPB_DMAE_DCR_SPDS_32BIT |             \
 354                   HPB_DMAE_DCR_DPDS_32BIT,              \
 355         .port   = 0x1111,                               \
 356         .dma_ch = (28 + _id),                           \
 357 }
 358
 359 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
 360         {
 361                 .id     = HPBDMA_SLAVE_SDHI0_TX,
 362                 .addr   = 0xffe4c000 + 0x30,
 363                 .dcr    = HPB_DMAE_DCR_SPDS_16BIT |
 364                           HPB_DMAE_DCR_DMDL |
 365                           HPB_DMAE_DCR_DPDS_16BIT,
 366                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 367                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 368                           HPB_DMAE_ASYNCRSTR_ASRST23,
 369                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD21_MULTI,
 370                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD21_MASK,
 371                 .port   = 0x0D0C,
 372                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 373                 .dma_ch = 21,
 374         }, {
 375                 .id     = HPBDMA_SLAVE_SDHI0_RX,
 376                 .addr   = 0xffe4c000 + 0x30,
 377                 .dcr    = HPB_DMAE_DCR_SMDL |
 378                           HPB_DMAE_DCR_SPDS_16BIT |
 379                           HPB_DMAE_DCR_DPDS_16BIT,
 380                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 381                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 382                           HPB_DMAE_ASYNCRSTR_ASRST23,
 383                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD22_MULTI,
 384                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD22_MASK,
 385                 .port   = 0x0D0C,
 386                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 387                 .dma_ch = 22,
 388         }, {
 389                 .id     = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */
 390                 .addr   = 0xffe60018,
 391                 .dcr    = HPB_DMAE_DCR_SPDS_32BIT |
 392                           HPB_DMAE_DCR_DMDL |
 393                           HPB_DMAE_DCR_DPDS_32BIT,
 394                 .port   = 0x0000,
 395                 .dma_ch = 14,
 396         }, {
 397                 .id     = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */
 398                 .addr   = 0xffe6001c,
 399                 .dcr    = HPB_DMAE_DCR_SMDL |
 400                           HPB_DMAE_DCR_SPDS_32BIT |
 401                           HPB_DMAE_DCR_DPDS_32BIT,
 402                 .port   = 0x0101,
 403                 .dma_ch = 15,
 404         },
 405
 406         HPBDMA_SSI(0),
 407         HPBDMA_SSI(1),
 408         HPBDMA_SSI(2),
 409         HPBDMA_SSI(3),
 410         HPBDMA_SSI(4),
 411         HPBDMA_SSI(5),
 412         HPBDMA_SSI(6),
 413         HPBDMA_SSI(7),
 414         HPBDMA_SSI(8),
 415
 416         HPBDMA_HPBIF(0),
 417         HPBDMA_HPBIF(1),
 418         HPBDMA_HPBIF(2),
 419         HPBDMA_HPBIF(3),
 420         HPBDMA_HPBIF(4),
 421         HPBDMA_HPBIF(5),
 422         HPBDMA_HPBIF(6),
 423         HPBDMA_HPBIF(7),
 424         HPBDMA_HPBIF(8),
 425 };
 426
 427 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
 428         HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */
 429         HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */
 430         HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
 431         HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
 432         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX),   /* ch. 28 */
 433         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX),   /* ch. 28 */
 434         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
 435         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
 436         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX),   /* ch. 29 */
 437         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX),   /* ch. 29 */
 438         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
 439         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
 440         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX),   /* ch. 30 */
 441         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX),   /* ch. 30 */
 442         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
 443         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
 444         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX),   /* ch. 31 */
 445         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX),   /* ch. 31 */
 446         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
 447         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
 448         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX),   /* ch. 32 */
 449         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX),   /* ch. 32 */
 450         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
 451         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
 452         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX),   /* ch. 33 */
 453         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX),   /* ch. 33 */
 454         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
 455         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
 456         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX),   /* ch. 34 */
 457         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX),   /* ch. 34 */
 458         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
 459         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
 460         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX),   /* ch. 35 */
 461         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX),   /* ch. 35 */
 462         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
 463         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
 464         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX),   /* ch. 36 */
 465         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX),   /* ch. 36 */
 466         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
 467         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
 468 };
 469
 470 static struct hpb_dmae_pdata dma_platform_data __initdata = {
 471         .slaves                 = hpb_dmae_slaves,
 472         .num_slaves             = ARRAY_SIZE(hpb_dmae_slaves),
 473         .channels               = hpb_dmae_channels,
 474         .num_channels           = ARRAY_SIZE(hpb_dmae_channels),
 475         .ts_shift               = {
 476                 [XMIT_SZ_8BIT]  = 0,
 477                 [XMIT_SZ_16BIT] = 1,
 478                 [XMIT_SZ_32BIT] = 2,
 479         },
 480         .num_hw_channels        = 39,
 481 };
 482
 483 static struct resource hpb_dmae_resources[] __initdata = {
 484         /* Channel registers */
 485         DEFINE_RES_MEM(0xffc08000, 0x1000),
 486         /* Common registers */
 487         DEFINE_RES_MEM(0xffc09000, 0x170),
 488         /* Asynchronous reset registers */
 489         DEFINE_RES_MEM(0xffc00300, 4),
 490         /* Asynchronous mode registers */
 491         DEFINE_RES_MEM(0xffc00400, 4),
 492         /* IRQ for DMA channels */
 493         DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ),
 494 };
 495
 496 static void __init r8a7778_register_hpb_dmae(void)
 497 {
 498         platform_device_register_resndata(NULL, "hpb-dma-engine",
 499                                           -1, hpb_dmae_resources,
 500                                           ARRAY_SIZE(hpb_dmae_resources),
 501                                           &dma_platform_data,
 502                                           sizeof(dma_platform_data));
 503 }
 504
 505 void __init r8a7778_add_standard_devices(void)
 506 {
 507         r8a7778_add_dt_devices();
 508         r8a7778_register_i2c(0);
 509         r8a7778_register_i2c(1);
 510         r8a7778_register_i2c(2);
 511         r8a7778_register_i2c(3);
 512         r8a7778_register_hspi(0);
 513         r8a7778_register_hspi(1);
 514         r8a7778_register_hspi(2);
 515
 516         r8a7778_register_hpb_dmae();
 517 }
 518
 519 void __init r8a7778_init_late(void)
 520 {
 521         platform_device_register_full(&ehci_info);
 522         platform_device_register_full(&ohci_info);
 523 }
 524
 525 static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
 526         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
 527         .sense_bitfield_width = 2,
 528 };
 529
 530 static struct resource irqpin_resources[] __initdata = {
 531         DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
 532         DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
 533         DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
 534         DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
 535         DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
 536         DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
 537         DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
 538         DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
 539         DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
 540 };
 541
 542 void __init r8a7778_init_irq_extpin_dt(int irlm)
 543 {
 544         void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
 545         unsigned long tmp;
 546
 547         if (!icr0) {
 548                 pr_warn("r8a7778: unable to setup external irq pin mode\n");
 549                 return;
 550         }
 551
 552         tmp = ioread32(icr0);
 553         if (irlm)
 554                 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
 555         else
 556                 tmp &= ~(1 << 23); /* IRL mode - not supported */
 557         tmp |= (1 << 21); /* LVLMODE = 1 */
 558         iowrite32(tmp, icr0);
 559         iounmap(icr0);
 560 }
 561
 562 void __init r8a7778_init_irq_extpin(int irlm)
 563 {
 564         r8a7778_init_irq_extpin_dt(irlm);
 565         if (irlm)
 566                 platform_device_register_resndata(
 567                         NULL, "renesas_intc_irqpin", -1,
 568                         irqpin_resources, ARRAY_SIZE(irqpin_resources),
 569                         &irqpin_platform_data, sizeof(irqpin_platform_data));
 570 }
 571
 572 void __init r8a7778_init_delay(void)
 573 {
 574         shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
 575 }
 576
 577 #ifdef CONFIG_USE_OF
 578 #define INT2SMSKCR0     0x82288 /* 0xfe782288 */
 579 #define INT2SMSKCR1     0x8228c /* 0xfe78228c */
 580
 581 #define INT2NTSR0       0x00018 /* 0xfe700018 */
 582 #define INT2NTSR1       0x0002c /* 0xfe70002c */
 583 void __init r8a7778_init_irq_dt(void)
 584 {
 585         void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
 586
 587         BUG_ON(!base);
 588
 589         irqchip_init();
 590
 591         /* route all interrupts to ARM */
 592         __raw_writel(0x73ffffff, base + INT2NTSR0);
 593         __raw_writel(0xffffffff, base + INT2NTSR1);
 594
 595         /* unmask all known interrupts in INTCS2 */
 596         __raw_writel(0x08330773, base + INT2SMSKCR0);
 597         __raw_writel(0x00311110, base + INT2SMSKCR1);
 598
 599         iounmap(base);
 600 }
 601
 602 static const char *r8a7778_compat_dt[] __initdata = {
 603         "renesas,r8a7778",
 604         NULL,
 605 };
 606
 607 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
 608         .init_early     = r8a7778_init_delay,
 609         .init_irq       = r8a7778_init_irq_dt,
 610         .dt_compat      = r8a7778_compat_dt,
 611         .init_late      = r8a7778_init_late,
 612 MACHINE_END
 613
 614 #endif /* CONFIG_USE_OF */