arch/arm/mach-shmobile/setup-r8a7779.c

   1 /*
   2  * r8a7779 processor support
   3  *
   4  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqchip.h>
  22 #include <linux/irqchip/arm-gic.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_data/dma-rcar-hpbdma.h>
  25 #include <linux/platform_data/gpio-rcar.h>
  26 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/delay.h>
  29 #include <linux/input.h>
  30 #include <linux/io.h>
  31 #include <linux/serial_sci.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/usb/otg.h>
  35 #include <linux/usb/hcd.h>
  36 #include <linux/usb/ehci_pdriver.h>
  37 #include <linux/usb/ohci_pdriver.h>
  38 #include <linux/pm_runtime.h>
  39
  40 #include <asm/mach-types.h>
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/time.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/hardware/cache-l2x0.h>
  45
  46 #include "common.h"
  47 #include "irqs.h"
  48 #include "r8a7779.h"
  49
  50 static struct map_desc r8a7779_io_desc[] __initdata = {
  51         /* 2M entity map for 0xf0000000 (MPCORE) */
  52         {
  53                 .virtual        = 0xf0000000,
  54                 .pfn            = __phys_to_pfn(0xf0000000),
  55                 .length         = SZ_2M,
  56                 .type           = MT_DEVICE_NONSHARED
  57         },
  58         /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
  59         {
  60                 .virtual        = 0xfe000000,
  61                 .pfn            = __phys_to_pfn(0xfe000000),
  62                 .length         = SZ_16M,
  63                 .type           = MT_DEVICE_NONSHARED
  64         },
  65 };
  66
  67 void __init r8a7779_map_io(void)
  68 {
  69         iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
  70 }
  71
  72 /* IRQ */
  73 #define INT2SMSKCR0 IOMEM(0xfe7822a0)
  74 #define INT2SMSKCR1 IOMEM(0xfe7822a4)
  75 #define INT2SMSKCR2 IOMEM(0xfe7822a8)
  76 #define INT2SMSKCR3 IOMEM(0xfe7822ac)
  77 #define INT2SMSKCR4 IOMEM(0xfe7822b0)
  78
  79 #define INT2NTSR0 IOMEM(0xfe700060)
  80 #define INT2NTSR1 IOMEM(0xfe700064)
  81
  82 static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
  83         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
  84         .sense_bitfield_width = 2,
  85 };
  86
  87 static struct resource irqpin0_resources[] __initdata = {
  88         DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
  89         DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
  90         DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
  91         DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
  92         DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
  93         DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
  94         DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
  95         DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
  96         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
  97 };
  98
  99 void __init r8a7779_init_irq_extpin_dt(int irlm)
 100 {
 101         void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
 102         u32 tmp;
 103
 104         if (!icr0) {
 105                 pr_warn("r8a7779: unable to setup external irq pin mode\n");
 106                 return;
 107         }
 108
 109         tmp = ioread32(icr0);
 110         if (irlm)
 111                 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
 112         else
 113                 tmp &= ~(1 << 23); /* IRL mode - not supported */
 114         tmp |= (1 << 21); /* LVLMODE = 1 */
 115         iowrite32(tmp, icr0);
 116         iounmap(icr0);
 117 }
 118
 119 void __init r8a7779_init_irq_extpin(int irlm)
 120 {
 121         r8a7779_init_irq_extpin_dt(irlm);
 122         if (irlm)
 123                 platform_device_register_resndata(
 124                         NULL, "renesas_intc_irqpin", -1,
 125                         irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
 126                         &irqpin0_platform_data, sizeof(irqpin0_platform_data));
 127 }
 128
 129 /* PFC/GPIO */
 130 static struct resource r8a7779_pfc_resources[] = {
 131         DEFINE_RES_MEM(0xfffc0000, 0x023c),
 132 };
 133
 134 static struct platform_device r8a7779_pfc_device = {
 135         .name           = "pfc-r8a7779",
 136         .id             = -1,
 137         .resource       = r8a7779_pfc_resources,
 138         .num_resources  = ARRAY_SIZE(r8a7779_pfc_resources),
 139 };
 140
 141 #define R8A7779_GPIO(idx, npins) \
 142 static struct resource r8a7779_gpio##idx##_resources[] = {              \
 143         DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),          \
 144         DEFINE_RES_IRQ(gic_iid(0xad + (idx))),                          \
 145 };                                                                      \
 146                                                                         \
 147 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {    \
 148         .gpio_base      = 32 * (idx),                                   \
 149         .irq_base       = 0,                                            \
 150         .number_of_pins = npins,                                        \
 151         .pctl_name      = "pfc-r8a7779",                                \
 152 };                                                                      \
 153                                                                         \
 154 static struct platform_device r8a7779_gpio##idx##_device = {            \
 155         .name           = "gpio_rcar",                                  \
 156         .id             = idx,                                          \
 157         .resource       = r8a7779_gpio##idx##_resources,                \
 158         .num_resources  = ARRAY_SIZE(r8a7779_gpio##idx##_resources),    \
 159         .dev            = {                                             \
 160                 .platform_data  = &r8a7779_gpio##idx##_platform_data,   \
 161         },                                                              \
 162 }
 163
 164 R8A7779_GPIO(0, 32);
 165 R8A7779_GPIO(1, 32);
 166 R8A7779_GPIO(2, 32);
 167 R8A7779_GPIO(3, 32);
 168 R8A7779_GPIO(4, 32);
 169 R8A7779_GPIO(5, 32);
 170 R8A7779_GPIO(6, 9);
 171
 172 static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
 173         &r8a7779_pfc_device,
 174         &r8a7779_gpio0_device,
 175         &r8a7779_gpio1_device,
 176         &r8a7779_gpio2_device,
 177         &r8a7779_gpio3_device,
 178         &r8a7779_gpio4_device,
 179         &r8a7779_gpio5_device,
 180         &r8a7779_gpio6_device,
 181 };
 182
 183 void __init r8a7779_pinmux_init(void)
 184 {
 185         platform_add_devices(r8a7779_pinctrl_devices,
 186                             ARRAY_SIZE(r8a7779_pinctrl_devices));
 187 }
 188
 189 /* SCIF */
 190 #define R8A7779_SCIF(index, baseaddr, irq)                      \
 191 static struct plat_sci_port scif##index##_platform_data = {     \
 192         .type           = PORT_SCIF,                            \
 193         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
 194         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,     \
 195 };                                                              \
 196                                                                 \
 197 static struct resource scif##index##_resources[] = {            \
 198         DEFINE_RES_MEM(baseaddr, 0x100),                        \
 199         DEFINE_RES_IRQ(irq),                                    \
 200 };                                                              \
 201                                                                 \
 202 static struct platform_device scif##index##_device = {          \
 203         .name           = "sh-sci",                             \
 204         .id             = index,                                \
 205         .resource       = scif##index##_resources,              \
 206         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 207         .dev            = {                                     \
 208                 .platform_data  = &scif##index##_platform_data, \
 209         },                                                      \
 210 }
 211
 212 R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
 213 R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
 214 R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
 215 R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
 216 R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
 217 R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
 218
 219 /* TMU */
 220 static struct sh_timer_config tmu0_platform_data = {
 221         .channels_mask = 7,
 222 };
 223
 224 static struct resource tmu0_resources[] = {
 225         DEFINE_RES_MEM(0xffd80000, 0x30),
 226         DEFINE_RES_IRQ(gic_iid(0x40)),
 227         DEFINE_RES_IRQ(gic_iid(0x41)),
 228         DEFINE_RES_IRQ(gic_iid(0x42)),
 229 };
 230
 231 static struct platform_device tmu0_device = {
 232         .name           = "sh-tmu",
 233         .id             = 0,
 234         .dev = {
 235                 .platform_data  = &tmu0_platform_data,
 236         },
 237         .resource       = tmu0_resources,
 238         .num_resources  = ARRAY_SIZE(tmu0_resources),
 239 };
 240
 241 /* I2C */
 242 static struct resource rcar_i2c0_res[] = {
 243         {
 244                 .start  = 0xffc70000,
 245                 .end    = 0xffc70fff,
 246                 .flags  = IORESOURCE_MEM,
 247         }, {
 248                 .start  = gic_iid(0x6f),
 249                 .flags  = IORESOURCE_IRQ,
 250         },
 251 };
 252
 253 static struct platform_device i2c0_device = {
 254         .name           = "i2c-rcar",
 255         .id             = 0,
 256         .resource       = rcar_i2c0_res,
 257         .num_resources  = ARRAY_SIZE(rcar_i2c0_res),
 258 };
 259
 260 static struct resource rcar_i2c1_res[] = {
 261         {
 262                 .start  = 0xffc71000,
 263                 .end    = 0xffc71fff,
 264                 .flags  = IORESOURCE_MEM,
 265         }, {
 266                 .start  = gic_iid(0x72),
 267                 .flags  = IORESOURCE_IRQ,
 268         },
 269 };
 270
 271 static struct platform_device i2c1_device = {
 272         .name           = "i2c-rcar",
 273         .id             = 1,
 274         .resource       = rcar_i2c1_res,
 275         .num_resources  = ARRAY_SIZE(rcar_i2c1_res),
 276 };
 277
 278 static struct resource rcar_i2c2_res[] = {
 279         {
 280                 .start  = 0xffc72000,
 281                 .end    = 0xffc72fff,
 282                 .flags  = IORESOURCE_MEM,
 283         }, {
 284                 .start  = gic_iid(0x70),
 285                 .flags  = IORESOURCE_IRQ,
 286         },
 287 };
 288
 289 static struct platform_device i2c2_device = {
 290         .name           = "i2c-rcar",
 291         .id             = 2,
 292         .resource       = rcar_i2c2_res,
 293         .num_resources  = ARRAY_SIZE(rcar_i2c2_res),
 294 };
 295
 296 static struct resource rcar_i2c3_res[] = {
 297         {
 298                 .start  = 0xffc73000,
 299                 .end    = 0xffc73fff,
 300                 .flags  = IORESOURCE_MEM,
 301         }, {
 302                 .start  = gic_iid(0x71),
 303                 .flags  = IORESOURCE_IRQ,
 304         },
 305 };
 306
 307 static struct platform_device i2c3_device = {
 308         .name           = "i2c-rcar",
 309         .id             = 3,
 310         .resource       = rcar_i2c3_res,
 311         .num_resources  = ARRAY_SIZE(rcar_i2c3_res),
 312 };
 313
 314 static struct resource sata_resources[] = {
 315         [0] = {
 316                 .name   = "rcar-sata",
 317                 .start  = 0xfc600000,
 318                 .end    = 0xfc601fff,
 319                 .flags  = IORESOURCE_MEM,
 320         },
 321         [1] = {
 322                 .start  = gic_iid(0x84),
 323                 .flags  = IORESOURCE_IRQ,
 324         },
 325 };
 326
 327 static struct platform_device sata_device = {
 328         .name           = "sata_rcar",
 329         .id             = -1,
 330         .resource       = sata_resources,
 331         .num_resources  = ARRAY_SIZE(sata_resources),
 332         .dev            = {
 333                 .dma_mask               = &sata_device.dev.coherent_dma_mask,
 334                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 335         },
 336 };
 337
 338 /* USB */
 339 static struct usb_phy *phy;
 340
 341 static int usb_power_on(struct platform_device *pdev)
 342 {
 343         if (IS_ERR(phy))
 344                 return PTR_ERR(phy);
 345
 346         pm_runtime_enable(&pdev->dev);
 347         pm_runtime_get_sync(&pdev->dev);
 348
 349         usb_phy_init(phy);
 350
 351         return 0;
 352 }
 353
 354 static void usb_power_off(struct platform_device *pdev)
 355 {
 356         if (IS_ERR(phy))
 357                 return;
 358
 359         usb_phy_shutdown(phy);
 360
 361         pm_runtime_put_sync(&pdev->dev);
 362         pm_runtime_disable(&pdev->dev);
 363 }
 364
 365 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
 366 {
 367         /*
 368          * Below are recommended values from the datasheet;
 369          * see [USB :: Setting of EHCI Internal Buffer].
 370          */
 371         /* EHCI IP internal buffer setting */
 372         iowrite32(0x00ff0040, hcd->regs + 0x0094);
 373         /* EHCI IP internal buffer enable */
 374         iowrite32(0x00000001, hcd->regs + 0x009C);
 375
 376         return 0;
 377 }
 378
 379 static struct usb_ehci_pdata ehcix_pdata = {
 380         .power_on       = usb_power_on,
 381         .power_off      = usb_power_off,
 382         .power_suspend  = usb_power_off,
 383         .pre_setup      = ehci_init_internal_buffer,
 384 };
 385
 386 static struct resource ehci0_resources[] = {
 387         [0] = {
 388                 .start  = 0xffe70000,
 389                 .end    = 0xffe70400 - 1,
 390                 .flags  = IORESOURCE_MEM,
 391         },
 392         [1] = {
 393                 .start  = gic_iid(0x4c),
 394                 .flags  = IORESOURCE_IRQ,
 395         },
 396 };
 397
 398 static struct platform_device ehci0_device = {
 399         .name   = "ehci-platform",
 400         .id     = 0,
 401         .dev    = {
 402                 .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
 403                 .coherent_dma_mask      = 0xffffffff,
 404                 .platform_data          = &ehcix_pdata,
 405         },
 406         .num_resources  = ARRAY_SIZE(ehci0_resources),
 407         .resource       = ehci0_resources,
 408 };
 409
 410 static struct resource ehci1_resources[] = {
 411         [0] = {
 412                 .start  = 0xfff70000,
 413                 .end    = 0xfff70400 - 1,
 414                 .flags  = IORESOURCE_MEM,
 415         },
 416         [1] = {
 417                 .start  = gic_iid(0x4d),
 418                 .flags  = IORESOURCE_IRQ,
 419         },
 420 };
 421
 422 static struct platform_device ehci1_device = {
 423         .name   = "ehci-platform",
 424         .id     = 1,
 425         .dev    = {
 426                 .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
 427                 .coherent_dma_mask      = 0xffffffff,
 428                 .platform_data          = &ehcix_pdata,
 429         },
 430         .num_resources  = ARRAY_SIZE(ehci1_resources),
 431         .resource       = ehci1_resources,
 432 };
 433
 434 static struct usb_ohci_pdata ohcix_pdata = {
 435         .power_on       = usb_power_on,
 436         .power_off      = usb_power_off,
 437         .power_suspend  = usb_power_off,
 438 };
 439
 440 static struct resource ohci0_resources[] = {
 441         [0] = {
 442                 .start  = 0xffe70400,
 443                 .end    = 0xffe70800 - 1,
 444                 .flags  = IORESOURCE_MEM,
 445         },
 446         [1] = {
 447                 .start  = gic_iid(0x4c),
 448                 .flags  = IORESOURCE_IRQ,
 449         },
 450 };
 451
 452 static struct platform_device ohci0_device = {
 453         .name   = "ohci-platform",
 454         .id     = 0,
 455         .dev    = {
 456                 .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
 457                 .coherent_dma_mask      = 0xffffffff,
 458                 .platform_data          = &ohcix_pdata,
 459         },
 460         .num_resources  = ARRAY_SIZE(ohci0_resources),
 461         .resource       = ohci0_resources,
 462 };
 463
 464 static struct resource ohci1_resources[] = {
 465         [0] = {
 466                 .start  = 0xfff70400,
 467                 .end    = 0xfff70800 - 1,
 468                 .flags  = IORESOURCE_MEM,
 469         },
 470         [1] = {
 471                 .start  = gic_iid(0x4d),
 472                 .flags  = IORESOURCE_IRQ,
 473         },
 474 };
 475
 476 static struct platform_device ohci1_device = {
 477         .name   = "ohci-platform",
 478         .id     = 1,
 479         .dev    = {
 480                 .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
 481                 .coherent_dma_mask      = 0xffffffff,
 482                 .platform_data          = &ohcix_pdata,
 483         },
 484         .num_resources  = ARRAY_SIZE(ohci1_resources),
 485         .resource       = ohci1_resources,
 486 };
 487
 488 /* HPB-DMA */
 489
 490 /* Asynchronous mode register bits */
 491 #define HPB_DMAE_ASYNCMDR_ASMD43_MASK           BIT(23) /* MMC1 */
 492 #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE         BIT(23) /* MMC1 */
 493 #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI          0       /* MMC1 */
 494 #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK         BIT(22) /* MMC1 */
 495 #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST        BIT(22) /* MMC1 */
 496 #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST       0       /* MMC1 */
 497 #define HPB_DMAE_ASYNCMDR_ASMD24_MASK           BIT(21) /* MMC0 */
 498 #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE         BIT(21) /* MMC0 */
 499 #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI          0       /* MMC0 */
 500 #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK         BIT(20) /* MMC0 */
 501 #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST        BIT(20) /* MMC0 */
 502 #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST       0       /* MMC0 */
 503 #define HPB_DMAE_ASYNCMDR_ASMD41_MASK           BIT(19) /* SDHI3 */
 504 #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE         BIT(19) /* SDHI3 */
 505 #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI          0       /* SDHI3 */
 506 #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK         BIT(18) /* SDHI3 */
 507 #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST        BIT(18) /* SDHI3 */
 508 #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST       0       /* SDHI3 */
 509 #define HPB_DMAE_ASYNCMDR_ASMD40_MASK           BIT(17) /* SDHI3 */
 510 #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE         BIT(17) /* SDHI3 */
 511 #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI          0       /* SDHI3 */
 512 #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK         BIT(16) /* SDHI3 */
 513 #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST        BIT(16) /* SDHI3 */
 514 #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST       0       /* SDHI3 */
 515 #define HPB_DMAE_ASYNCMDR_ASMD39_MASK           BIT(15) /* SDHI3 */
 516 #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE         BIT(15) /* SDHI3 */
 517 #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI          0       /* SDHI3 */
 518 #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK         BIT(14) /* SDHI3 */
 519 #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST        BIT(14) /* SDHI3 */
 520 #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST       0       /* SDHI3 */
 521 #define HPB_DMAE_ASYNCMDR_ASMD27_MASK           BIT(13) /* SDHI2 */
 522 #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE         BIT(13) /* SDHI2 */
 523 #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI          0       /* SDHI2 */
 524 #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK         BIT(12) /* SDHI2 */
 525 #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST        BIT(12) /* SDHI2 */
 526 #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST       0       /* SDHI2 */
 527 #define HPB_DMAE_ASYNCMDR_ASMD26_MASK           BIT(11) /* SDHI2 */
 528 #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE         BIT(11) /* SDHI2 */
 529 #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI          0       /* SDHI2 */
 530 #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK         BIT(10) /* SDHI2 */
 531 #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST        BIT(10) /* SDHI2 */
 532 #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST       0       /* SDHI2 */
 533 #define HPB_DMAE_ASYNCMDR_ASMD25_MASK           BIT(9)  /* SDHI2 */
 534 #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE         BIT(9)  /* SDHI2 */
 535 #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI          0       /* SDHI2 */
 536 #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK         BIT(8)  /* SDHI2 */
 537 #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST        BIT(8)  /* SDHI2 */
 538 #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST       0       /* SDHI2 */
 539 #define HPB_DMAE_ASYNCMDR_ASMD23_MASK           BIT(7)  /* SDHI0 */
 540 #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE         BIT(7)  /* SDHI0 */
 541 #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI          0       /* SDHI0 */
 542 #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK         BIT(6)  /* SDHI0 */
 543 #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST        BIT(6)  /* SDHI0 */
 544 #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST       0       /* SDHI0 */
 545 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK           BIT(5)  /* SDHI0 */
 546 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE         BIT(5)  /* SDHI0 */
 547 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI          0       /* SDHI0 */
 548 #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK         BIT(4)  /* SDHI0 */
 549 #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST        BIT(4)  /* SDHI0 */
 550 #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST       0       /* SDHI0 */
 551 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK           BIT(3)  /* SDHI0 */
 552 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE         BIT(3)  /* SDHI0 */
 553 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI          0       /* SDHI0 */
 554 #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK         BIT(2)  /* SDHI0 */
 555 #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST        BIT(2)  /* SDHI0 */
 556 #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST       0       /* SDHI0 */
 557 #define HPB_DMAE_ASYNCMDR_ASMD20_MASK           BIT(1)  /* SDHI1 */
 558 #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE         BIT(1)  /* SDHI1 */
 559 #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI          0       /* SDHI1 */
 560 #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK         BIT(0)  /* SDHI1 */
 561 #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST        BIT(0)  /* SDHI1 */
 562 #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST       0       /* SDHI1 */
 563
 564 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
 565         {
 566                 .id     = HPBDMA_SLAVE_SDHI0_TX,
 567                 .addr   = 0xffe4c000 + 0x30,
 568                 .dcr    = HPB_DMAE_DCR_SPDS_16BIT |
 569                           HPB_DMAE_DCR_DMDL |
 570                           HPB_DMAE_DCR_DPDS_16BIT,
 571                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 572                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 573                           HPB_DMAE_ASYNCRSTR_ASRST23,
 574                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
 575                           HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
 576                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
 577                           HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
 578                 .port   = 0x0D0C,
 579                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 580                 .dma_ch = 21,
 581         }, {
 582                 .id     = HPBDMA_SLAVE_SDHI0_RX,
 583                 .addr   = 0xffe4c000 + 0x30,
 584                 .dcr    = HPB_DMAE_DCR_SMDL |
 585                           HPB_DMAE_DCR_SPDS_16BIT |
 586                           HPB_DMAE_DCR_DPDS_16BIT,
 587                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 588                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 589                           HPB_DMAE_ASYNCRSTR_ASRST23,
 590                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
 591                           HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
 592                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
 593                           HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
 594                 .port   = 0x0D0C,
 595                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 596                 .dma_ch = 22,
 597         },
 598 };
 599
 600 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
 601         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
 602         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
 603 };
 604
 605 static struct hpb_dmae_pdata dma_platform_data __initdata = {
 606         .slaves                 = hpb_dmae_slaves,
 607         .num_slaves             = ARRAY_SIZE(hpb_dmae_slaves),
 608         .channels               = hpb_dmae_channels,
 609         .num_channels           = ARRAY_SIZE(hpb_dmae_channels),
 610         .ts_shift               = {
 611                 [XMIT_SZ_8BIT]  = 0,
 612                 [XMIT_SZ_16BIT] = 1,
 613                 [XMIT_SZ_32BIT] = 2,
 614         },
 615         .num_hw_channels        = 44,
 616 };
 617
 618 static struct resource hpb_dmae_resources[] __initdata = {
 619         /* Channel registers */
 620         DEFINE_RES_MEM(0xffc08000, 0x1000),
 621         /* Common registers */
 622         DEFINE_RES_MEM(0xffc09000, 0x170),
 623         /* Asynchronous reset registers */
 624         DEFINE_RES_MEM(0xffc00300, 4),
 625         /* Asynchronous mode registers */
 626         DEFINE_RES_MEM(0xffc00400, 4),
 627         /* IRQ for DMA channels */
 628         DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
 629 };
 630
 631 static void __init r8a7779_register_hpb_dmae(void)
 632 {
 633         platform_device_register_resndata(NULL, "hpb-dma-engine",
 634                                           -1, hpb_dmae_resources,
 635                                           ARRAY_SIZE(hpb_dmae_resources),
 636                                           &dma_platform_data,
 637                                           sizeof(dma_platform_data));
 638 }
 639
 640 static struct platform_device *r8a7779_early_devices[] __initdata = {
 641         &tmu0_device,
 642 };
 643
 644 static struct platform_device *r8a7779_standard_devices[] __initdata = {
 645         &scif0_device,
 646         &scif1_device,
 647         &scif2_device,
 648         &scif3_device,
 649         &scif4_device,
 650         &scif5_device,
 651         &i2c0_device,
 652         &i2c1_device,
 653         &i2c2_device,
 654         &i2c3_device,
 655         &sata_device,
 656 };
 657
 658 void __init r8a7779_add_standard_devices(void)
 659 {
 660 #ifdef CONFIG_CACHE_L2X0
 661         /* Shared attribute override enable, 64K*16way */
 662         l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
 663 #endif
 664         r8a7779_pm_init();
 665
 666         r8a7779_init_pm_domains();
 667
 668         platform_add_devices(r8a7779_early_devices,
 669                             ARRAY_SIZE(r8a7779_early_devices));
 670         platform_add_devices(r8a7779_standard_devices,
 671                             ARRAY_SIZE(r8a7779_standard_devices));
 672         r8a7779_register_hpb_dmae();
 673 }
 674
 675 void __init r8a7779_add_early_devices(void)
 676 {
 677         early_platform_add_devices(r8a7779_early_devices,
 678                                    ARRAY_SIZE(r8a7779_early_devices));
 679
 680         /* Early serial console setup is not included here due to
 681          * memory map collisions. The SCIF serial ports in r8a7779
 682          * are difficult to entity map 1:1 due to collision with the
 683          * virtual memory range used by the coherent DMA code on ARM.
 684          *
 685          * Anyone wanting to debug early can remove UPF_IOREMAP from
 686          * the sh-sci serial console platform data, adjust mapbase
 687          * to a static M:N virt:phys mapping that needs to be added to
 688          * the mappings passed with iotable_init() above.
 689          *
 690          * Then add a call to shmobile_setup_console() from this function.
 691          *
 692          * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
 693          * command line in case of the marzen board.
 694          */
 695 }
 696
 697 static struct platform_device *r8a7779_late_devices[] __initdata = {
 698         &ehci0_device,
 699         &ehci1_device,
 700         &ohci0_device,
 701         &ohci1_device,
 702 };
 703
 704 void __init r8a7779_init_late(void)
 705 {
 706         /* get USB PHY */
 707         phy = usb_get_phy(USB_PHY_TYPE_USB2);
 708
 709         shmobile_init_late();
 710         platform_add_devices(r8a7779_late_devices,
 711                              ARRAY_SIZE(r8a7779_late_devices));
 712 }
 713
 714 #ifdef CONFIG_USE_OF
 715 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 716 {
 717         return 0; /* always allow wakeup */
 718 }
 719
 720 void __init r8a7779_init_irq_dt(void)
 721 {
 722         gic_arch_extn.irq_set_wake = r8a7779_set_wake;
 723
 724         irqchip_init();
 725
 726         /* route all interrupts to ARM */
 727         __raw_writel(0xffffffff, INT2NTSR0);
 728         __raw_writel(0x3fffffff, INT2NTSR1);
 729
 730         /* unmask all known interrupts in INTCS2 */
 731         __raw_writel(0xfffffff0, INT2SMSKCR0);
 732         __raw_writel(0xfff7ffff, INT2SMSKCR1);
 733         __raw_writel(0xfffbffdf, INT2SMSKCR2);
 734         __raw_writel(0xbffffffc, INT2SMSKCR3);
 735         __raw_writel(0x003fee3f, INT2SMSKCR4);
 736 }
 737
 738 #define MODEMR          0xffcc0020
 739
 740 u32 __init r8a7779_read_mode_pins(void)
 741 {
 742         static u32 mode;
 743         static bool mode_valid;
 744
 745         if (!mode_valid) {
 746                 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
 747                 BUG_ON(!modemr);
 748                 mode = ioread32(modemr);
 749                 iounmap(modemr);
 750                 mode_valid = true;
 751         }
 752
 753         return mode;
 754 }
 755
 756 static const char *r8a7779_compat_dt[] __initdata = {
 757         "renesas,r8a7779",
 758         NULL,
 759 };
 760
 761 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
 762         .map_io         = r8a7779_map_io,
 763         .init_early     = shmobile_init_delay,
 764         .init_irq       = r8a7779_init_irq_dt,
 765         .init_late      = shmobile_init_late,
 766         .dt_compat      = r8a7779_compat_dt,
 767 MACHINE_END
 768 #endif /* CONFIG_USE_OF */