arch/arm/mach-shmobile/setup-r8a7779.c

   1 /*
   2  * r8a7779 processor support
   3  *
   4  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/irqchip.h>
  26 #include <linux/irqchip/arm-gic.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_data/dma-rcar-hpbdma.h>
  29 #include <linux/platform_data/gpio-rcar.h>
  30 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/delay.h>
  33 #include <linux/input.h>
  34 #include <linux/io.h>
  35 #include <linux/serial_sci.h>
  36 #include <linux/sh_timer.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/usb/otg.h>
  39 #include <linux/usb/hcd.h>
  40 #include <linux/usb/ehci_pdriver.h>
  41 #include <linux/usb/ohci_pdriver.h>
  42 #include <linux/pm_runtime.h>
  43
  44 #include <asm/mach-types.h>
  45 #include <asm/mach/arch.h>
  46 #include <asm/mach/time.h>
  47 #include <asm/mach/map.h>
  48 #include <asm/hardware/cache-l2x0.h>
  49
  50 #include "common.h"
  51 #include "irqs.h"
  52 #include "r8a7779.h"
  53
  54 static struct map_desc r8a7779_io_desc[] __initdata = {
  55         /* 2M entity map for 0xf0000000 (MPCORE) */
  56         {
  57                 .virtual        = 0xf0000000,
  58                 .pfn            = __phys_to_pfn(0xf0000000),
  59                 .length         = SZ_2M,
  60                 .type           = MT_DEVICE_NONSHARED
  61         },
  62         /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
  63         {
  64                 .virtual        = 0xfe000000,
  65                 .pfn            = __phys_to_pfn(0xfe000000),
  66                 .length         = SZ_16M,
  67                 .type           = MT_DEVICE_NONSHARED
  68         },
  69 };
  70
  71 void __init r8a7779_map_io(void)
  72 {
  73         debug_ll_io_init();
  74         iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
  75 }
  76
  77 /* IRQ */
  78 #define INT2SMSKCR0 IOMEM(0xfe7822a0)
  79 #define INT2SMSKCR1 IOMEM(0xfe7822a4)
  80 #define INT2SMSKCR2 IOMEM(0xfe7822a8)
  81 #define INT2SMSKCR3 IOMEM(0xfe7822ac)
  82 #define INT2SMSKCR4 IOMEM(0xfe7822b0)
  83
  84 #define INT2NTSR0 IOMEM(0xfe700060)
  85 #define INT2NTSR1 IOMEM(0xfe700064)
  86
  87 static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
  88         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
  89         .sense_bitfield_width = 2,
  90 };
  91
  92 static struct resource irqpin0_resources[] __initdata = {
  93         DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
  94         DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
  95         DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
  96         DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
  97         DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
  98         DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
  99         DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
 100         DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
 101         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
 102 };
 103
 104 void __init r8a7779_init_irq_extpin_dt(int irlm)
 105 {
 106         void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
 107         u32 tmp;
 108
 109         if (!icr0) {
 110                 pr_warn("r8a7779: unable to setup external irq pin mode\n");
 111                 return;
 112         }
 113
 114         tmp = ioread32(icr0);
 115         if (irlm)
 116                 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
 117         else
 118                 tmp &= ~(1 << 23); /* IRL mode - not supported */
 119         tmp |= (1 << 21); /* LVLMODE = 1 */
 120         iowrite32(tmp, icr0);
 121         iounmap(icr0);
 122 }
 123
 124 void __init r8a7779_init_irq_extpin(int irlm)
 125 {
 126         r8a7779_init_irq_extpin_dt(irlm);
 127         if (irlm)
 128                 platform_device_register_resndata(
 129                         NULL, "renesas_intc_irqpin", -1,
 130                         irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
 131                         &irqpin0_platform_data, sizeof(irqpin0_platform_data));
 132 }
 133
 134 /* PFC/GPIO */
 135 static struct resource r8a7779_pfc_resources[] = {
 136         DEFINE_RES_MEM(0xfffc0000, 0x023c),
 137 };
 138
 139 static struct platform_device r8a7779_pfc_device = {
 140         .name           = "pfc-r8a7779",
 141         .id             = -1,
 142         .resource       = r8a7779_pfc_resources,
 143         .num_resources  = ARRAY_SIZE(r8a7779_pfc_resources),
 144 };
 145
 146 #define R8A7779_GPIO(idx, npins) \
 147 static struct resource r8a7779_gpio##idx##_resources[] = {              \
 148         DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),          \
 149         DEFINE_RES_IRQ(gic_iid(0xad + (idx))),                          \
 150 };                                                                      \
 151                                                                         \
 152 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {    \
 153         .gpio_base      = 32 * (idx),                                   \
 154         .irq_base       = 0,                                            \
 155         .number_of_pins = npins,                                        \
 156         .pctl_name      = "pfc-r8a7779",                                \
 157 };                                                                      \
 158                                                                         \
 159 static struct platform_device r8a7779_gpio##idx##_device = {            \
 160         .name           = "gpio_rcar",                                  \
 161         .id             = idx,                                          \
 162         .resource       = r8a7779_gpio##idx##_resources,                \
 163         .num_resources  = ARRAY_SIZE(r8a7779_gpio##idx##_resources),    \
 164         .dev            = {                                             \
 165                 .platform_data  = &r8a7779_gpio##idx##_platform_data,   \
 166         },                                                              \
 167 }
 168
 169 R8A7779_GPIO(0, 32);
 170 R8A7779_GPIO(1, 32);
 171 R8A7779_GPIO(2, 32);
 172 R8A7779_GPIO(3, 32);
 173 R8A7779_GPIO(4, 32);
 174 R8A7779_GPIO(5, 32);
 175 R8A7779_GPIO(6, 9);
 176
 177 static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
 178         &r8a7779_pfc_device,
 179         &r8a7779_gpio0_device,
 180         &r8a7779_gpio1_device,
 181         &r8a7779_gpio2_device,
 182         &r8a7779_gpio3_device,
 183         &r8a7779_gpio4_device,
 184         &r8a7779_gpio5_device,
 185         &r8a7779_gpio6_device,
 186 };
 187
 188 void __init r8a7779_pinmux_init(void)
 189 {
 190         platform_add_devices(r8a7779_pinctrl_devices,
 191                             ARRAY_SIZE(r8a7779_pinctrl_devices));
 192 }
 193
 194 /* SCIF */
 195 #define R8A7779_SCIF(index, baseaddr, irq)                      \
 196 static struct plat_sci_port scif##index##_platform_data = {     \
 197         .type           = PORT_SCIF,                            \
 198         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
 199         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,     \
 200 };                                                              \
 201                                                                 \
 202 static struct resource scif##index##_resources[] = {            \
 203         DEFINE_RES_MEM(baseaddr, 0x100),                        \
 204         DEFINE_RES_IRQ(irq),                                    \
 205 };                                                              \
 206                                                                 \
 207 static struct platform_device scif##index##_device = {          \
 208         .name           = "sh-sci",                             \
 209         .id             = index,                                \
 210         .resource       = scif##index##_resources,              \
 211         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 212         .dev            = {                                     \
 213                 .platform_data  = &scif##index##_platform_data, \
 214         },                                                      \
 215 }
 216
 217 R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
 218 R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
 219 R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
 220 R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
 221 R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
 222 R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
 223
 224 /* TMU */
 225 static struct sh_timer_config tmu0_platform_data = {
 226         .channels_mask = 7,
 227 };
 228
 229 static struct resource tmu0_resources[] = {
 230         DEFINE_RES_MEM(0xffd80000, 0x30),
 231         DEFINE_RES_IRQ(gic_iid(0x40)),
 232         DEFINE_RES_IRQ(gic_iid(0x41)),
 233         DEFINE_RES_IRQ(gic_iid(0x42)),
 234 };
 235
 236 static struct platform_device tmu0_device = {
 237         .name           = "sh-tmu",
 238         .id             = 0,
 239         .dev = {
 240                 .platform_data  = &tmu0_platform_data,
 241         },
 242         .resource       = tmu0_resources,
 243         .num_resources  = ARRAY_SIZE(tmu0_resources),
 244 };
 245
 246 /* I2C */
 247 static struct resource rcar_i2c0_res[] = {
 248         {
 249                 .start  = 0xffc70000,
 250                 .end    = 0xffc70fff,
 251                 .flags  = IORESOURCE_MEM,
 252         }, {
 253                 .start  = gic_iid(0x6f),
 254                 .flags  = IORESOURCE_IRQ,
 255         },
 256 };
 257
 258 static struct platform_device i2c0_device = {
 259         .name           = "i2c-rcar",
 260         .id             = 0,
 261         .resource       = rcar_i2c0_res,
 262         .num_resources  = ARRAY_SIZE(rcar_i2c0_res),
 263 };
 264
 265 static struct resource rcar_i2c1_res[] = {
 266         {
 267                 .start  = 0xffc71000,
 268                 .end    = 0xffc71fff,
 269                 .flags  = IORESOURCE_MEM,
 270         }, {
 271                 .start  = gic_iid(0x72),
 272                 .flags  = IORESOURCE_IRQ,
 273         },
 274 };
 275
 276 static struct platform_device i2c1_device = {
 277         .name           = "i2c-rcar",
 278         .id             = 1,
 279         .resource       = rcar_i2c1_res,
 280         .num_resources  = ARRAY_SIZE(rcar_i2c1_res),
 281 };
 282
 283 static struct resource rcar_i2c2_res[] = {
 284         {
 285                 .start  = 0xffc72000,
 286                 .end    = 0xffc72fff,
 287                 .flags  = IORESOURCE_MEM,
 288         }, {
 289                 .start  = gic_iid(0x70),
 290                 .flags  = IORESOURCE_IRQ,
 291         },
 292 };
 293
 294 static struct platform_device i2c2_device = {
 295         .name           = "i2c-rcar",
 296         .id             = 2,
 297         .resource       = rcar_i2c2_res,
 298         .num_resources  = ARRAY_SIZE(rcar_i2c2_res),
 299 };
 300
 301 static struct resource rcar_i2c3_res[] = {
 302         {
 303                 .start  = 0xffc73000,
 304                 .end    = 0xffc73fff,
 305                 .flags  = IORESOURCE_MEM,
 306         }, {
 307                 .start  = gic_iid(0x71),
 308                 .flags  = IORESOURCE_IRQ,
 309         },
 310 };
 311
 312 static struct platform_device i2c3_device = {
 313         .name           = "i2c-rcar",
 314         .id             = 3,
 315         .resource       = rcar_i2c3_res,
 316         .num_resources  = ARRAY_SIZE(rcar_i2c3_res),
 317 };
 318
 319 static struct resource sata_resources[] = {
 320         [0] = {
 321                 .name   = "rcar-sata",
 322                 .start  = 0xfc600000,
 323                 .end    = 0xfc601fff,
 324                 .flags  = IORESOURCE_MEM,
 325         },
 326         [1] = {
 327                 .start  = gic_iid(0x84),
 328                 .flags  = IORESOURCE_IRQ,
 329         },
 330 };
 331
 332 static struct platform_device sata_device = {
 333         .name           = "sata_rcar",
 334         .id             = -1,
 335         .resource       = sata_resources,
 336         .num_resources  = ARRAY_SIZE(sata_resources),
 337         .dev            = {
 338                 .dma_mask               = &sata_device.dev.coherent_dma_mask,
 339                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 340         },
 341 };
 342
 343 /* USB */
 344 static struct usb_phy *phy;
 345
 346 static int usb_power_on(struct platform_device *pdev)
 347 {
 348         if (IS_ERR(phy))
 349                 return PTR_ERR(phy);
 350
 351         pm_runtime_enable(&pdev->dev);
 352         pm_runtime_get_sync(&pdev->dev);
 353
 354         usb_phy_init(phy);
 355
 356         return 0;
 357 }
 358
 359 static void usb_power_off(struct platform_device *pdev)
 360 {
 361         if (IS_ERR(phy))
 362                 return;
 363
 364         usb_phy_shutdown(phy);
 365
 366         pm_runtime_put_sync(&pdev->dev);
 367         pm_runtime_disable(&pdev->dev);
 368 }
 369
 370 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
 371 {
 372         /*
 373          * Below are recommended values from the datasheet;
 374          * see [USB :: Setting of EHCI Internal Buffer].
 375          */
 376         /* EHCI IP internal buffer setting */
 377         iowrite32(0x00ff0040, hcd->regs + 0x0094);
 378         /* EHCI IP internal buffer enable */
 379         iowrite32(0x00000001, hcd->regs + 0x009C);
 380
 381         return 0;
 382 }
 383
 384 static struct usb_ehci_pdata ehcix_pdata = {
 385         .power_on       = usb_power_on,
 386         .power_off      = usb_power_off,
 387         .power_suspend  = usb_power_off,
 388         .pre_setup      = ehci_init_internal_buffer,
 389 };
 390
 391 static struct resource ehci0_resources[] = {
 392         [0] = {
 393                 .start  = 0xffe70000,
 394                 .end    = 0xffe70400 - 1,
 395                 .flags  = IORESOURCE_MEM,
 396         },
 397         [1] = {
 398                 .start  = gic_iid(0x4c),
 399                 .flags  = IORESOURCE_IRQ,
 400         },
 401 };
 402
 403 static struct platform_device ehci0_device = {
 404         .name   = "ehci-platform",
 405         .id     = 0,
 406         .dev    = {
 407                 .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
 408                 .coherent_dma_mask      = 0xffffffff,
 409                 .platform_data          = &ehcix_pdata,
 410         },
 411         .num_resources  = ARRAY_SIZE(ehci0_resources),
 412         .resource       = ehci0_resources,
 413 };
 414
 415 static struct resource ehci1_resources[] = {
 416         [0] = {
 417                 .start  = 0xfff70000,
 418                 .end    = 0xfff70400 - 1,
 419                 .flags  = IORESOURCE_MEM,
 420         },
 421         [1] = {
 422                 .start  = gic_iid(0x4d),
 423                 .flags  = IORESOURCE_IRQ,
 424         },
 425 };
 426
 427 static struct platform_device ehci1_device = {
 428         .name   = "ehci-platform",
 429         .id     = 1,
 430         .dev    = {
 431                 .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
 432                 .coherent_dma_mask      = 0xffffffff,
 433                 .platform_data          = &ehcix_pdata,
 434         },
 435         .num_resources  = ARRAY_SIZE(ehci1_resources),
 436         .resource       = ehci1_resources,
 437 };
 438
 439 static struct usb_ohci_pdata ohcix_pdata = {
 440         .power_on       = usb_power_on,
 441         .power_off      = usb_power_off,
 442         .power_suspend  = usb_power_off,
 443 };
 444
 445 static struct resource ohci0_resources[] = {
 446         [0] = {
 447                 .start  = 0xffe70400,
 448                 .end    = 0xffe70800 - 1,
 449                 .flags  = IORESOURCE_MEM,
 450         },
 451         [1] = {
 452                 .start  = gic_iid(0x4c),
 453                 .flags  = IORESOURCE_IRQ,
 454         },
 455 };
 456
 457 static struct platform_device ohci0_device = {
 458         .name   = "ohci-platform",
 459         .id     = 0,
 460         .dev    = {
 461                 .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
 462                 .coherent_dma_mask      = 0xffffffff,
 463                 .platform_data          = &ohcix_pdata,
 464         },
 465         .num_resources  = ARRAY_SIZE(ohci0_resources),
 466         .resource       = ohci0_resources,
 467 };
 468
 469 static struct resource ohci1_resources[] = {
 470         [0] = {
 471                 .start  = 0xfff70400,
 472                 .end    = 0xfff70800 - 1,
 473                 .flags  = IORESOURCE_MEM,
 474         },
 475         [1] = {
 476                 .start  = gic_iid(0x4d),
 477                 .flags  = IORESOURCE_IRQ,
 478         },
 479 };
 480
 481 static struct platform_device ohci1_device = {
 482         .name   = "ohci-platform",
 483         .id     = 1,
 484         .dev    = {
 485                 .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
 486                 .coherent_dma_mask      = 0xffffffff,
 487                 .platform_data          = &ohcix_pdata,
 488         },
 489         .num_resources  = ARRAY_SIZE(ohci1_resources),
 490         .resource       = ohci1_resources,
 491 };
 492
 493 /* HPB-DMA */
 494
 495 /* Asynchronous mode register bits */
 496 #define HPB_DMAE_ASYNCMDR_ASMD43_MASK           BIT(23) /* MMC1 */
 497 #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE         BIT(23) /* MMC1 */
 498 #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI          0       /* MMC1 */
 499 #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK         BIT(22) /* MMC1 */
 500 #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST        BIT(22) /* MMC1 */
 501 #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST       0       /* MMC1 */
 502 #define HPB_DMAE_ASYNCMDR_ASMD24_MASK           BIT(21) /* MMC0 */
 503 #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE         BIT(21) /* MMC0 */
 504 #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI          0       /* MMC0 */
 505 #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK         BIT(20) /* MMC0 */
 506 #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST        BIT(20) /* MMC0 */
 507 #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST       0       /* MMC0 */
 508 #define HPB_DMAE_ASYNCMDR_ASMD41_MASK           BIT(19) /* SDHI3 */
 509 #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE         BIT(19) /* SDHI3 */
 510 #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI          0       /* SDHI3 */
 511 #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK         BIT(18) /* SDHI3 */
 512 #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST        BIT(18) /* SDHI3 */
 513 #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST       0       /* SDHI3 */
 514 #define HPB_DMAE_ASYNCMDR_ASMD40_MASK           BIT(17) /* SDHI3 */
 515 #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE         BIT(17) /* SDHI3 */
 516 #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI          0       /* SDHI3 */
 517 #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK         BIT(16) /* SDHI3 */
 518 #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST        BIT(16) /* SDHI3 */
 519 #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST       0       /* SDHI3 */
 520 #define HPB_DMAE_ASYNCMDR_ASMD39_MASK           BIT(15) /* SDHI3 */
 521 #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE         BIT(15) /* SDHI3 */
 522 #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI          0       /* SDHI3 */
 523 #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK         BIT(14) /* SDHI3 */
 524 #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST        BIT(14) /* SDHI3 */
 525 #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST       0       /* SDHI3 */
 526 #define HPB_DMAE_ASYNCMDR_ASMD27_MASK           BIT(13) /* SDHI2 */
 527 #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE         BIT(13) /* SDHI2 */
 528 #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI          0       /* SDHI2 */
 529 #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK         BIT(12) /* SDHI2 */
 530 #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST        BIT(12) /* SDHI2 */
 531 #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST       0       /* SDHI2 */
 532 #define HPB_DMAE_ASYNCMDR_ASMD26_MASK           BIT(11) /* SDHI2 */
 533 #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE         BIT(11) /* SDHI2 */
 534 #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI          0       /* SDHI2 */
 535 #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK         BIT(10) /* SDHI2 */
 536 #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST        BIT(10) /* SDHI2 */
 537 #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST       0       /* SDHI2 */
 538 #define HPB_DMAE_ASYNCMDR_ASMD25_MASK           BIT(9)  /* SDHI2 */
 539 #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE         BIT(9)  /* SDHI2 */
 540 #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI          0       /* SDHI2 */
 541 #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK         BIT(8)  /* SDHI2 */
 542 #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST        BIT(8)  /* SDHI2 */
 543 #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST       0       /* SDHI2 */
 544 #define HPB_DMAE_ASYNCMDR_ASMD23_MASK           BIT(7)  /* SDHI0 */
 545 #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE         BIT(7)  /* SDHI0 */
 546 #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI          0       /* SDHI0 */
 547 #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK         BIT(6)  /* SDHI0 */
 548 #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST        BIT(6)  /* SDHI0 */
 549 #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST       0       /* SDHI0 */
 550 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK           BIT(5)  /* SDHI0 */
 551 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE         BIT(5)  /* SDHI0 */
 552 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI          0       /* SDHI0 */
 553 #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK         BIT(4)  /* SDHI0 */
 554 #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST        BIT(4)  /* SDHI0 */
 555 #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST       0       /* SDHI0 */
 556 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK           BIT(3)  /* SDHI0 */
 557 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE         BIT(3)  /* SDHI0 */
 558 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI          0       /* SDHI0 */
 559 #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK         BIT(2)  /* SDHI0 */
 560 #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST        BIT(2)  /* SDHI0 */
 561 #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST       0       /* SDHI0 */
 562 #define HPB_DMAE_ASYNCMDR_ASMD20_MASK           BIT(1)  /* SDHI1 */
 563 #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE         BIT(1)  /* SDHI1 */
 564 #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI          0       /* SDHI1 */
 565 #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK         BIT(0)  /* SDHI1 */
 566 #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST        BIT(0)  /* SDHI1 */
 567 #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST       0       /* SDHI1 */
 568
 569 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
 570         {
 571                 .id     = HPBDMA_SLAVE_SDHI0_TX,
 572                 .addr   = 0xffe4c000 + 0x30,
 573                 .dcr    = HPB_DMAE_DCR_SPDS_16BIT |
 574                           HPB_DMAE_DCR_DMDL |
 575                           HPB_DMAE_DCR_DPDS_16BIT,
 576                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 577                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 578                           HPB_DMAE_ASYNCRSTR_ASRST23,
 579                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
 580                           HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
 581                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
 582                           HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
 583                 .port   = 0x0D0C,
 584                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 585                 .dma_ch = 21,
 586         }, {
 587                 .id     = HPBDMA_SLAVE_SDHI0_RX,
 588                 .addr   = 0xffe4c000 + 0x30,
 589                 .dcr    = HPB_DMAE_DCR_SMDL |
 590                           HPB_DMAE_DCR_SPDS_16BIT |
 591                           HPB_DMAE_DCR_DPDS_16BIT,
 592                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 593                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 594                           HPB_DMAE_ASYNCRSTR_ASRST23,
 595                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
 596                           HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
 597                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
 598                           HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
 599                 .port   = 0x0D0C,
 600                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 601                 .dma_ch = 22,
 602         },
 603 };
 604
 605 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
 606         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
 607         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
 608 };
 609
 610 static struct hpb_dmae_pdata dma_platform_data __initdata = {
 611         .slaves                 = hpb_dmae_slaves,
 612         .num_slaves             = ARRAY_SIZE(hpb_dmae_slaves),
 613         .channels               = hpb_dmae_channels,
 614         .num_channels           = ARRAY_SIZE(hpb_dmae_channels),
 615         .ts_shift               = {
 616                 [XMIT_SZ_8BIT]  = 0,
 617                 [XMIT_SZ_16BIT] = 1,
 618                 [XMIT_SZ_32BIT] = 2,
 619         },
 620         .num_hw_channels        = 44,
 621 };
 622
 623 static struct resource hpb_dmae_resources[] __initdata = {
 624         /* Channel registers */
 625         DEFINE_RES_MEM(0xffc08000, 0x1000),
 626         /* Common registers */
 627         DEFINE_RES_MEM(0xffc09000, 0x170),
 628         /* Asynchronous reset registers */
 629         DEFINE_RES_MEM(0xffc00300, 4),
 630         /* Asynchronous mode registers */
 631         DEFINE_RES_MEM(0xffc00400, 4),
 632         /* IRQ for DMA channels */
 633         DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
 634 };
 635
 636 static void __init r8a7779_register_hpb_dmae(void)
 637 {
 638         platform_device_register_resndata(NULL, "hpb-dma-engine",
 639                                           -1, hpb_dmae_resources,
 640                                           ARRAY_SIZE(hpb_dmae_resources),
 641                                           &dma_platform_data,
 642                                           sizeof(dma_platform_data));
 643 }
 644
 645 static struct platform_device *r8a7779_early_devices[] __initdata = {
 646         &tmu0_device,
 647 };
 648
 649 static struct platform_device *r8a7779_standard_devices[] __initdata = {
 650         &scif0_device,
 651         &scif1_device,
 652         &scif2_device,
 653         &scif3_device,
 654         &scif4_device,
 655         &scif5_device,
 656         &i2c0_device,
 657         &i2c1_device,
 658         &i2c2_device,
 659         &i2c3_device,
 660         &sata_device,
 661 };
 662
 663 void __init r8a7779_add_standard_devices(void)
 664 {
 665 #ifdef CONFIG_CACHE_L2X0
 666         /* Shared attribute override enable, 64K*16way */
 667         l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
 668 #endif
 669         r8a7779_pm_init();
 670
 671         r8a7779_init_pm_domains();
 672
 673         platform_add_devices(r8a7779_early_devices,
 674                             ARRAY_SIZE(r8a7779_early_devices));
 675         platform_add_devices(r8a7779_standard_devices,
 676                             ARRAY_SIZE(r8a7779_standard_devices));
 677         r8a7779_register_hpb_dmae();
 678 }
 679
 680 void __init r8a7779_add_early_devices(void)
 681 {
 682         early_platform_add_devices(r8a7779_early_devices,
 683                                    ARRAY_SIZE(r8a7779_early_devices));
 684
 685         /* Early serial console setup is not included here due to
 686          * memory map collisions. The SCIF serial ports in r8a7779
 687          * are difficult to entity map 1:1 due to collision with the
 688          * virtual memory range used by the coherent DMA code on ARM.
 689          *
 690          * Anyone wanting to debug early can remove UPF_IOREMAP from
 691          * the sh-sci serial console platform data, adjust mapbase
 692          * to a static M:N virt:phys mapping that needs to be added to
 693          * the mappings passed with iotable_init() above.
 694          *
 695          * Then add a call to shmobile_setup_console() from this function.
 696          *
 697          * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
 698          * command line in case of the marzen board.
 699          */
 700 }
 701
 702 static struct platform_device *r8a7779_late_devices[] __initdata = {
 703         &ehci0_device,
 704         &ehci1_device,
 705         &ohci0_device,
 706         &ohci1_device,
 707 };
 708
 709 void __init r8a7779_init_late(void)
 710 {
 711         /* get USB PHY */
 712         phy = usb_get_phy(USB_PHY_TYPE_USB2);
 713
 714         shmobile_init_late();
 715         platform_add_devices(r8a7779_late_devices,
 716                              ARRAY_SIZE(r8a7779_late_devices));
 717 }
 718
 719 #ifdef CONFIG_USE_OF
 720 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 721 {
 722         return 0; /* always allow wakeup */
 723 }
 724
 725 void __init r8a7779_init_irq_dt(void)
 726 {
 727 #ifdef CONFIG_ARCH_SHMOBILE_LEGACY
 728         void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000);
 729         void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000);
 730 #endif
 731         gic_arch_extn.irq_set_wake = r8a7779_set_wake;
 732
 733 #ifdef CONFIG_ARCH_SHMOBILE_LEGACY
 734         gic_init(0, 29, gic_dist_base, gic_cpu_base);
 735 #else
 736         irqchip_init();
 737 #endif
 738         /* route all interrupts to ARM */
 739         __raw_writel(0xffffffff, INT2NTSR0);
 740         __raw_writel(0x3fffffff, INT2NTSR1);
 741
 742         /* unmask all known interrupts in INTCS2 */
 743         __raw_writel(0xfffffff0, INT2SMSKCR0);
 744         __raw_writel(0xfff7ffff, INT2SMSKCR1);
 745         __raw_writel(0xfffbffdf, INT2SMSKCR2);
 746         __raw_writel(0xbffffffc, INT2SMSKCR3);
 747         __raw_writel(0x003fee3f, INT2SMSKCR4);
 748 }
 749
 750 #define MODEMR          0xffcc0020
 751
 752 u32 __init r8a7779_read_mode_pins(void)
 753 {
 754         static u32 mode;
 755         static bool mode_valid;
 756
 757         if (!mode_valid) {
 758                 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
 759                 BUG_ON(!modemr);
 760                 mode = ioread32(modemr);
 761                 iounmap(modemr);
 762                 mode_valid = true;
 763         }
 764
 765         return mode;
 766 }
 767
 768 static const char *r8a7779_compat_dt[] __initdata = {
 769         "renesas,r8a7779",
 770         NULL,
 771 };
 772
 773 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
 774         .map_io         = r8a7779_map_io,
 775         .init_early     = shmobile_init_delay,
 776         .init_irq       = r8a7779_init_irq_dt,
 777         .init_late      = shmobile_init_late,
 778         .dt_compat      = r8a7779_compat_dt,
 779 MACHINE_END
 780 #endif /* CONFIG_USE_OF */