arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/uio_driver.h>
  23 #include <linux/delay.h>
  24 #include <linux/input.h>
  25 #include <linux/io.h>
  26 #include <linux/serial_sci.h>
  27 #include <linux/sh_dma.h>
  28 #include <linux/sh_timer.h>
  29 #include <linux/pm_domain.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_data/sh_ipmmu.h>
  32
  33 #include <asm/mach/map.h>
  34 #include <asm/mach-types.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/time.h>
  37
  38 #include "common.h"
  39 #include "dma-register.h"
  40 #include "intc.h"
  41 #include "irqs.h"
  42 #include "pm-rmobile.h"
  43 #include "sh7372.h"
  44
  45 static struct map_desc sh7372_io_desc[] __initdata = {
  46         /* create a 1:1 entity map for 0xe6xxxxxx
  47          * used by CPGA, INTC and PFC.
  48          */
  49         {
  50                 .virtual        = 0xe6000000,
  51                 .pfn            = __phys_to_pfn(0xe6000000),
  52                 .length         = 256 << 20,
  53                 .type           = MT_DEVICE_NONSHARED
  54         },
  55 };
  56
  57 void __init sh7372_map_io(void)
  58 {
  59         iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
  60 }
  61
  62 /* PFC */
  63 static struct resource sh7372_pfc_resources[] = {
  64         [0] = {
  65                 .start  = 0xe6050000,
  66                 .end    = 0xe6057fff,
  67                 .flags  = IORESOURCE_MEM,
  68         },
  69         [1] = {
  70                 .start  = 0xe605800c,
  71                 .end    = 0xe6058027,
  72                 .flags  = IORESOURCE_MEM,
  73         }
  74 };
  75
  76 static struct platform_device sh7372_pfc_device = {
  77         .name           = "pfc-sh7372",
  78         .id             = -1,
  79         .resource       = sh7372_pfc_resources,
  80         .num_resources  = ARRAY_SIZE(sh7372_pfc_resources),
  81 };
  82
  83 void __init sh7372_pinmux_init(void)
  84 {
  85         platform_device_register(&sh7372_pfc_device);
  86 }
  87
  88 /* SCIF */
  89 #define SH7372_SCIF(scif_type, index, baseaddr, irq)            \
  90 static struct plat_sci_port scif##index##_platform_data = {     \
  91         .type           = scif_type,                            \
  92         .flags          = UPF_BOOT_AUTOCONF,                    \
  93         .scscr          = SCSCR_RE | SCSCR_TE,                  \
  94 };                                                              \
  95                                                                 \
  96 static struct resource scif##index##_resources[] = {            \
  97         DEFINE_RES_MEM(baseaddr, 0x100),                        \
  98         DEFINE_RES_IRQ(irq),                                    \
  99 };                                                              \
 100                                                                 \
 101 static struct platform_device scif##index##_device = {          \
 102         .name           = "sh-sci",                             \
 103         .id             = index,                                \
 104         .resource       = scif##index##_resources,              \
 105         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 106         .dev            = {                                     \
 107                 .platform_data  = &scif##index##_platform_data, \
 108         },                                                      \
 109 }
 110
 111 SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
 112 SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
 113 SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
 114 SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
 115 SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
 116 SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
 117 SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
 118
 119 /* CMT */
 120 static struct sh_timer_config cmt2_platform_data = {
 121         .channels_mask = 0x20,
 122 };
 123
 124 static struct resource cmt2_resources[] = {
 125         DEFINE_RES_MEM(0xe6130000, 0x50),
 126         DEFINE_RES_IRQ(evt2irq(0x0b80)),
 127 };
 128
 129 static struct platform_device cmt2_device = {
 130         .name           = "sh-cmt-32-fast",
 131         .id             = 2,
 132         .dev = {
 133                 .platform_data  = &cmt2_platform_data,
 134         },
 135         .resource       = cmt2_resources,
 136         .num_resources  = ARRAY_SIZE(cmt2_resources),
 137 };
 138
 139 /* TMU */
 140 static struct sh_timer_config tmu0_platform_data = {
 141         .channels_mask = 7,
 142 };
 143
 144 static struct resource tmu0_resources[] = {
 145         DEFINE_RES_MEM(0xfff60000, 0x2c),
 146         DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
 147         DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
 148         DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
 149 };
 150
 151 static struct platform_device tmu0_device = {
 152         .name           = "sh-tmu",
 153         .id             = 0,
 154         .dev = {
 155                 .platform_data  = &tmu0_platform_data,
 156         },
 157         .resource       = tmu0_resources,
 158         .num_resources  = ARRAY_SIZE(tmu0_resources),
 159 };
 160
 161 /* I2C */
 162 static struct resource iic0_resources[] = {
 163         [0] = {
 164                 .name   = "IIC0",
 165                 .start  = 0xFFF20000,
 166                 .end    = 0xFFF20425 - 1,
 167                 .flags  = IORESOURCE_MEM,
 168         },
 169         [1] = {
 170                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 171                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 172                 .flags  = IORESOURCE_IRQ,
 173         },
 174 };
 175
 176 static struct platform_device iic0_device = {
 177         .name           = "i2c-sh_mobile",
 178         .id             = 0, /* "i2c0" clock */
 179         .num_resources  = ARRAY_SIZE(iic0_resources),
 180         .resource       = iic0_resources,
 181 };
 182
 183 static struct resource iic1_resources[] = {
 184         [0] = {
 185                 .name   = "IIC1",
 186                 .start  = 0xE6C20000,
 187                 .end    = 0xE6C20425 - 1,
 188                 .flags  = IORESOURCE_MEM,
 189         },
 190         [1] = {
 191                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 192                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 193                 .flags  = IORESOURCE_IRQ,
 194         },
 195 };
 196
 197 static struct platform_device iic1_device = {
 198         .name           = "i2c-sh_mobile",
 199         .id             = 1, /* "i2c1" clock */
 200         .num_resources  = ARRAY_SIZE(iic1_resources),
 201         .resource       = iic1_resources,
 202 };
 203
 204 /* DMA */
 205 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 206         {
 207                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 208                 .addr           = 0xe6c40020,
 209                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 210                 .mid_rid        = 0x21,
 211         }, {
 212                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 213                 .addr           = 0xe6c40024,
 214                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 215                 .mid_rid        = 0x22,
 216         }, {
 217                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 218                 .addr           = 0xe6c50020,
 219                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 220                 .mid_rid        = 0x25,
 221         }, {
 222                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 223                 .addr           = 0xe6c50024,
 224                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 225                 .mid_rid        = 0x26,
 226         }, {
 227                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 228                 .addr           = 0xe6c60020,
 229                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 230                 .mid_rid        = 0x29,
 231         }, {
 232                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 233                 .addr           = 0xe6c60024,
 234                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 235                 .mid_rid        = 0x2a,
 236         }, {
 237                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 238                 .addr           = 0xe6c70020,
 239                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 240                 .mid_rid        = 0x2d,
 241         }, {
 242                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 243                 .addr           = 0xe6c70024,
 244                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 245                 .mid_rid        = 0x2e,
 246         }, {
 247                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 248                 .addr           = 0xe6c80020,
 249                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 250                 .mid_rid        = 0x39,
 251         }, {
 252                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 253                 .addr           = 0xe6c80024,
 254                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 255                 .mid_rid        = 0x3a,
 256         }, {
 257                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 258                 .addr           = 0xe6cb0020,
 259                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 260                 .mid_rid        = 0x35,
 261         }, {
 262                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 263                 .addr           = 0xe6cb0024,
 264                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 265                 .mid_rid        = 0x36,
 266         }, {
 267                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 268                 .addr           = 0xe6c30040,
 269                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 270                 .mid_rid        = 0x3d,
 271         }, {
 272                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 273                 .addr           = 0xe6c30060,
 274                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 275                 .mid_rid        = 0x3e,
 276         }, {
 277                 .slave_id       = SHDMA_SLAVE_FLCTL0_TX,
 278                 .addr           = 0xe6a30050,
 279                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 280                 .mid_rid        = 0x83,
 281         }, {
 282                 .slave_id       = SHDMA_SLAVE_FLCTL0_RX,
 283                 .addr           = 0xe6a30050,
 284                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 285                 .mid_rid        = 0x83,
 286         }, {
 287                 .slave_id       = SHDMA_SLAVE_FLCTL1_TX,
 288                 .addr           = 0xe6a30060,
 289                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 290                 .mid_rid        = 0x87,
 291         }, {
 292                 .slave_id       = SHDMA_SLAVE_FLCTL1_RX,
 293                 .addr           = 0xe6a30060,
 294                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 295                 .mid_rid        = 0x87,
 296         }, {
 297                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 298                 .addr           = 0xe6850030,
 299                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 300                 .mid_rid        = 0xc1,
 301         }, {
 302                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 303                 .addr           = 0xe6850030,
 304                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 305                 .mid_rid        = 0xc2,
 306         }, {
 307                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 308                 .addr           = 0xe6860030,
 309                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 310                 .mid_rid        = 0xc9,
 311         }, {
 312                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 313                 .addr           = 0xe6860030,
 314                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 315                 .mid_rid        = 0xca,
 316         }, {
 317                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 318                 .addr           = 0xe6870030,
 319                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 320                 .mid_rid        = 0xcd,
 321         }, {
 322                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 323                 .addr           = 0xe6870030,
 324                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 325                 .mid_rid        = 0xce,
 326         }, {
 327                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 328                 .addr           = 0xfe1f0024,
 329                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 330                 .mid_rid        = 0xb1,
 331         }, {
 332                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 333                 .addr           = 0xfe1f0020,
 334                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 335                 .mid_rid        = 0xb2,
 336         }, {
 337                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 338                 .addr           = 0xe6bd0034,
 339                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 340                 .mid_rid        = 0xd1,
 341         }, {
 342                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 343                 .addr           = 0xe6bd0034,
 344                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 345                 .mid_rid        = 0xd2,
 346         },
 347 };
 348
 349 #define SH7372_CHCLR (0x220 - 0x20)
 350
 351 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 352         {
 353                 .offset = 0,
 354                 .dmars = 0,
 355                 .dmars_bit = 0,
 356                 .chclr_offset = SH7372_CHCLR + 0,
 357         }, {
 358                 .offset = 0x10,
 359                 .dmars = 0,
 360                 .dmars_bit = 8,
 361                 .chclr_offset = SH7372_CHCLR + 0x10,
 362         }, {
 363                 .offset = 0x20,
 364                 .dmars = 4,
 365                 .dmars_bit = 0,
 366                 .chclr_offset = SH7372_CHCLR + 0x20,
 367         }, {
 368                 .offset = 0x30,
 369                 .dmars = 4,
 370                 .dmars_bit = 8,
 371                 .chclr_offset = SH7372_CHCLR + 0x30,
 372         }, {
 373                 .offset = 0x50,
 374                 .dmars = 8,
 375                 .dmars_bit = 0,
 376                 .chclr_offset = SH7372_CHCLR + 0x50,
 377         }, {
 378                 .offset = 0x60,
 379                 .dmars = 8,
 380                 .dmars_bit = 8,
 381                 .chclr_offset = SH7372_CHCLR + 0x60,
 382         }
 383 };
 384
 385 static struct sh_dmae_pdata dma_platform_data = {
 386         .slave          = sh7372_dmae_slaves,
 387         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 388         .channel        = sh7372_dmae_channels,
 389         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 390         .ts_low_shift   = TS_LOW_SHIFT,
 391         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 392         .ts_high_shift  = TS_HI_SHIFT,
 393         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 394         .ts_shift       = dma_ts_shift,
 395         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 396         .dmaor_init     = DMAOR_DME,
 397         .chclr_present  = 1,
 398 };
 399
 400 /* Resource order important! */
 401 static struct resource sh7372_dmae0_resources[] = {
 402         {
 403                 /* Channel registers and DMAOR */
 404                 .start  = 0xfe008020,
 405                 .end    = 0xfe00828f,
 406                 .flags  = IORESOURCE_MEM,
 407         },
 408         {
 409                 /* DMARSx */
 410                 .start  = 0xfe009000,
 411                 .end    = 0xfe00900b,
 412                 .flags  = IORESOURCE_MEM,
 413         },
 414         {
 415                 .name   = "error_irq",
 416                 .start  = evt2irq(0x20c0),
 417                 .end    = evt2irq(0x20c0),
 418                 .flags  = IORESOURCE_IRQ,
 419         },
 420         {
 421                 /* IRQ for channels 0-5 */
 422                 .start  = evt2irq(0x2000),
 423                 .end    = evt2irq(0x20a0),
 424                 .flags  = IORESOURCE_IRQ,
 425         },
 426 };
 427
 428 /* Resource order important! */
 429 static struct resource sh7372_dmae1_resources[] = {
 430         {
 431                 /* Channel registers and DMAOR */
 432                 .start  = 0xfe018020,
 433                 .end    = 0xfe01828f,
 434                 .flags  = IORESOURCE_MEM,
 435         },
 436         {
 437                 /* DMARSx */
 438                 .start  = 0xfe019000,
 439                 .end    = 0xfe01900b,
 440                 .flags  = IORESOURCE_MEM,
 441         },
 442         {
 443                 .name   = "error_irq",
 444                 .start  = evt2irq(0x21c0),
 445                 .end    = evt2irq(0x21c0),
 446                 .flags  = IORESOURCE_IRQ,
 447         },
 448         {
 449                 /* IRQ for channels 0-5 */
 450                 .start  = evt2irq(0x2100),
 451                 .end    = evt2irq(0x21a0),
 452                 .flags  = IORESOURCE_IRQ,
 453         },
 454 };
 455
 456 /* Resource order important! */
 457 static struct resource sh7372_dmae2_resources[] = {
 458         {
 459                 /* Channel registers and DMAOR */
 460                 .start  = 0xfe028020,
 461                 .end    = 0xfe02828f,
 462                 .flags  = IORESOURCE_MEM,
 463         },
 464         {
 465                 /* DMARSx */
 466                 .start  = 0xfe029000,
 467                 .end    = 0xfe02900b,
 468                 .flags  = IORESOURCE_MEM,
 469         },
 470         {
 471                 .name   = "error_irq",
 472                 .start  = evt2irq(0x22c0),
 473                 .end    = evt2irq(0x22c0),
 474                 .flags  = IORESOURCE_IRQ,
 475         },
 476         {
 477                 /* IRQ for channels 0-5 */
 478                 .start  = evt2irq(0x2200),
 479                 .end    = evt2irq(0x22a0),
 480                 .flags  = IORESOURCE_IRQ,
 481         },
 482 };
 483
 484 static struct platform_device dma0_device = {
 485         .name           = "sh-dma-engine",
 486         .id             = 0,
 487         .resource       = sh7372_dmae0_resources,
 488         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 489         .dev            = {
 490                 .platform_data  = &dma_platform_data,
 491         },
 492 };
 493
 494 static struct platform_device dma1_device = {
 495         .name           = "sh-dma-engine",
 496         .id             = 1,
 497         .resource       = sh7372_dmae1_resources,
 498         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 499         .dev            = {
 500                 .platform_data  = &dma_platform_data,
 501         },
 502 };
 503
 504 static struct platform_device dma2_device = {
 505         .name           = "sh-dma-engine",
 506         .id             = 2,
 507         .resource       = sh7372_dmae2_resources,
 508         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 509         .dev            = {
 510                 .platform_data  = &dma_platform_data,
 511         },
 512 };
 513
 514 /*
 515  * USB-DMAC
 516  */
 517 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 518         {
 519                 .offset = 0,
 520         }, {
 521                 .offset = 0x20,
 522         },
 523 };
 524
 525 /* USB DMAC0 */
 526 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
 527         {
 528                 .slave_id       = SHDMA_SLAVE_USB0_TX,
 529                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 530         }, {
 531                 .slave_id       = SHDMA_SLAVE_USB0_RX,
 532                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 533         },
 534 };
 535
 536 static struct sh_dmae_pdata usb_dma0_platform_data = {
 537         .slave          = sh7372_usb_dmae0_slaves,
 538         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
 539         .channel        = sh7372_usb_dmae_channels,
 540         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 541         .ts_low_shift   = USBTS_LOW_SHIFT,
 542         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 543         .ts_high_shift  = USBTS_HI_SHIFT,
 544         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 545         .ts_shift       = dma_usbts_shift,
 546         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 547         .dmaor_init     = DMAOR_DME,
 548         .chcr_offset    = 0x14,
 549         .chcr_ie_bit    = 1 << 5,
 550         .dmaor_is_32bit = 1,
 551         .needs_tend_set = 1,
 552         .no_dmars       = 1,
 553         .slave_only     = 1,
 554 };
 555
 556 static struct resource sh7372_usb_dmae0_resources[] = {
 557         {
 558                 /* Channel registers and DMAOR */
 559                 .start  = 0xe68a0020,
 560                 .end    = 0xe68a0064 - 1,
 561                 .flags  = IORESOURCE_MEM,
 562         },
 563         {
 564                 /* VCR/SWR/DMICR */
 565                 .start  = 0xe68a0000,
 566                 .end    = 0xe68a0014 - 1,
 567                 .flags  = IORESOURCE_MEM,
 568         },
 569         {
 570                 /* IRQ for channels */
 571                 .start  = evt2irq(0x0a00),
 572                 .end    = evt2irq(0x0a00),
 573                 .flags  = IORESOURCE_IRQ,
 574         },
 575 };
 576
 577 static struct platform_device usb_dma0_device = {
 578         .name           = "sh-dma-engine",
 579         .id             = 3,
 580         .resource       = sh7372_usb_dmae0_resources,
 581         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
 582         .dev            = {
 583                 .platform_data  = &usb_dma0_platform_data,
 584         },
 585 };
 586
 587 /* USB DMAC1 */
 588 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
 589         {
 590                 .slave_id       = SHDMA_SLAVE_USB1_TX,
 591                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 592         }, {
 593                 .slave_id       = SHDMA_SLAVE_USB1_RX,
 594                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 595         },
 596 };
 597
 598 static struct sh_dmae_pdata usb_dma1_platform_data = {
 599         .slave          = sh7372_usb_dmae1_slaves,
 600         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
 601         .channel        = sh7372_usb_dmae_channels,
 602         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 603         .ts_low_shift   = USBTS_LOW_SHIFT,
 604         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 605         .ts_high_shift  = USBTS_HI_SHIFT,
 606         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 607         .ts_shift       = dma_usbts_shift,
 608         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 609         .dmaor_init     = DMAOR_DME,
 610         .chcr_offset    = 0x14,
 611         .chcr_ie_bit    = 1 << 5,
 612         .dmaor_is_32bit = 1,
 613         .needs_tend_set = 1,
 614         .no_dmars       = 1,
 615         .slave_only     = 1,
 616 };
 617
 618 static struct resource sh7372_usb_dmae1_resources[] = {
 619         {
 620                 /* Channel registers and DMAOR */
 621                 .start  = 0xe68c0020,
 622                 .end    = 0xe68c0064 - 1,
 623                 .flags  = IORESOURCE_MEM,
 624         },
 625         {
 626                 /* VCR/SWR/DMICR */
 627                 .start  = 0xe68c0000,
 628                 .end    = 0xe68c0014 - 1,
 629                 .flags  = IORESOURCE_MEM,
 630         },
 631         {
 632                 /* IRQ for channels */
 633                 .start  = evt2irq(0x1d00),
 634                 .end    = evt2irq(0x1d00),
 635                 .flags  = IORESOURCE_IRQ,
 636         },
 637 };
 638
 639 static struct platform_device usb_dma1_device = {
 640         .name           = "sh-dma-engine",
 641         .id             = 4,
 642         .resource       = sh7372_usb_dmae1_resources,
 643         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
 644         .dev            = {
 645                 .platform_data  = &usb_dma1_platform_data,
 646         },
 647 };
 648
 649 /* VPU */
 650 static struct uio_info vpu_platform_data = {
 651         .name = "VPU5HG",
 652         .version = "0",
 653         .irq = intcs_evt2irq(0x980),
 654 };
 655
 656 static struct resource vpu_resources[] = {
 657         [0] = {
 658                 .name   = "VPU",
 659                 .start  = 0xfe900000,
 660                 .end    = 0xfe900157,
 661                 .flags  = IORESOURCE_MEM,
 662         },
 663 };
 664
 665 static struct platform_device vpu_device = {
 666         .name           = "uio_pdrv_genirq",
 667         .id             = 0,
 668         .dev = {
 669                 .platform_data  = &vpu_platform_data,
 670         },
 671         .resource       = vpu_resources,
 672         .num_resources  = ARRAY_SIZE(vpu_resources),
 673 };
 674
 675 /* VEU0 */
 676 static struct uio_info veu0_platform_data = {
 677         .name = "VEU0",
 678         .version = "0",
 679         .irq = intcs_evt2irq(0x700),
 680 };
 681
 682 static struct resource veu0_resources[] = {
 683         [0] = {
 684                 .name   = "VEU0",
 685                 .start  = 0xfe920000,
 686                 .end    = 0xfe9200cb,
 687                 .flags  = IORESOURCE_MEM,
 688         },
 689 };
 690
 691 static struct platform_device veu0_device = {
 692         .name           = "uio_pdrv_genirq",
 693         .id             = 1,
 694         .dev = {
 695                 .platform_data  = &veu0_platform_data,
 696         },
 697         .resource       = veu0_resources,
 698         .num_resources  = ARRAY_SIZE(veu0_resources),
 699 };
 700
 701 /* VEU1 */
 702 static struct uio_info veu1_platform_data = {
 703         .name = "VEU1",
 704         .version = "0",
 705         .irq = intcs_evt2irq(0x720),
 706 };
 707
 708 static struct resource veu1_resources[] = {
 709         [0] = {
 710                 .name   = "VEU1",
 711                 .start  = 0xfe924000,
 712                 .end    = 0xfe9240cb,
 713                 .flags  = IORESOURCE_MEM,
 714         },
 715 };
 716
 717 static struct platform_device veu1_device = {
 718         .name           = "uio_pdrv_genirq",
 719         .id             = 2,
 720         .dev = {
 721                 .platform_data  = &veu1_platform_data,
 722         },
 723         .resource       = veu1_resources,
 724         .num_resources  = ARRAY_SIZE(veu1_resources),
 725 };
 726
 727 /* VEU2 */
 728 static struct uio_info veu2_platform_data = {
 729         .name = "VEU2",
 730         .version = "0",
 731         .irq = intcs_evt2irq(0x740),
 732 };
 733
 734 static struct resource veu2_resources[] = {
 735         [0] = {
 736                 .name   = "VEU2",
 737                 .start  = 0xfe928000,
 738                 .end    = 0xfe928307,
 739                 .flags  = IORESOURCE_MEM,
 740         },
 741 };
 742
 743 static struct platform_device veu2_device = {
 744         .name           = "uio_pdrv_genirq",
 745         .id             = 3,
 746         .dev = {
 747                 .platform_data  = &veu2_platform_data,
 748         },
 749         .resource       = veu2_resources,
 750         .num_resources  = ARRAY_SIZE(veu2_resources),
 751 };
 752
 753 /* VEU3 */
 754 static struct uio_info veu3_platform_data = {
 755         .name = "VEU3",
 756         .version = "0",
 757         .irq = intcs_evt2irq(0x760),
 758 };
 759
 760 static struct resource veu3_resources[] = {
 761         [0] = {
 762                 .name   = "VEU3",
 763                 .start  = 0xfe92c000,
 764                 .end    = 0xfe92c307,
 765                 .flags  = IORESOURCE_MEM,
 766         },
 767 };
 768
 769 static struct platform_device veu3_device = {
 770         .name           = "uio_pdrv_genirq",
 771         .id             = 4,
 772         .dev = {
 773                 .platform_data  = &veu3_platform_data,
 774         },
 775         .resource       = veu3_resources,
 776         .num_resources  = ARRAY_SIZE(veu3_resources),
 777 };
 778
 779 /* JPU */
 780 static struct uio_info jpu_platform_data = {
 781         .name = "JPU",
 782         .version = "0",
 783         .irq = intcs_evt2irq(0x560),
 784 };
 785
 786 static struct resource jpu_resources[] = {
 787         [0] = {
 788                 .name   = "JPU",
 789                 .start  = 0xfe980000,
 790                 .end    = 0xfe9902d3,
 791                 .flags  = IORESOURCE_MEM,
 792         },
 793 };
 794
 795 static struct platform_device jpu_device = {
 796         .name           = "uio_pdrv_genirq",
 797         .id             = 5,
 798         .dev = {
 799                 .platform_data  = &jpu_platform_data,
 800         },
 801         .resource       = jpu_resources,
 802         .num_resources  = ARRAY_SIZE(jpu_resources),
 803 };
 804
 805 /* SPU2DSP0 */
 806 static struct uio_info spu0_platform_data = {
 807         .name = "SPU2DSP0",
 808         .version = "0",
 809         .irq = evt2irq(0x1800),
 810 };
 811
 812 static struct resource spu0_resources[] = {
 813         [0] = {
 814                 .name   = "SPU2DSP0",
 815                 .start  = 0xfe200000,
 816                 .end    = 0xfe2fffff,
 817                 .flags  = IORESOURCE_MEM,
 818         },
 819 };
 820
 821 static struct platform_device spu0_device = {
 822         .name           = "uio_pdrv_genirq",
 823         .id             = 6,
 824         .dev = {
 825                 .platform_data  = &spu0_platform_data,
 826         },
 827         .resource       = spu0_resources,
 828         .num_resources  = ARRAY_SIZE(spu0_resources),
 829 };
 830
 831 /* SPU2DSP1 */
 832 static struct uio_info spu1_platform_data = {
 833         .name = "SPU2DSP1",
 834         .version = "0",
 835         .irq = evt2irq(0x1820),
 836 };
 837
 838 static struct resource spu1_resources[] = {
 839         [0] = {
 840                 .name   = "SPU2DSP1",
 841                 .start  = 0xfe300000,
 842                 .end    = 0xfe3fffff,
 843                 .flags  = IORESOURCE_MEM,
 844         },
 845 };
 846
 847 static struct platform_device spu1_device = {
 848         .name           = "uio_pdrv_genirq",
 849         .id             = 7,
 850         .dev = {
 851                 .platform_data  = &spu1_platform_data,
 852         },
 853         .resource       = spu1_resources,
 854         .num_resources  = ARRAY_SIZE(spu1_resources),
 855 };
 856
 857 /* IPMMUI (an IPMMU module for ICB/LMB) */
 858 static struct resource ipmmu_resources[] = {
 859         [0] = {
 860                 .name   = "IPMMUI",
 861                 .start  = 0xfe951000,
 862                 .end    = 0xfe9510ff,
 863                 .flags  = IORESOURCE_MEM,
 864         },
 865 };
 866
 867 static const char * const ipmmu_dev_names[] = {
 868         "sh_mobile_lcdc_fb.0",
 869         "sh_mobile_lcdc_fb.1",
 870         "sh_mobile_ceu.0",
 871         "uio_pdrv_genirq.0",
 872         "uio_pdrv_genirq.1",
 873         "uio_pdrv_genirq.2",
 874         "uio_pdrv_genirq.3",
 875         "uio_pdrv_genirq.4",
 876         "uio_pdrv_genirq.5",
 877 };
 878
 879 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 880         .dev_names = ipmmu_dev_names,
 881         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 882 };
 883
 884 static struct platform_device ipmmu_device = {
 885         .name           = "ipmmu",
 886         .id             = -1,
 887         .dev = {
 888                 .platform_data = &ipmmu_platform_data,
 889         },
 890         .resource       = ipmmu_resources,
 891         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 892 };
 893
 894 static struct platform_device *sh7372_early_devices[] __initdata = {
 895         &scif0_device,
 896         &scif1_device,
 897         &scif2_device,
 898         &scif3_device,
 899         &scif4_device,
 900         &scif5_device,
 901         &scif6_device,
 902         &cmt2_device,
 903         &tmu0_device,
 904         &ipmmu_device,
 905 };
 906
 907 static struct platform_device *sh7372_late_devices[] __initdata = {
 908         &iic0_device,
 909         &iic1_device,
 910         &dma0_device,
 911         &dma1_device,
 912         &dma2_device,
 913         &usb_dma0_device,
 914         &usb_dma1_device,
 915         &vpu_device,
 916         &veu0_device,
 917         &veu1_device,
 918         &veu2_device,
 919         &veu3_device,
 920         &jpu_device,
 921         &spu0_device,
 922         &spu1_device,
 923 };
 924
 925 void __init sh7372_add_standard_devices(void)
 926 {
 927         static struct pm_domain_device domain_devices[] __initdata = {
 928                 { "A3RV", &vpu_device, },
 929                 { "A4MP", &spu0_device, },
 930                 { "A4MP", &spu1_device, },
 931                 { "A3SP", &scif0_device, },
 932                 { "A3SP", &scif1_device, },
 933                 { "A3SP", &scif2_device, },
 934                 { "A3SP", &scif3_device, },
 935                 { "A3SP", &scif4_device, },
 936                 { "A3SP", &scif5_device, },
 937                 { "A3SP", &scif6_device, },
 938                 { "A3SP", &iic1_device, },
 939                 { "A3SP", &dma0_device, },
 940                 { "A3SP", &dma1_device, },
 941                 { "A3SP", &dma2_device, },
 942                 { "A3SP", &usb_dma0_device, },
 943                 { "A3SP", &usb_dma1_device, },
 944                 { "A4R", &iic0_device, },
 945                 { "A4R", &veu0_device, },
 946                 { "A4R", &veu1_device, },
 947                 { "A4R", &veu2_device, },
 948                 { "A4R", &veu3_device, },
 949                 { "A4R", &jpu_device, },
 950                 { "A4R", &tmu0_device, },
 951         };
 952
 953         sh7372_init_pm_domains();
 954
 955         platform_add_devices(sh7372_early_devices,
 956                             ARRAY_SIZE(sh7372_early_devices));
 957
 958         platform_add_devices(sh7372_late_devices,
 959                             ARRAY_SIZE(sh7372_late_devices));
 960
 961         rmobile_add_devices_to_domains(domain_devices,
 962                                        ARRAY_SIZE(domain_devices));
 963 }
 964
 965 void __init sh7372_earlytimer_init(void)
 966 {
 967         sh7372_clock_init();
 968         shmobile_earlytimer_init();
 969 }
 970
 971 void __init sh7372_add_early_devices(void)
 972 {
 973         early_platform_add_devices(sh7372_early_devices,
 974                                    ARRAY_SIZE(sh7372_early_devices));
 975
 976         /* setup early console here as well */
 977         shmobile_setup_console();
 978 }
 979
 980 #ifdef CONFIG_USE_OF
 981
 982 void __init sh7372_add_early_devices_dt(void)
 983 {
 984         shmobile_init_delay();
 985
 986         sh7372_add_early_devices();
 987 }
 988
 989 void __init sh7372_add_standard_devices_dt(void)
 990 {
 991         /* clocks are setup late during boot in the case of DT */
 992         sh7372_clock_init();
 993
 994         platform_add_devices(sh7372_early_devices,
 995                             ARRAY_SIZE(sh7372_early_devices));
 996
 997         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 998 }
 999
1000 static const char *sh7372_boards_compat_dt[] __initdata = {
1001         "renesas,sh7372",
1002         NULL,
1003 };
1004
1005 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1006         .map_io         = sh7372_map_io,
1007         .init_early     = sh7372_add_early_devices_dt,
1008         .init_irq       = sh7372_init_irq,
1009         .handle_irq     = shmobile_handle_irq_intc,
1010         .init_machine   = sh7372_add_standard_devices_dt,
1011         .dt_compat      = sh7372_boards_compat_dt,
1012 MACHINE_END
1013
1014 #endif /* CONFIG_USE_OF */