arch/arm/mach-shmobile/setup-sh73a0.c

   1 /*
   2  * sh73a0 processor support
   3  *
   4  * Copyright (C) 2010  Takashi Yoshii
   5  * Copyright (C) 2010  Magnus Damm
   6  * Copyright (C) 2008  Yoshihiro Shimoda
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/delay.h>
  24 #include <linux/input.h>
  25 #include <linux/i2c/i2c-sh_mobile.h>
  26 #include <linux/io.h>
  27 #include <linux/serial_sci.h>
  28 #include <linux/sh_dma.h>
  29 #include <linux/sh_timer.h>
  30 #include <linux/platform_data/sh_ipmmu.h>
  31 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  32
  33 #include <asm/mach-types.h>
  34 #include <asm/mach/map.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/time.h>
  37
  38 #include "common.h"
  39 #include "dma-register.h"
  40 #include "intc.h"
  41 #include "irqs.h"
  42 #include "sh73a0.h"
  43
  44 static struct map_desc sh73a0_io_desc[] __initdata = {
  45         /* create a 1:1 entity map for 0xe6xxxxxx
  46          * used by CPGA, INTC and PFC.
  47          */
  48         {
  49                 .virtual        = 0xe6000000,
  50                 .pfn            = __phys_to_pfn(0xe6000000),
  51                 .length         = 256 << 20,
  52                 .type           = MT_DEVICE_NONSHARED
  53         },
  54 };
  55
  56 void __init sh73a0_map_io(void)
  57 {
  58         iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
  59 }
  60
  61 /* PFC */
  62 static struct resource pfc_resources[] __initdata = {
  63         DEFINE_RES_MEM(0xe6050000, 0x8000),
  64         DEFINE_RES_MEM(0xe605801c, 0x000c),
  65 };
  66
  67 void __init sh73a0_pinmux_init(void)
  68 {
  69         platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
  70                                         ARRAY_SIZE(pfc_resources));
  71 }
  72
  73 /* SCIF */
  74 #define SH73A0_SCIF(scif_type, index, baseaddr, irq)            \
  75 static struct plat_sci_port scif##index##_platform_data = {     \
  76         .type           = scif_type,                            \
  77         .flags          = UPF_BOOT_AUTOCONF,                    \
  78         .scscr          = SCSCR_RE | SCSCR_TE,                  \
  79 };                                                              \
  80                                                                 \
  81 static struct resource scif##index##_resources[] = {            \
  82         DEFINE_RES_MEM(baseaddr, 0x100),                        \
  83         DEFINE_RES_IRQ(irq),                                    \
  84 };                                                              \
  85                                                                 \
  86 static struct platform_device scif##index##_device = {          \
  87         .name           = "sh-sci",                             \
  88         .id             = index,                                \
  89         .resource       = scif##index##_resources,              \
  90         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
  91         .dev            = {                                     \
  92                 .platform_data  = &scif##index##_platform_data, \
  93         },                                                      \
  94 }
  95
  96 SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
  97 SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
  98 SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
  99 SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
 100 SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
 101 SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
 102 SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
 103 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
 104 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
 105
 106 static struct sh_timer_config cmt1_platform_data = {
 107         .channels_mask = 0x3f,
 108 };
 109
 110 static struct resource cmt1_resources[] = {
 111         DEFINE_RES_MEM(0xe6138000, 0x200),
 112         DEFINE_RES_IRQ(gic_spi(65)),
 113 };
 114
 115 static struct platform_device cmt1_device = {
 116         .name           = "sh-cmt-48",
 117         .id             = 1,
 118         .dev = {
 119                 .platform_data  = &cmt1_platform_data,
 120         },
 121         .resource       = cmt1_resources,
 122         .num_resources  = ARRAY_SIZE(cmt1_resources),
 123 };
 124
 125 /* TMU */
 126 static struct sh_timer_config tmu0_platform_data = {
 127         .channels_mask = 7,
 128 };
 129
 130 static struct resource tmu0_resources[] = {
 131         DEFINE_RES_MEM(0xfff60000, 0x2c),
 132         DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
 133         DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
 134         DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
 135 };
 136
 137 static struct platform_device tmu0_device = {
 138         .name           = "sh-tmu",
 139         .id             = 0,
 140         .dev = {
 141                 .platform_data  = &tmu0_platform_data,
 142         },
 143         .resource       = tmu0_resources,
 144         .num_resources  = ARRAY_SIZE(tmu0_resources),
 145 };
 146
 147 static struct resource i2c0_resources[] = {
 148         [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
 149         [1] = {
 150                 .start  = gic_spi(167),
 151                 .end    = gic_spi(170),
 152                 .flags  = IORESOURCE_IRQ,
 153         },
 154 };
 155
 156 static struct resource i2c1_resources[] = {
 157         [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
 158         [1] = {
 159                 .start  = gic_spi(51),
 160                 .end    = gic_spi(54),
 161                 .flags  = IORESOURCE_IRQ,
 162         },
 163 };
 164
 165 static struct resource i2c2_resources[] = {
 166         [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
 167         [1] = {
 168                 .start  = gic_spi(171),
 169                 .end    = gic_spi(174),
 170                 .flags  = IORESOURCE_IRQ,
 171         },
 172 };
 173
 174 static struct resource i2c3_resources[] = {
 175         [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
 176         [1] = {
 177                 .start  = gic_spi(183),
 178                 .end    = gic_spi(186),
 179                 .flags  = IORESOURCE_IRQ,
 180         },
 181 };
 182
 183 static struct resource i2c4_resources[] = {
 184         [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
 185         [1] = {
 186                 .start  = gic_spi(187),
 187                 .end    = gic_spi(190),
 188                 .flags  = IORESOURCE_IRQ,
 189         },
 190 };
 191
 192 static struct i2c_sh_mobile_platform_data i2c_platform_data = {
 193         .clks_per_count = 2,
 194 };
 195
 196 static struct platform_device i2c0_device = {
 197         .name           = "i2c-sh_mobile",
 198         .id             = 0,
 199         .resource       = i2c0_resources,
 200         .num_resources  = ARRAY_SIZE(i2c0_resources),
 201         .dev            = {
 202                 .platform_data  = &i2c_platform_data,
 203         },
 204 };
 205
 206 static struct platform_device i2c1_device = {
 207         .name           = "i2c-sh_mobile",
 208         .id             = 1,
 209         .resource       = i2c1_resources,
 210         .num_resources  = ARRAY_SIZE(i2c1_resources),
 211         .dev            = {
 212                 .platform_data  = &i2c_platform_data,
 213         },
 214 };
 215
 216 static struct platform_device i2c2_device = {
 217         .name           = "i2c-sh_mobile",
 218         .id             = 2,
 219         .resource       = i2c2_resources,
 220         .num_resources  = ARRAY_SIZE(i2c2_resources),
 221         .dev            = {
 222                 .platform_data  = &i2c_platform_data,
 223         },
 224 };
 225
 226 static struct platform_device i2c3_device = {
 227         .name           = "i2c-sh_mobile",
 228         .id             = 3,
 229         .resource       = i2c3_resources,
 230         .num_resources  = ARRAY_SIZE(i2c3_resources),
 231         .dev            = {
 232                 .platform_data  = &i2c_platform_data,
 233         },
 234 };
 235
 236 static struct platform_device i2c4_device = {
 237         .name           = "i2c-sh_mobile",
 238         .id             = 4,
 239         .resource       = i2c4_resources,
 240         .num_resources  = ARRAY_SIZE(i2c4_resources),
 241         .dev            = {
 242                 .platform_data  = &i2c_platform_data,
 243         },
 244 };
 245
 246 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
 247         {
 248                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 249                 .addr           = 0xe6c40020,
 250                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 251                 .mid_rid        = 0x21,
 252         }, {
 253                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 254                 .addr           = 0xe6c40024,
 255                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 256                 .mid_rid        = 0x22,
 257         }, {
 258                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 259                 .addr           = 0xe6c50020,
 260                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 261                 .mid_rid        = 0x25,
 262         }, {
 263                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 264                 .addr           = 0xe6c50024,
 265                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 266                 .mid_rid        = 0x26,
 267         }, {
 268                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 269                 .addr           = 0xe6c60020,
 270                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 271                 .mid_rid        = 0x29,
 272         }, {
 273                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 274                 .addr           = 0xe6c60024,
 275                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 276                 .mid_rid        = 0x2a,
 277         }, {
 278                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 279                 .addr           = 0xe6c70020,
 280                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 281                 .mid_rid        = 0x2d,
 282         }, {
 283                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 284                 .addr           = 0xe6c70024,
 285                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 286                 .mid_rid        = 0x2e,
 287         }, {
 288                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 289                 .addr           = 0xe6c80020,
 290                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 291                 .mid_rid        = 0x39,
 292         }, {
 293                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 294                 .addr           = 0xe6c80024,
 295                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 296                 .mid_rid        = 0x3a,
 297         }, {
 298                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 299                 .addr           = 0xe6cb0020,
 300                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 301                 .mid_rid        = 0x35,
 302         }, {
 303                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 304                 .addr           = 0xe6cb0024,
 305                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 306                 .mid_rid        = 0x36,
 307         }, {
 308                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 309                 .addr           = 0xe6cc0020,
 310                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 311                 .mid_rid        = 0x1d,
 312         }, {
 313                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 314                 .addr           = 0xe6cc0024,
 315                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 316                 .mid_rid        = 0x1e,
 317         }, {
 318                 .slave_id       = SHDMA_SLAVE_SCIF7_TX,
 319                 .addr           = 0xe6cd0020,
 320                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 321                 .mid_rid        = 0x19,
 322         }, {
 323                 .slave_id       = SHDMA_SLAVE_SCIF7_RX,
 324                 .addr           = 0xe6cd0024,
 325                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 326                 .mid_rid        = 0x1a,
 327         }, {
 328                 .slave_id       = SHDMA_SLAVE_SCIF8_TX,
 329                 .addr           = 0xe6c30040,
 330                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 331                 .mid_rid        = 0x3d,
 332         }, {
 333                 .slave_id       = SHDMA_SLAVE_SCIF8_RX,
 334                 .addr           = 0xe6c30060,
 335                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 336                 .mid_rid        = 0x3e,
 337         }, {
 338                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 339                 .addr           = 0xee100030,
 340                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 341                 .mid_rid        = 0xc1,
 342         }, {
 343                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 344                 .addr           = 0xee100030,
 345                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 346                 .mid_rid        = 0xc2,
 347         }, {
 348                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 349                 .addr           = 0xee120030,
 350                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 351                 .mid_rid        = 0xc9,
 352         }, {
 353                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 354                 .addr           = 0xee120030,
 355                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 356                 .mid_rid        = 0xca,
 357         }, {
 358                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 359                 .addr           = 0xee140030,
 360                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 361                 .mid_rid        = 0xcd,
 362         }, {
 363                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 364                 .addr           = 0xee140030,
 365                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 366                 .mid_rid        = 0xce,
 367         }, {
 368                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 369                 .addr           = 0xe6bd0034,
 370                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 371                 .mid_rid        = 0xd1,
 372         }, {
 373                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 374                 .addr           = 0xe6bd0034,
 375                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 376                 .mid_rid        = 0xd2,
 377         },
 378 };
 379
 380 #define DMAE_CHANNEL(_offset)                                   \
 381         {                                                       \
 382                 .offset         = _offset - 0x20,               \
 383                 .dmars          = _offset - 0x20 + 0x40,        \
 384         }
 385
 386 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
 387         DMAE_CHANNEL(0x8000),
 388         DMAE_CHANNEL(0x8080),
 389         DMAE_CHANNEL(0x8100),
 390         DMAE_CHANNEL(0x8180),
 391         DMAE_CHANNEL(0x8200),
 392         DMAE_CHANNEL(0x8280),
 393         DMAE_CHANNEL(0x8300),
 394         DMAE_CHANNEL(0x8380),
 395         DMAE_CHANNEL(0x8400),
 396         DMAE_CHANNEL(0x8480),
 397         DMAE_CHANNEL(0x8500),
 398         DMAE_CHANNEL(0x8580),
 399         DMAE_CHANNEL(0x8600),
 400         DMAE_CHANNEL(0x8680),
 401         DMAE_CHANNEL(0x8700),
 402         DMAE_CHANNEL(0x8780),
 403         DMAE_CHANNEL(0x8800),
 404         DMAE_CHANNEL(0x8880),
 405         DMAE_CHANNEL(0x8900),
 406         DMAE_CHANNEL(0x8980),
 407 };
 408
 409 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 410         .slave          = sh73a0_dmae_slaves,
 411         .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
 412         .channel        = sh73a0_dmae_channels,
 413         .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
 414         .ts_low_shift   = TS_LOW_SHIFT,
 415         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 416         .ts_high_shift  = TS_HI_SHIFT,
 417         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 418         .ts_shift       = dma_ts_shift,
 419         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 420         .dmaor_init     = DMAOR_DME,
 421 };
 422
 423 static struct resource sh73a0_dmae_resources[] = {
 424         DEFINE_RES_MEM(0xfe000020, 0x89e0),
 425         {
 426                 .name   = "error_irq",
 427                 .start  = gic_spi(129),
 428                 .end    = gic_spi(129),
 429                 .flags  = IORESOURCE_IRQ,
 430         },
 431         {
 432                 /* IRQ for channels 0-19 */
 433                 .start  = gic_spi(109),
 434                 .end    = gic_spi(128),
 435                 .flags  = IORESOURCE_IRQ,
 436         },
 437 };
 438
 439 static struct platform_device dma0_device = {
 440         .name           = "sh-dma-engine",
 441         .id             = 0,
 442         .resource       = sh73a0_dmae_resources,
 443         .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
 444         .dev            = {
 445                 .platform_data  = &sh73a0_dmae_platform_data,
 446         },
 447 };
 448
 449 /* MPDMAC */
 450 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
 451         {
 452                 .slave_id       = SHDMA_SLAVE_FSI2A_RX,
 453                 .addr           = 0xec230020,
 454                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 455                 .mid_rid        = 0xd6, /* CHECK ME */
 456         }, {
 457                 .slave_id       = SHDMA_SLAVE_FSI2A_TX,
 458                 .addr           = 0xec230024,
 459                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 460                 .mid_rid        = 0xd5, /* CHECK ME */
 461         }, {
 462                 .slave_id       = SHDMA_SLAVE_FSI2C_RX,
 463                 .addr           = 0xec230060,
 464                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 465                 .mid_rid        = 0xda, /* CHECK ME */
 466         }, {
 467                 .slave_id       = SHDMA_SLAVE_FSI2C_TX,
 468                 .addr           = 0xec230064,
 469                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 470                 .mid_rid        = 0xd9, /* CHECK ME */
 471         }, {
 472                 .slave_id       = SHDMA_SLAVE_FSI2B_RX,
 473                 .addr           = 0xec240020,
 474                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 475                 .mid_rid        = 0x8e, /* CHECK ME */
 476         }, {
 477                 .slave_id       = SHDMA_SLAVE_FSI2B_TX,
 478                 .addr           = 0xec240024,
 479                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 480                 .mid_rid        = 0x8d, /* CHECK ME */
 481         }, {
 482                 .slave_id       = SHDMA_SLAVE_FSI2D_RX,
 483                 .addr           =  0xec240060,
 484                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 485                 .mid_rid        = 0x9a, /* CHECK ME */
 486         },
 487 };
 488
 489 #define MPDMA_CHANNEL(a, b, c)                  \
 490 {                                               \
 491         .offset         = a,                    \
 492         .dmars          = b,                    \
 493         .dmars_bit      = c,                    \
 494         .chclr_offset   = (0x220 - 0x20) + a    \
 495 }
 496
 497 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
 498         MPDMA_CHANNEL(0x00, 0, 0),
 499         MPDMA_CHANNEL(0x10, 0, 8),
 500         MPDMA_CHANNEL(0x20, 4, 0),
 501         MPDMA_CHANNEL(0x30, 4, 8),
 502         MPDMA_CHANNEL(0x50, 8, 0),
 503         MPDMA_CHANNEL(0x70, 8, 8),
 504 };
 505
 506 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 507         .slave          = sh73a0_mpdma_slaves,
 508         .slave_num      = ARRAY_SIZE(sh73a0_mpdma_slaves),
 509         .channel        = sh73a0_mpdma_channels,
 510         .channel_num    = ARRAY_SIZE(sh73a0_mpdma_channels),
 511         .ts_low_shift   = TS_LOW_SHIFT,
 512         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 513         .ts_high_shift  = TS_HI_SHIFT,
 514         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 515         .ts_shift       = dma_ts_shift,
 516         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 517         .dmaor_init     = DMAOR_DME,
 518         .chclr_present  = 1,
 519 };
 520
 521 /* Resource order important! */
 522 static struct resource sh73a0_mpdma_resources[] = {
 523         /* Channel registers and DMAOR */
 524         DEFINE_RES_MEM(0xec618020, 0x270),
 525         /* DMARSx */
 526         DEFINE_RES_MEM(0xec619000, 0xc),
 527         {
 528                 .name   = "error_irq",
 529                 .start  = gic_spi(181),
 530                 .end    = gic_spi(181),
 531                 .flags  = IORESOURCE_IRQ,
 532         },
 533         {
 534                 /* IRQ for channels 0-5 */
 535                 .start  = gic_spi(175),
 536                 .end    = gic_spi(180),
 537                 .flags  = IORESOURCE_IRQ,
 538         },
 539 };
 540
 541 static struct platform_device mpdma0_device = {
 542         .name           = "sh-dma-engine",
 543         .id             = 1,
 544         .resource       = sh73a0_mpdma_resources,
 545         .num_resources  = ARRAY_SIZE(sh73a0_mpdma_resources),
 546         .dev            = {
 547                 .platform_data  = &sh73a0_mpdma_platform_data,
 548         },
 549 };
 550
 551 static struct resource pmu_resources[] = {
 552         [0] = {
 553                 .start  = gic_spi(55),
 554                 .end    = gic_spi(55),
 555                 .flags  = IORESOURCE_IRQ,
 556         },
 557         [1] = {
 558                 .start  = gic_spi(56),
 559                 .end    = gic_spi(56),
 560                 .flags  = IORESOURCE_IRQ,
 561         },
 562 };
 563
 564 static struct platform_device pmu_device = {
 565         .name           = "arm-pmu",
 566         .id             = -1,
 567         .num_resources  = ARRAY_SIZE(pmu_resources),
 568         .resource       = pmu_resources,
 569 };
 570
 571 /* an IPMMU module for ICB */
 572 static struct resource ipmmu_resources[] = {
 573         DEFINE_RES_MEM(0xfe951000, 0x100),
 574 };
 575
 576 static const char * const ipmmu_dev_names[] = {
 577         "sh_mobile_lcdc_fb.0",
 578 };
 579
 580 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 581         .dev_names = ipmmu_dev_names,
 582         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 583 };
 584
 585 static struct platform_device ipmmu_device = {
 586         .name           = "ipmmu",
 587         .id             = -1,
 588         .dev = {
 589                 .platform_data = &ipmmu_platform_data,
 590         },
 591         .resource       = ipmmu_resources,
 592         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 593 };
 594
 595 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
 596         .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
 597 };
 598
 599 static struct resource irqpin0_resources[] = {
 600         DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
 601         DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
 602         DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
 603         DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
 604         DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
 605         DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
 606         DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
 607         DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
 608         DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
 609         DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
 610         DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
 611         DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
 612         DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
 613 };
 614
 615 static struct platform_device irqpin0_device = {
 616         .name           = "renesas_intc_irqpin",
 617         .id             = 0,
 618         .resource       = irqpin0_resources,
 619         .num_resources  = ARRAY_SIZE(irqpin0_resources),
 620         .dev            = {
 621                 .platform_data  = &irqpin0_platform_data,
 622         },
 623 };
 624
 625 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
 626         .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
 627         .control_parent = true, /* Disable spurious IRQ10 */
 628 };
 629
 630 static struct resource irqpin1_resources[] = {
 631         DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
 632         DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
 633         DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
 634         DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
 635         DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
 636         DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
 637         DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
 638         DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
 639         DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
 640         DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
 641         DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
 642         DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
 643         DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
 644 };
 645
 646 static struct platform_device irqpin1_device = {
 647         .name           = "renesas_intc_irqpin",
 648         .id             = 1,
 649         .resource       = irqpin1_resources,
 650         .num_resources  = ARRAY_SIZE(irqpin1_resources),
 651         .dev            = {
 652                 .platform_data  = &irqpin1_platform_data,
 653         },
 654 };
 655
 656 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
 657         .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
 658 };
 659
 660 static struct resource irqpin2_resources[] = {
 661         DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
 662         DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
 663         DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
 664         DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
 665         DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
 666         DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
 667         DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
 668         DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
 669         DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
 670         DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
 671         DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
 672         DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
 673         DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
 674 };
 675
 676 static struct platform_device irqpin2_device = {
 677         .name           = "renesas_intc_irqpin",
 678         .id             = 2,
 679         .resource       = irqpin2_resources,
 680         .num_resources  = ARRAY_SIZE(irqpin2_resources),
 681         .dev            = {
 682                 .platform_data  = &irqpin2_platform_data,
 683         },
 684 };
 685
 686 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
 687         .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
 688 };
 689
 690 static struct resource irqpin3_resources[] = {
 691         DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
 692         DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
 693         DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
 694         DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
 695         DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
 696         DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
 697         DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
 698         DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
 699         DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
 700         DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
 701         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
 702         DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
 703         DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
 704 };
 705
 706 static struct platform_device irqpin3_device = {
 707         .name           = "renesas_intc_irqpin",
 708         .id             = 3,
 709         .resource       = irqpin3_resources,
 710         .num_resources  = ARRAY_SIZE(irqpin3_resources),
 711         .dev            = {
 712                 .platform_data  = &irqpin3_platform_data,
 713         },
 714 };
 715
 716 static struct platform_device *sh73a0_early_devices[] __initdata = {
 717         &scif0_device,
 718         &scif1_device,
 719         &scif2_device,
 720         &scif3_device,
 721         &scif4_device,
 722         &scif5_device,
 723         &scif6_device,
 724         &scif7_device,
 725         &scif8_device,
 726         &tmu0_device,
 727         &ipmmu_device,
 728         &cmt1_device,
 729 };
 730
 731 static struct platform_device *sh73a0_late_devices[] __initdata = {
 732         &i2c0_device,
 733         &i2c1_device,
 734         &i2c2_device,
 735         &i2c3_device,
 736         &i2c4_device,
 737         &dma0_device,
 738         &mpdma0_device,
 739         &pmu_device,
 740         &irqpin0_device,
 741         &irqpin1_device,
 742         &irqpin2_device,
 743         &irqpin3_device,
 744 };
 745
 746 #define SRCR2          IOMEM(0xe61580b0)
 747
 748 void __init sh73a0_add_standard_devices(void)
 749 {
 750         /* Clear software reset bit on SY-DMAC module */
 751         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 752
 753         platform_add_devices(sh73a0_early_devices,
 754                             ARRAY_SIZE(sh73a0_early_devices));
 755         platform_add_devices(sh73a0_late_devices,
 756                             ARRAY_SIZE(sh73a0_late_devices));
 757 }
 758
 759 void __init sh73a0_init_delay(void)
 760 {
 761         shmobile_init_delay();
 762 }
 763
 764 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 765 void __init __weak sh73a0_register_twd(void) { }
 766
 767 void __init sh73a0_earlytimer_init(void)
 768 {
 769         sh73a0_init_delay();
 770         sh73a0_clock_init();
 771         shmobile_earlytimer_init();
 772         sh73a0_register_twd();
 773 }
 774
 775 void __init sh73a0_add_early_devices(void)
 776 {
 777         early_platform_add_devices(sh73a0_early_devices,
 778                                    ARRAY_SIZE(sh73a0_early_devices));
 779
 780         /* setup early console here as well */
 781         shmobile_setup_console();
 782 }
 783
 784 #ifdef CONFIG_USE_OF
 785
 786 void __init sh73a0_add_standard_devices_dt(void)
 787 {
 788         /* clocks are setup late during boot in the case of DT */
 789         sh73a0_clock_init();
 790
 791         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 792 }
 793
 794 static const char *sh73a0_boards_compat_dt[] __initdata = {
 795         "renesas,sh73a0",
 796         NULL,
 797 };
 798
 799 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
 800         .smp            = smp_ops(sh73a0_smp_ops),
 801         .map_io         = sh73a0_map_io,
 802         .init_early     = sh73a0_init_delay,
 803         .init_machine   = sh73a0_add_standard_devices_dt,
 804         .init_late      = shmobile_init_late,
 805         .dt_compat      = sh73a0_boards_compat_dt,
 806 MACHINE_END
 807 #endif /* CONFIG_USE_OF */