arch/arm/mach-shmobile/setup-sh73a0.c

   1 /*
   2  * sh73a0 processor support
   3  *
   4  * Copyright (C) 2010  Takashi Yoshii
   5  * Copyright (C) 2010  Magnus Damm
   6  * Copyright (C) 2008  Yoshihiro Shimoda
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/delay.h>
  28 #include <linux/input.h>
  29 #include <linux/io.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/platform_data/sh_ipmmu.h>
  34 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  35
  36 #include <asm/mach-types.h>
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/arch.h>
  39 #include <asm/mach/time.h>
  40
  41 #include "common.h"
  42 #include "dma-register.h"
  43 #include "intc.h"
  44 #include "irqs.h"
  45 #include "sh73a0.h"
  46
  47 static struct map_desc sh73a0_io_desc[] __initdata = {
  48         /* create a 1:1 entity map for 0xe6xxxxxx
  49          * used by CPGA, INTC and PFC.
  50          */
  51         {
  52                 .virtual        = 0xe6000000,
  53                 .pfn            = __phys_to_pfn(0xe6000000),
  54                 .length         = 256 << 20,
  55                 .type           = MT_DEVICE_NONSHARED
  56         },
  57 };
  58
  59 void __init sh73a0_map_io(void)
  60 {
  61         debug_ll_io_init();
  62         iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
  63 }
  64
  65 /* PFC */
  66 static struct resource pfc_resources[] __initdata = {
  67         DEFINE_RES_MEM(0xe6050000, 0x8000),
  68         DEFINE_RES_MEM(0xe605801c, 0x000c),
  69 };
  70
  71 void __init sh73a0_pinmux_init(void)
  72 {
  73         platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
  74                                         ARRAY_SIZE(pfc_resources));
  75 }
  76
  77 /* SCIF */
  78 #define SH73A0_SCIF(scif_type, index, baseaddr, irq)            \
  79 static struct plat_sci_port scif##index##_platform_data = {     \
  80         .type           = scif_type,                            \
  81         .flags          = UPF_BOOT_AUTOCONF,                    \
  82         .scscr          = SCSCR_RE | SCSCR_TE,                  \
  83 };                                                              \
  84                                                                 \
  85 static struct resource scif##index##_resources[] = {            \
  86         DEFINE_RES_MEM(baseaddr, 0x100),                        \
  87         DEFINE_RES_IRQ(irq),                                    \
  88 };                                                              \
  89                                                                 \
  90 static struct platform_device scif##index##_device = {          \
  91         .name           = "sh-sci",                             \
  92         .id             = index,                                \
  93         .resource       = scif##index##_resources,              \
  94         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
  95         .dev            = {                                     \
  96                 .platform_data  = &scif##index##_platform_data, \
  97         },                                                      \
  98 }
  99
 100 SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
 101 SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
 102 SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
 103 SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
 104 SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
 105 SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
 106 SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
 107 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
 108 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
 109
 110 static struct sh_timer_config cmt1_platform_data = {
 111         .channels_mask = 0x3f,
 112 };
 113
 114 static struct resource cmt1_resources[] = {
 115         DEFINE_RES_MEM(0xe6138000, 0x200),
 116         DEFINE_RES_IRQ(gic_spi(65)),
 117 };
 118
 119 static struct platform_device cmt1_device = {
 120         .name           = "sh-cmt-48",
 121         .id             = 1,
 122         .dev = {
 123                 .platform_data  = &cmt1_platform_data,
 124         },
 125         .resource       = cmt1_resources,
 126         .num_resources  = ARRAY_SIZE(cmt1_resources),
 127 };
 128
 129 /* TMU */
 130 static struct sh_timer_config tmu0_platform_data = {
 131         .channels_mask = 7,
 132 };
 133
 134 static struct resource tmu0_resources[] = {
 135         DEFINE_RES_MEM(0xfff60000, 0x2c),
 136         DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
 137         DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
 138         DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
 139 };
 140
 141 static struct platform_device tmu0_device = {
 142         .name           = "sh-tmu",
 143         .id             = 0,
 144         .dev = {
 145                 .platform_data  = &tmu0_platform_data,
 146         },
 147         .resource       = tmu0_resources,
 148         .num_resources  = ARRAY_SIZE(tmu0_resources),
 149 };
 150
 151 static struct resource i2c0_resources[] = {
 152         [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
 153         [1] = {
 154                 .start  = gic_spi(167),
 155                 .end    = gic_spi(170),
 156                 .flags  = IORESOURCE_IRQ,
 157         },
 158 };
 159
 160 static struct resource i2c1_resources[] = {
 161         [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
 162         [1] = {
 163                 .start  = gic_spi(51),
 164                 .end    = gic_spi(54),
 165                 .flags  = IORESOURCE_IRQ,
 166         },
 167 };
 168
 169 static struct resource i2c2_resources[] = {
 170         [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
 171         [1] = {
 172                 .start  = gic_spi(171),
 173                 .end    = gic_spi(174),
 174                 .flags  = IORESOURCE_IRQ,
 175         },
 176 };
 177
 178 static struct resource i2c3_resources[] = {
 179         [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
 180         [1] = {
 181                 .start  = gic_spi(183),
 182                 .end    = gic_spi(186),
 183                 .flags  = IORESOURCE_IRQ,
 184         },
 185 };
 186
 187 static struct resource i2c4_resources[] = {
 188         [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
 189         [1] = {
 190                 .start  = gic_spi(187),
 191                 .end    = gic_spi(190),
 192                 .flags  = IORESOURCE_IRQ,
 193         },
 194 };
 195
 196 static struct platform_device i2c0_device = {
 197         .name           = "i2c-sh_mobile",
 198         .id             = 0,
 199         .resource       = i2c0_resources,
 200         .num_resources  = ARRAY_SIZE(i2c0_resources),
 201 };
 202
 203 static struct platform_device i2c1_device = {
 204         .name           = "i2c-sh_mobile",
 205         .id             = 1,
 206         .resource       = i2c1_resources,
 207         .num_resources  = ARRAY_SIZE(i2c1_resources),
 208 };
 209
 210 static struct platform_device i2c2_device = {
 211         .name           = "i2c-sh_mobile",
 212         .id             = 2,
 213         .resource       = i2c2_resources,
 214         .num_resources  = ARRAY_SIZE(i2c2_resources),
 215 };
 216
 217 static struct platform_device i2c3_device = {
 218         .name           = "i2c-sh_mobile",
 219         .id             = 3,
 220         .resource       = i2c3_resources,
 221         .num_resources  = ARRAY_SIZE(i2c3_resources),
 222 };
 223
 224 static struct platform_device i2c4_device = {
 225         .name           = "i2c-sh_mobile",
 226         .id             = 4,
 227         .resource       = i2c4_resources,
 228         .num_resources  = ARRAY_SIZE(i2c4_resources),
 229 };
 230
 231 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
 232         {
 233                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 234                 .addr           = 0xe6c40020,
 235                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 236                 .mid_rid        = 0x21,
 237         }, {
 238                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 239                 .addr           = 0xe6c40024,
 240                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 241                 .mid_rid        = 0x22,
 242         }, {
 243                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 244                 .addr           = 0xe6c50020,
 245                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 246                 .mid_rid        = 0x25,
 247         }, {
 248                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 249                 .addr           = 0xe6c50024,
 250                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 251                 .mid_rid        = 0x26,
 252         }, {
 253                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 254                 .addr           = 0xe6c60020,
 255                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 256                 .mid_rid        = 0x29,
 257         }, {
 258                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 259                 .addr           = 0xe6c60024,
 260                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 261                 .mid_rid        = 0x2a,
 262         }, {
 263                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 264                 .addr           = 0xe6c70020,
 265                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 266                 .mid_rid        = 0x2d,
 267         }, {
 268                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 269                 .addr           = 0xe6c70024,
 270                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 271                 .mid_rid        = 0x2e,
 272         }, {
 273                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 274                 .addr           = 0xe6c80020,
 275                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 276                 .mid_rid        = 0x39,
 277         }, {
 278                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 279                 .addr           = 0xe6c80024,
 280                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 281                 .mid_rid        = 0x3a,
 282         }, {
 283                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 284                 .addr           = 0xe6cb0020,
 285                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 286                 .mid_rid        = 0x35,
 287         }, {
 288                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 289                 .addr           = 0xe6cb0024,
 290                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 291                 .mid_rid        = 0x36,
 292         }, {
 293                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 294                 .addr           = 0xe6cc0020,
 295                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 296                 .mid_rid        = 0x1d,
 297         }, {
 298                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 299                 .addr           = 0xe6cc0024,
 300                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 301                 .mid_rid        = 0x1e,
 302         }, {
 303                 .slave_id       = SHDMA_SLAVE_SCIF7_TX,
 304                 .addr           = 0xe6cd0020,
 305                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 306                 .mid_rid        = 0x19,
 307         }, {
 308                 .slave_id       = SHDMA_SLAVE_SCIF7_RX,
 309                 .addr           = 0xe6cd0024,
 310                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 311                 .mid_rid        = 0x1a,
 312         }, {
 313                 .slave_id       = SHDMA_SLAVE_SCIF8_TX,
 314                 .addr           = 0xe6c30040,
 315                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 316                 .mid_rid        = 0x3d,
 317         }, {
 318                 .slave_id       = SHDMA_SLAVE_SCIF8_RX,
 319                 .addr           = 0xe6c30060,
 320                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 321                 .mid_rid        = 0x3e,
 322         }, {
 323                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 324                 .addr           = 0xee100030,
 325                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 326                 .mid_rid        = 0xc1,
 327         }, {
 328                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 329                 .addr           = 0xee100030,
 330                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 331                 .mid_rid        = 0xc2,
 332         }, {
 333                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 334                 .addr           = 0xee120030,
 335                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 336                 .mid_rid        = 0xc9,
 337         }, {
 338                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 339                 .addr           = 0xee120030,
 340                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 341                 .mid_rid        = 0xca,
 342         }, {
 343                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 344                 .addr           = 0xee140030,
 345                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 346                 .mid_rid        = 0xcd,
 347         }, {
 348                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 349                 .addr           = 0xee140030,
 350                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 351                 .mid_rid        = 0xce,
 352         }, {
 353                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 354                 .addr           = 0xe6bd0034,
 355                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 356                 .mid_rid        = 0xd1,
 357         }, {
 358                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 359                 .addr           = 0xe6bd0034,
 360                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 361                 .mid_rid        = 0xd2,
 362         },
 363 };
 364
 365 #define DMAE_CHANNEL(_offset)                                   \
 366         {                                                       \
 367                 .offset         = _offset - 0x20,               \
 368                 .dmars          = _offset - 0x20 + 0x40,        \
 369         }
 370
 371 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
 372         DMAE_CHANNEL(0x8000),
 373         DMAE_CHANNEL(0x8080),
 374         DMAE_CHANNEL(0x8100),
 375         DMAE_CHANNEL(0x8180),
 376         DMAE_CHANNEL(0x8200),
 377         DMAE_CHANNEL(0x8280),
 378         DMAE_CHANNEL(0x8300),
 379         DMAE_CHANNEL(0x8380),
 380         DMAE_CHANNEL(0x8400),
 381         DMAE_CHANNEL(0x8480),
 382         DMAE_CHANNEL(0x8500),
 383         DMAE_CHANNEL(0x8580),
 384         DMAE_CHANNEL(0x8600),
 385         DMAE_CHANNEL(0x8680),
 386         DMAE_CHANNEL(0x8700),
 387         DMAE_CHANNEL(0x8780),
 388         DMAE_CHANNEL(0x8800),
 389         DMAE_CHANNEL(0x8880),
 390         DMAE_CHANNEL(0x8900),
 391         DMAE_CHANNEL(0x8980),
 392 };
 393
 394 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 395         .slave          = sh73a0_dmae_slaves,
 396         .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
 397         .channel        = sh73a0_dmae_channels,
 398         .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
 399         .ts_low_shift   = TS_LOW_SHIFT,
 400         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 401         .ts_high_shift  = TS_HI_SHIFT,
 402         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 403         .ts_shift       = dma_ts_shift,
 404         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 405         .dmaor_init     = DMAOR_DME,
 406 };
 407
 408 static struct resource sh73a0_dmae_resources[] = {
 409         DEFINE_RES_MEM(0xfe000020, 0x89e0),
 410         {
 411                 .name   = "error_irq",
 412                 .start  = gic_spi(129),
 413                 .end    = gic_spi(129),
 414                 .flags  = IORESOURCE_IRQ,
 415         },
 416         {
 417                 /* IRQ for channels 0-19 */
 418                 .start  = gic_spi(109),
 419                 .end    = gic_spi(128),
 420                 .flags  = IORESOURCE_IRQ,
 421         },
 422 };
 423
 424 static struct platform_device dma0_device = {
 425         .name           = "sh-dma-engine",
 426         .id             = 0,
 427         .resource       = sh73a0_dmae_resources,
 428         .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
 429         .dev            = {
 430                 .platform_data  = &sh73a0_dmae_platform_data,
 431         },
 432 };
 433
 434 /* MPDMAC */
 435 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
 436         {
 437                 .slave_id       = SHDMA_SLAVE_FSI2A_RX,
 438                 .addr           = 0xec230020,
 439                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 440                 .mid_rid        = 0xd6, /* CHECK ME */
 441         }, {
 442                 .slave_id       = SHDMA_SLAVE_FSI2A_TX,
 443                 .addr           = 0xec230024,
 444                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 445                 .mid_rid        = 0xd5, /* CHECK ME */
 446         }, {
 447                 .slave_id       = SHDMA_SLAVE_FSI2C_RX,
 448                 .addr           = 0xec230060,
 449                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 450                 .mid_rid        = 0xda, /* CHECK ME */
 451         }, {
 452                 .slave_id       = SHDMA_SLAVE_FSI2C_TX,
 453                 .addr           = 0xec230064,
 454                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 455                 .mid_rid        = 0xd9, /* CHECK ME */
 456         }, {
 457                 .slave_id       = SHDMA_SLAVE_FSI2B_RX,
 458                 .addr           = 0xec240020,
 459                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 460                 .mid_rid        = 0x8e, /* CHECK ME */
 461         }, {
 462                 .slave_id       = SHDMA_SLAVE_FSI2B_TX,
 463                 .addr           = 0xec240024,
 464                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 465                 .mid_rid        = 0x8d, /* CHECK ME */
 466         }, {
 467                 .slave_id       = SHDMA_SLAVE_FSI2D_RX,
 468                 .addr           =  0xec240060,
 469                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 470                 .mid_rid        = 0x9a, /* CHECK ME */
 471         },
 472 };
 473
 474 #define MPDMA_CHANNEL(a, b, c)                  \
 475 {                                               \
 476         .offset         = a,                    \
 477         .dmars          = b,                    \
 478         .dmars_bit      = c,                    \
 479         .chclr_offset   = (0x220 - 0x20) + a    \
 480 }
 481
 482 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
 483         MPDMA_CHANNEL(0x00, 0, 0),
 484         MPDMA_CHANNEL(0x10, 0, 8),
 485         MPDMA_CHANNEL(0x20, 4, 0),
 486         MPDMA_CHANNEL(0x30, 4, 8),
 487         MPDMA_CHANNEL(0x50, 8, 0),
 488         MPDMA_CHANNEL(0x70, 8, 8),
 489 };
 490
 491 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 492         .slave          = sh73a0_mpdma_slaves,
 493         .slave_num      = ARRAY_SIZE(sh73a0_mpdma_slaves),
 494         .channel        = sh73a0_mpdma_channels,
 495         .channel_num    = ARRAY_SIZE(sh73a0_mpdma_channels),
 496         .ts_low_shift   = TS_LOW_SHIFT,
 497         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 498         .ts_high_shift  = TS_HI_SHIFT,
 499         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 500         .ts_shift       = dma_ts_shift,
 501         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 502         .dmaor_init     = DMAOR_DME,
 503         .chclr_present  = 1,
 504 };
 505
 506 /* Resource order important! */
 507 static struct resource sh73a0_mpdma_resources[] = {
 508         /* Channel registers and DMAOR */
 509         DEFINE_RES_MEM(0xec618020, 0x270),
 510         /* DMARSx */
 511         DEFINE_RES_MEM(0xec619000, 0xc),
 512         {
 513                 .name   = "error_irq",
 514                 .start  = gic_spi(181),
 515                 .end    = gic_spi(181),
 516                 .flags  = IORESOURCE_IRQ,
 517         },
 518         {
 519                 /* IRQ for channels 0-5 */
 520                 .start  = gic_spi(175),
 521                 .end    = gic_spi(180),
 522                 .flags  = IORESOURCE_IRQ,
 523         },
 524 };
 525
 526 static struct platform_device mpdma0_device = {
 527         .name           = "sh-dma-engine",
 528         .id             = 1,
 529         .resource       = sh73a0_mpdma_resources,
 530         .num_resources  = ARRAY_SIZE(sh73a0_mpdma_resources),
 531         .dev            = {
 532                 .platform_data  = &sh73a0_mpdma_platform_data,
 533         },
 534 };
 535
 536 static struct resource pmu_resources[] = {
 537         [0] = {
 538                 .start  = gic_spi(55),
 539                 .end    = gic_spi(55),
 540                 .flags  = IORESOURCE_IRQ,
 541         },
 542         [1] = {
 543                 .start  = gic_spi(56),
 544                 .end    = gic_spi(56),
 545                 .flags  = IORESOURCE_IRQ,
 546         },
 547 };
 548
 549 static struct platform_device pmu_device = {
 550         .name           = "arm-pmu",
 551         .id             = -1,
 552         .num_resources  = ARRAY_SIZE(pmu_resources),
 553         .resource       = pmu_resources,
 554 };
 555
 556 /* an IPMMU module for ICB */
 557 static struct resource ipmmu_resources[] = {
 558         DEFINE_RES_MEM(0xfe951000, 0x100),
 559 };
 560
 561 static const char * const ipmmu_dev_names[] = {
 562         "sh_mobile_lcdc_fb.0",
 563 };
 564
 565 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 566         .dev_names = ipmmu_dev_names,
 567         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 568 };
 569
 570 static struct platform_device ipmmu_device = {
 571         .name           = "ipmmu",
 572         .id             = -1,
 573         .dev = {
 574                 .platform_data = &ipmmu_platform_data,
 575         },
 576         .resource       = ipmmu_resources,
 577         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 578 };
 579
 580 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
 581         .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
 582 };
 583
 584 static struct resource irqpin0_resources[] = {
 585         DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
 586         DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
 587         DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
 588         DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
 589         DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
 590         DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
 591         DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
 592         DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
 593         DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
 594         DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
 595         DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
 596         DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
 597         DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
 598 };
 599
 600 static struct platform_device irqpin0_device = {
 601         .name           = "renesas_intc_irqpin",
 602         .id             = 0,
 603         .resource       = irqpin0_resources,
 604         .num_resources  = ARRAY_SIZE(irqpin0_resources),
 605         .dev            = {
 606                 .platform_data  = &irqpin0_platform_data,
 607         },
 608 };
 609
 610 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
 611         .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
 612         .control_parent = true, /* Disable spurious IRQ10 */
 613 };
 614
 615 static struct resource irqpin1_resources[] = {
 616         DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
 617         DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
 618         DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
 619         DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
 620         DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
 621         DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
 622         DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
 623         DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
 624         DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
 625         DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
 626         DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
 627         DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
 628         DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
 629 };
 630
 631 static struct platform_device irqpin1_device = {
 632         .name           = "renesas_intc_irqpin",
 633         .id             = 1,
 634         .resource       = irqpin1_resources,
 635         .num_resources  = ARRAY_SIZE(irqpin1_resources),
 636         .dev            = {
 637                 .platform_data  = &irqpin1_platform_data,
 638         },
 639 };
 640
 641 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
 642         .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
 643 };
 644
 645 static struct resource irqpin2_resources[] = {
 646         DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
 647         DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
 648         DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
 649         DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
 650         DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
 651         DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
 652         DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
 653         DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
 654         DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
 655         DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
 656         DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
 657         DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
 658         DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
 659 };
 660
 661 static struct platform_device irqpin2_device = {
 662         .name           = "renesas_intc_irqpin",
 663         .id             = 2,
 664         .resource       = irqpin2_resources,
 665         .num_resources  = ARRAY_SIZE(irqpin2_resources),
 666         .dev            = {
 667                 .platform_data  = &irqpin2_platform_data,
 668         },
 669 };
 670
 671 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
 672         .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
 673 };
 674
 675 static struct resource irqpin3_resources[] = {
 676         DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
 677         DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
 678         DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
 679         DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
 680         DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
 681         DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
 682         DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
 683         DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
 684         DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
 685         DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
 686         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
 687         DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
 688         DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
 689 };
 690
 691 static struct platform_device irqpin3_device = {
 692         .name           = "renesas_intc_irqpin",
 693         .id             = 3,
 694         .resource       = irqpin3_resources,
 695         .num_resources  = ARRAY_SIZE(irqpin3_resources),
 696         .dev            = {
 697                 .platform_data  = &irqpin3_platform_data,
 698         },
 699 };
 700
 701 static struct platform_device *sh73a0_early_devices[] __initdata = {
 702         &scif0_device,
 703         &scif1_device,
 704         &scif2_device,
 705         &scif3_device,
 706         &scif4_device,
 707         &scif5_device,
 708         &scif6_device,
 709         &scif7_device,
 710         &scif8_device,
 711         &tmu0_device,
 712         &ipmmu_device,
 713         &cmt1_device,
 714 };
 715
 716 static struct platform_device *sh73a0_late_devices[] __initdata = {
 717         &i2c0_device,
 718         &i2c1_device,
 719         &i2c2_device,
 720         &i2c3_device,
 721         &i2c4_device,
 722         &dma0_device,
 723         &mpdma0_device,
 724         &pmu_device,
 725         &irqpin0_device,
 726         &irqpin1_device,
 727         &irqpin2_device,
 728         &irqpin3_device,
 729 };
 730
 731 #define SRCR2          IOMEM(0xe61580b0)
 732
 733 void __init sh73a0_add_standard_devices(void)
 734 {
 735         /* Clear software reset bit on SY-DMAC module */
 736         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 737
 738         platform_add_devices(sh73a0_early_devices,
 739                             ARRAY_SIZE(sh73a0_early_devices));
 740         platform_add_devices(sh73a0_late_devices,
 741                             ARRAY_SIZE(sh73a0_late_devices));
 742 }
 743
 744 void __init sh73a0_init_delay(void)
 745 {
 746         shmobile_init_delay();
 747 }
 748
 749 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 750 void __init __weak sh73a0_register_twd(void) { }
 751
 752 void __init sh73a0_earlytimer_init(void)
 753 {
 754         sh73a0_init_delay();
 755         sh73a0_clock_init();
 756         shmobile_earlytimer_init();
 757         sh73a0_register_twd();
 758 }
 759
 760 void __init sh73a0_add_early_devices(void)
 761 {
 762         early_platform_add_devices(sh73a0_early_devices,
 763                                    ARRAY_SIZE(sh73a0_early_devices));
 764
 765         /* setup early console here as well */
 766         shmobile_setup_console();
 767 }
 768
 769 #ifdef CONFIG_USE_OF
 770
 771 void __init sh73a0_add_standard_devices_dt(void)
 772 {
 773         /* clocks are setup late during boot in the case of DT */
 774         sh73a0_clock_init();
 775
 776         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 777 }
 778
 779 #define RESCNT2 IOMEM(0xe6188020)
 780 static void sh73a0_restart(enum reboot_mode mode, const char *cmd)
 781 {
 782         /* Do soft power on reset */
 783         writel((1 << 31), RESCNT2);
 784 }
 785
 786 static const char *sh73a0_boards_compat_dt[] __initdata = {
 787         "renesas,sh73a0",
 788         NULL,
 789 };
 790
 791 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
 792         .smp            = smp_ops(sh73a0_smp_ops),
 793         .map_io         = sh73a0_map_io,
 794         .init_early     = sh73a0_init_delay,
 795         .init_machine   = sh73a0_add_standard_devices_dt,
 796         .init_late      = shmobile_init_late,
 797         .restart        = sh73a0_restart,
 798         .dt_compat      = sh73a0_boards_compat_dt,
 799 MACHINE_END
 800 #endif /* CONFIG_USE_OF */