2 * linux/arch/arm/mm/proc-v7.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv7 processor support.
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #ifdef CONFIG_ARM_LPAE
23 #include "proc-v7-3level.S"
25 #include "proc-v7-2level.S"
28 ENTRY(cpu_v7_proc_init)
30 ENDPROC(cpu_v7_proc_init)
32 ENTRY(cpu_v7_proc_fin)
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
38 ENDPROC(cpu_v7_proc_fin)
43 * Perform a soft reset of the system. Put the CPU into the
44 * same state as it would be if it had been reset, and branch
45 * to what would be the reset vector.
47 * - loc - location to jump to for soft reset
49 * This code must be executed using a flat identity mapping with
53 .pushsection .idmap.text, "ax"
55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
56 bic r1, r1, #0x1 @ ...............m
57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
67 * Idle the processor (eg, wait for interrupt).
69 * IRQs are already disabled.
72 dsb @ WFI may enter a low-power mode
75 ENDPROC(cpu_v7_do_idle)
77 ENTRY(cpu_v7_dcache_clean_area)
78 #ifndef TLB_CAN_READ_FROM_L1_CACHE
79 dcache_line_size r2, r3
80 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
87 ENDPROC(cpu_v7_dcache_clean_area)
89 string cpu_v7_name, "ARMv7 Processor"
92 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
93 .globl cpu_v7_suspend_size
94 .equ cpu_v7_suspend_size, 4 * 8
95 #ifdef CONFIG_ARM_CPU_SUSPEND
96 ENTRY(cpu_v7_do_suspend)
97 stmfd sp!, {r4 - r10, lr}
98 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
99 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
101 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
102 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
103 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
104 mrc p15, 0, r8, c1, c0, 0 @ Control register
105 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
106 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
108 ldmfd sp!, {r4 - r10, pc}
109 ENDPROC(cpu_v7_do_suspend)
111 ENTRY(cpu_v7_do_resume)
113 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
114 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
115 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
117 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
118 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
120 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
121 #ifndef CONFIG_ARM_LPAE
122 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
123 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
125 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
126 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
127 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
128 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
129 teq r4, r9 @ Is it already set?
130 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
131 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
134 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
135 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
138 mov r0, r8 @ control register
140 ENDPROC(cpu_v7_do_resume)
148 * Initialise TLB, Caches, and MMU state ready to switch the MMU
149 * on. Return in r0 the new CP15 C1 control register setting.
151 * This should be able to cover all ARMv7 cores.
153 * It is assumed that:
154 * - cache type register is implemented
158 mov r10, #(1 << 0) @ TLB ops broadcasting
165 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
166 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
167 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
168 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
169 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
170 mcreq p15, 0, r0, c1, c0, 1
174 #ifdef CONFIG_CPU_PJ4B
176 /* Auxiliary Debug Modes Control 1 Register */
177 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
178 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
179 #define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
180 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
182 /* Auxiliary Debug Modes Control 2 Register */
183 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
184 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
185 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
186 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
187 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
188 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
189 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
191 /* Auxiliary Functional Modes Control Register 0 */
192 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
193 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
194 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
196 /* Auxiliary Debug Modes Control 0 Register */
197 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
199 /* Auxiliary Debug Modes Control 1 Register */
200 mrc p15, 1, r0, c15, c1, 1
201 orr r0, r0, #PJ4B_CLEAN_LINE
202 orr r0, r0, #PJ4B_BCK_OFF_STREX
203 orr r0, r0, #PJ4B_INTER_PARITY
204 bic r0, r0, #PJ4B_STATIC_BP
205 mcr p15, 1, r0, c15, c1, 1
207 /* Auxiliary Debug Modes Control 2 Register */
208 mrc p15, 1, r0, c15, c1, 2
209 bic r0, r0, #PJ4B_FAST_LDR
210 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
211 mcr p15, 1, r0, c15, c1, 2
213 /* Auxiliary Functional Modes Control Register 0 */
214 mrc p15, 1, r0, c15, c2, 0
216 orr r0, r0, #PJ4B_SMP_CFB
218 orr r0, r0, #PJ4B_L1_PAR_CHK
219 orr r0, r0, #PJ4B_BROADCAST_CACHE
220 mcr p15, 1, r0, c15, c2, 0
222 /* Auxiliary Debug Modes Control 0 Register */
223 mrc p15, 1, r0, c15, c1, 0
224 orr r0, r0, #PJ4B_WFI_WFE
225 mcr p15, 1, r0, c15, c1, 0
227 #endif /* CONFIG_CPU_PJ4B */
230 adr r12, __v7_setup_stack @ the local stack
231 stmia r12, {r0-r5, r7, r9, r11, lr}
232 bl v7_flush_dcache_louis
233 ldmia r12, {r0-r5, r7, r9, r11, lr}
235 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
236 and r10, r0, #0xff000000 @ ARM?
239 and r5, r0, #0x00f00000 @ variant
240 and r6, r0, #0x0000000f @ revision
241 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
242 ubfx r0, r0, #4, #12 @ primary part number
244 /* Cortex-A8 Errata */
245 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
248 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
250 teq r5, #0x00100000 @ only present in r1p*
251 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
252 orreq r10, r10, #(1 << 6) @ set IBE to 1
253 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
255 #ifdef CONFIG_ARM_ERRATA_458693
256 teq r6, #0x20 @ only present in r2p0
257 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
258 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
259 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
260 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
262 #ifdef CONFIG_ARM_ERRATA_460075
263 teq r6, #0x20 @ only present in r2p0
264 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
266 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
267 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
271 /* Cortex-A9 Errata */
272 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
275 #ifdef CONFIG_ARM_ERRATA_742230
276 cmp r6, #0x22 @ only present up to r2p2
277 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
278 orrle r10, r10, #1 << 4 @ set bit #4
279 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
281 #ifdef CONFIG_ARM_ERRATA_742231
282 teq r6, #0x20 @ present in r2p0
283 teqne r6, #0x21 @ present in r2p1
284 teqne r6, #0x22 @ present in r2p2
285 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
286 orreq r10, r10, #1 << 12 @ set bit #12
287 orreq r10, r10, #1 << 22 @ set bit #22
288 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
290 #ifdef CONFIG_ARM_ERRATA_743622
291 teq r5, #0x00200000 @ only present in r2p*
292 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
293 orreq r10, r10, #1 << 6 @ set bit #6
294 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
296 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
297 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
299 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
300 orrlt r10, r10, #1 << 11 @ set bit #11
301 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
306 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
309 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
310 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
313 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
314 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
316 #ifndef CONFIG_ARM_THUMBEE
317 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
318 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
319 teq r0, #(1 << 12) @ check if ThumbEE is present
322 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
323 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
324 orr r0, r0, #1 @ set the 1st bit in order to
325 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
330 #ifdef CONFIG_CPU_ENDIAN_BE8
331 orr r6, r6, #1 << 25 @ big-endian page tables
333 #ifdef CONFIG_SWP_EMULATE
334 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
335 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
337 mrc p15, 0, r0, c1, c0, 0 @ read control register
338 bic r0, r0, r5 @ clear bits them
339 orr r0, r0, r6 @ set them
340 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
341 mov pc, lr @ return to head.S:__ret
346 .space 4 * 11 @ 11 registers
350 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
351 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
355 string cpu_arch_name, "armv7"
356 string cpu_elf_name, "v7"
359 .section ".proc.info.init", #alloc, #execinstr
362 * Standard v7 proc info content
364 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
365 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
366 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
367 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
368 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
369 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
370 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
374 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
375 HWCAP_EDSP | HWCAP_TLS | \hwcaps
377 .long v7_processor_functions
383 #ifndef CONFIG_ARM_LPAE
385 * ARM Ltd. Cortex A5 processor.
387 .type __v7_ca5mp_proc_info, #object
388 __v7_ca5mp_proc_info:
391 __v7_proc __v7_ca5mp_setup
392 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
395 * ARM Ltd. Cortex A9 processor.
397 .type __v7_ca9mp_proc_info, #object
398 __v7_ca9mp_proc_info:
401 __v7_proc __v7_ca9mp_setup
402 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
405 * Marvell PJ4B processor.
407 .type __v7_pj4b_proc_info, #object
411 __v7_proc __v7_pj4b_setup
412 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
413 #endif /* CONFIG_ARM_LPAE */
416 * ARM Ltd. Cortex A7 processor.
418 .type __v7_ca7mp_proc_info, #object
419 __v7_ca7mp_proc_info:
422 __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
423 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
426 * ARM Ltd. Cortex A15 processor.
428 .type __v7_ca15mp_proc_info, #object
429 __v7_ca15mp_proc_info:
432 __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
433 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
436 * Match any ARMv7 processor core.
438 .type __v7_proc_info, #object
440 .long 0x000f0000 @ Required ID value
441 .long 0x000f0000 @ Mask for ID
443 .size __v7_proc_info, . - __v7_proc_info