2 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 compatible = "apm,xgene-storm";
14 interrupt-parent = <&gic>;
24 compatible = "apm,potenza", "arm,armv8";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
31 compatible = "apm,potenza", "arm,armv8";
33 enable-method = "spin-table";
34 cpu-release-addr = <0x1 0x0000fff8>;
38 compatible = "apm,potenza", "arm,armv8";
40 enable-method = "spin-table";
41 cpu-release-addr = <0x1 0x0000fff8>;
45 compatible = "apm,potenza", "arm,armv8";
47 enable-method = "spin-table";
48 cpu-release-addr = <0x1 0x0000fff8>;
52 compatible = "apm,potenza", "arm,armv8";
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
59 compatible = "apm,potenza", "arm,armv8";
61 enable-method = "spin-table";
62 cpu-release-addr = <0x1 0x0000fff8>;
66 compatible = "apm,potenza", "arm,armv8";
68 enable-method = "spin-table";
69 cpu-release-addr = <0x1 0x0000fff8>;
73 compatible = "apm,potenza", "arm,armv8";
75 enable-method = "spin-table";
76 cpu-release-addr = <0x1 0x0000fff8>;
80 gic: interrupt-controller@78010000 {
81 compatible = "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
84 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
85 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
86 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
87 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
88 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
92 compatible = "arm,armv8-timer";
93 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
94 <1 13 0xff01>, /* Non-secure Phys IRQ */
95 <1 14 0xff01>, /* Virt IRQ */
96 <1 15 0xff01>; /* Hyp IRQ */
97 clock-frequency = <50000000>;
101 compatible = "simple-bus";
102 #address-cells = <2>;
107 #address-cells = <2>;
111 compatible = "fixed-clock";
113 clock-frequency = <100000000>;
114 clock-output-names = "refclk";
117 pcppll: pcppll@17000100 {
118 compatible = "apm,xgene-pcppll-clock";
120 clocks = <&refclk 0>;
121 clock-names = "pcppll";
122 reg = <0x0 0x17000100 0x0 0x1000>;
123 clock-output-names = "pcppll";
127 socpll: socpll@17000120 {
128 compatible = "apm,xgene-socpll-clock";
130 clocks = <&refclk 0>;
131 clock-names = "socpll";
132 reg = <0x0 0x17000120 0x0 0x1000>;
133 clock-output-names = "socpll";
137 socplldiv2: socplldiv2 {
138 compatible = "fixed-factor-clock";
140 clocks = <&socpll 0>;
141 clock-names = "socplldiv2";
144 clock-output-names = "socplldiv2";
148 compatible = "apm,xgene-device-clock";
150 clocks = <&socplldiv2 0>;
151 clock-names = "qmlclk";
152 reg = <0x0 0x1703C000 0x0 0x1000>;
153 reg-names = "csr-reg";
154 clock-output-names = "qmlclk";
158 compatible = "apm,xgene-device-clock";
160 clocks = <&socplldiv2 0>;
161 clock-names = "ethclk";
162 reg = <0x0 0x17000000 0x0 0x1000>;
163 reg-names = "div-reg";
164 divider-offset = <0x238>;
165 divider-width = <0x9>;
166 divider-shift = <0x0>;
167 clock-output-names = "ethclk";
171 compatible = "apm,xgene-device-clock";
173 clocks = <ðclk 0>;
174 reg = <0x0 0x1702C000 0x0 0x1000>;
175 reg-names = "csr-reg";
176 clock-output-names = "menetclk";
179 sataphy1clk: sataphy1clk@1f21c000 {
180 compatible = "apm,xgene-device-clock";
182 clocks = <&socplldiv2 0>;
183 reg = <0x0 0x1f21c000 0x0 0x1000>;
184 reg-names = "csr-reg";
185 clock-output-names = "sataphy1clk";
189 enable-offset = <0x0>;
190 enable-mask = <0x06>;
193 sataphy2clk: sataphy1clk@1f22c000 {
194 compatible = "apm,xgene-device-clock";
196 clocks = <&socplldiv2 0>;
197 reg = <0x0 0x1f22c000 0x0 0x1000>;
198 reg-names = "csr-reg";
199 clock-output-names = "sataphy2clk";
203 enable-offset = <0x0>;
204 enable-mask = <0x06>;
207 sataphy3clk: sataphy1clk@1f23c000 {
208 compatible = "apm,xgene-device-clock";
210 clocks = <&socplldiv2 0>;
211 reg = <0x0 0x1f23c000 0x0 0x1000>;
212 reg-names = "csr-reg";
213 clock-output-names = "sataphy3clk";
217 enable-offset = <0x0>;
218 enable-mask = <0x06>;
221 sata01clk: sata01clk@1f21c000 {
222 compatible = "apm,xgene-device-clock";
224 clocks = <&socplldiv2 0>;
225 reg = <0x0 0x1f21c000 0x0 0x1000>;
226 reg-names = "csr-reg";
227 clock-output-names = "sata01clk";
230 enable-offset = <0x0>;
231 enable-mask = <0x39>;
234 sata23clk: sata23clk@1f22c000 {
235 compatible = "apm,xgene-device-clock";
237 clocks = <&socplldiv2 0>;
238 reg = <0x0 0x1f22c000 0x0 0x1000>;
239 reg-names = "csr-reg";
240 clock-output-names = "sata23clk";
243 enable-offset = <0x0>;
244 enable-mask = <0x39>;
247 sata45clk: sata45clk@1f23c000 {
248 compatible = "apm,xgene-device-clock";
250 clocks = <&socplldiv2 0>;
251 reg = <0x0 0x1f23c000 0x0 0x1000>;
252 reg-names = "csr-reg";
253 clock-output-names = "sata45clk";
256 enable-offset = <0x0>;
257 enable-mask = <0x39>;
260 rtcclk: rtcclk@17000000 {
261 compatible = "apm,xgene-device-clock";
263 clocks = <&socplldiv2 0>;
264 reg = <0x0 0x17000000 0x0 0x2000>;
265 reg-names = "csr-reg";
268 enable-offset = <0x10>;
270 clock-output-names = "rtcclk";
273 rngpkaclk: rngpkaclk@17000000 {
274 compatible = "apm,xgene-device-clock";
276 clocks = <&socplldiv2 0>;
277 reg = <0x0 0x17000000 0x0 0x2000>;
278 reg-names = "csr-reg";
281 enable-offset = <0x10>;
282 enable-mask = <0x10>;
283 clock-output-names = "rngpkaclk";
286 pcie0clk: pcie0clk@1f2bc000 {
288 compatible = "apm,xgene-device-clock";
290 clocks = <&socplldiv2 0>;
291 reg = <0x0 0x1f2bc000 0x0 0x1000>;
292 reg-names = "csr-reg";
293 clock-output-names = "pcie0clk";
296 pcie1clk: pcie1clk@1f2cc000 {
298 compatible = "apm,xgene-device-clock";
300 clocks = <&socplldiv2 0>;
301 reg = <0x0 0x1f2cc000 0x0 0x1000>;
302 reg-names = "csr-reg";
303 clock-output-names = "pcie1clk";
306 pcie2clk: pcie2clk@1f2dc000 {
308 compatible = "apm,xgene-device-clock";
310 clocks = <&socplldiv2 0>;
311 reg = <0x0 0x1f2dc000 0x0 0x1000>;
312 reg-names = "csr-reg";
313 clock-output-names = "pcie2clk";
316 pcie3clk: pcie3clk@1f50c000 {
318 compatible = "apm,xgene-device-clock";
320 clocks = <&socplldiv2 0>;
321 reg = <0x0 0x1f50c000 0x0 0x1000>;
322 reg-names = "csr-reg";
323 clock-output-names = "pcie3clk";
326 pcie4clk: pcie4clk@1f51c000 {
328 compatible = "apm,xgene-device-clock";
330 clocks = <&socplldiv2 0>;
331 reg = <0x0 0x1f51c000 0x0 0x1000>;
332 reg-names = "csr-reg";
333 clock-output-names = "pcie4clk";
337 pcie0: pcie@1f2b0000 {
340 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
341 #interrupt-cells = <1>;
343 #address-cells = <3>;
344 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
345 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
346 reg-names = "csr", "cfg";
347 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
348 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
349 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
350 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
351 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
352 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
353 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
354 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
355 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
357 clocks = <&pcie0clk 0>;
360 pcie1: pcie@1f2c0000 {
363 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
364 #interrupt-cells = <1>;
366 #address-cells = <3>;
367 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
368 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
369 reg-names = "csr", "cfg";
370 ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
371 0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */
372 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
373 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
374 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
375 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
376 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
377 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
378 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
380 clocks = <&pcie1clk 0>;
383 pcie2: pcie@1f2d0000 {
386 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
387 #interrupt-cells = <1>;
389 #address-cells = <3>;
390 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
391 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
392 reg-names = "csr", "cfg";
393 ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000 /* io */
394 0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */
395 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
396 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
397 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
398 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
399 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
400 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
401 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
403 clocks = <&pcie2clk 0>;
406 pcie3: pcie@1f500000 {
409 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
410 #interrupt-cells = <1>;
412 #address-cells = <3>;
413 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
414 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
415 reg-names = "csr", "cfg";
416 ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000 /* io */
417 0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem */
418 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
419 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
420 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
421 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
422 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
423 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
424 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
426 clocks = <&pcie3clk 0>;
429 pcie4: pcie@1f510000 {
432 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
433 #interrupt-cells = <1>;
435 #address-cells = <3>;
436 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
437 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
438 reg-names = "csr", "cfg";
439 ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000 /* io */
440 0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */
441 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
442 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
443 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
444 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
445 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
446 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
447 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
449 clocks = <&pcie4clk 0>;
452 serial0: serial@1c020000 {
454 device_type = "serial";
455 compatible = "ns16550a";
456 reg = <0 0x1c020000 0x0 0x1000>;
458 clock-frequency = <10000000>; /* Updated by bootloader */
459 interrupt-parent = <&gic>;
460 interrupts = <0x0 0x4c 0x4>;
463 serial1: serial@1c021000 {
465 device_type = "serial";
466 compatible = "ns16550a";
467 reg = <0 0x1c021000 0x0 0x1000>;
469 clock-frequency = <10000000>; /* Updated by bootloader */
470 interrupt-parent = <&gic>;
471 interrupts = <0x0 0x4d 0x4>;
474 serial2: serial@1c022000 {
476 device_type = "serial";
477 compatible = "ns16550a";
478 reg = <0 0x1c022000 0x0 0x1000>;
480 clock-frequency = <10000000>; /* Updated by bootloader */
481 interrupt-parent = <&gic>;
482 interrupts = <0x0 0x4e 0x4>;
485 serial3: serial@1c023000 {
487 device_type = "serial";
488 compatible = "ns16550a";
489 reg = <0 0x1c023000 0x0 0x1000>;
491 clock-frequency = <10000000>; /* Updated by bootloader */
492 interrupt-parent = <&gic>;
493 interrupts = <0x0 0x4f 0x4>;
497 compatible = "apm,xgene-phy";
498 reg = <0x0 0x1f21a000 0x0 0x100>;
500 clocks = <&sataphy1clk 0>;
502 apm,tx-boost-gain = <30 30 30 30 30 30>;
503 apm,tx-eye-tuning = <2 10 10 2 10 10>;
507 compatible = "apm,xgene-phy";
508 reg = <0x0 0x1f22a000 0x0 0x100>;
510 clocks = <&sataphy2clk 0>;
512 apm,tx-boost-gain = <30 30 30 30 30 30>;
513 apm,tx-eye-tuning = <1 10 10 2 10 10>;
517 compatible = "apm,xgene-phy";
518 reg = <0x0 0x1f23a000 0x0 0x100>;
520 clocks = <&sataphy3clk 0>;
522 apm,tx-boost-gain = <31 31 31 31 31 31>;
523 apm,tx-eye-tuning = <2 10 10 2 10 10>;
526 sata1: sata@1a000000 {
527 compatible = "apm,xgene-ahci";
528 reg = <0x0 0x1a000000 0x0 0x1000>,
529 <0x0 0x1f210000 0x0 0x1000>,
530 <0x0 0x1f21d000 0x0 0x1000>,
531 <0x0 0x1f21e000 0x0 0x1000>,
532 <0x0 0x1f217000 0x0 0x1000>;
533 interrupts = <0x0 0x86 0x4>;
536 clocks = <&sata01clk 0>;
538 phy-names = "sata-phy";
541 sata2: sata@1a400000 {
542 compatible = "apm,xgene-ahci";
543 reg = <0x0 0x1a400000 0x0 0x1000>,
544 <0x0 0x1f220000 0x0 0x1000>,
545 <0x0 0x1f22d000 0x0 0x1000>,
546 <0x0 0x1f22e000 0x0 0x1000>,
547 <0x0 0x1f227000 0x0 0x1000>;
548 interrupts = <0x0 0x87 0x4>;
551 clocks = <&sata23clk 0>;
553 phy-names = "sata-phy";
556 sata3: sata@1a800000 {
557 compatible = "apm,xgene-ahci";
558 reg = <0x0 0x1a800000 0x0 0x1000>,
559 <0x0 0x1f230000 0x0 0x1000>,
560 <0x0 0x1f23d000 0x0 0x1000>,
561 <0x0 0x1f23e000 0x0 0x1000>;
562 interrupts = <0x0 0x88 0x4>;
565 clocks = <&sata45clk 0>;
567 phy-names = "sata-phy";
571 compatible = "apm,xgene-rtc";
572 reg = <0x0 0x10510000 0x0 0x400>;
573 interrupts = <0x0 0x46 0x4>;
575 clocks = <&rtcclk 0>;
578 menet: ethernet@17020000 {
579 compatible = "apm,xgene-enet";
581 reg = <0x0 0x17020000 0x0 0xd100>,
582 <0x0 0X17030000 0x0 0X400>,
583 <0x0 0X10000000 0x0 0X200>;
584 reg-names = "enet_csr", "ring_csr", "ring_cmd";
585 interrupts = <0x0 0x3c 0x4>;
587 clocks = <&menetclk 0>;
588 local-mac-address = [00 01 73 00 00 01];
589 phy-connection-type = "rgmii";
590 phy-handle = <&menetphy>;
592 compatible = "apm,xgene-mdio";
593 #address-cells = <1>;
595 menetphy: menetphy@3 {
596 compatible = "ethernet-phy-id001c.c915";
604 compatible = "apm,xgene-rng";
605 reg = <0x0 0x10520000 0x0 0x100>;
606 interrupts = <0x0 0x41 0x4>;
607 clocks = <&rngpkaclk 0>;