2 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
4 * Copyright (C) 2015, Applied Micro Circuits Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 compatible = "apm,xgene-shadowcat";
14 interrupt-parent = <&gic>;
24 compatible = "apm,strega", "arm,armv8";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
28 next-level-cache = <&xgene_L2_0>;
30 clocks = <&pmd0clk 0>;
34 compatible = "apm,strega", "arm,armv8";
36 enable-method = "spin-table";
37 cpu-release-addr = <0x1 0x0000fff8>;
38 next-level-cache = <&xgene_L2_0>;
40 clocks = <&pmd0clk 0>;
44 compatible = "apm,strega", "arm,armv8";
46 enable-method = "spin-table";
47 cpu-release-addr = <0x1 0x0000fff8>;
48 next-level-cache = <&xgene_L2_1>;
50 clocks = <&pmd1clk 0>;
54 compatible = "apm,strega", "arm,armv8";
56 enable-method = "spin-table";
57 cpu-release-addr = <0x1 0x0000fff8>;
58 next-level-cache = <&xgene_L2_1>;
60 clocks = <&pmd1clk 0>;
64 compatible = "apm,strega", "arm,armv8";
66 enable-method = "spin-table";
67 cpu-release-addr = <0x1 0x0000fff8>;
68 next-level-cache = <&xgene_L2_2>;
70 clocks = <&pmd2clk 0>;
74 compatible = "apm,strega", "arm,armv8";
76 enable-method = "spin-table";
77 cpu-release-addr = <0x1 0x0000fff8>;
78 next-level-cache = <&xgene_L2_2>;
80 clocks = <&pmd2clk 0>;
84 compatible = "apm,strega", "arm,armv8";
86 enable-method = "spin-table";
87 cpu-release-addr = <0x1 0x0000fff8>;
88 next-level-cache = <&xgene_L2_3>;
90 clocks = <&pmd3clk 0>;
94 compatible = "apm,strega", "arm,armv8";
96 enable-method = "spin-table";
97 cpu-release-addr = <0x1 0x0000fff8>;
98 next-level-cache = <&xgene_L2_3>;
100 clocks = <&pmd3clk 0>;
102 xgene_L2_0: l2-cache-0 {
103 compatible = "cache";
105 xgene_L2_1: l2-cache-1 {
106 compatible = "cache";
108 xgene_L2_2: l2-cache-2 {
109 compatible = "cache";
111 xgene_L2_3: l2-cache-3 {
112 compatible = "cache";
116 gic: interrupt-controller@78090000 {
117 compatible = "arm,cortex-a15-gic";
118 #interrupt-cells = <3>;
119 #address-cells = <2>;
121 interrupt-controller;
122 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
123 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
124 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
125 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
126 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
127 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
129 compatible = "arm,gic-v2m-frame";
131 reg = <0x0 0x0 0x0 0x1000>;
134 compatible = "arm,gic-v2m-frame";
136 reg = <0x0 0x10000 0x0 0x1000>;
139 compatible = "arm,gic-v2m-frame";
141 reg = <0x0 0x20000 0x0 0x1000>;
144 compatible = "arm,gic-v2m-frame";
146 reg = <0x0 0x30000 0x0 0x1000>;
149 compatible = "arm,gic-v2m-frame";
151 reg = <0x0 0x40000 0x0 0x1000>;
154 compatible = "arm,gic-v2m-frame";
156 reg = <0x0 0x50000 0x0 0x1000>;
159 compatible = "arm,gic-v2m-frame";
161 reg = <0x0 0x60000 0x0 0x1000>;
164 compatible = "arm,gic-v2m-frame";
166 reg = <0x0 0x70000 0x0 0x1000>;
169 compatible = "arm,gic-v2m-frame";
171 reg = <0x0 0x80000 0x0 0x1000>;
174 compatible = "arm,gic-v2m-frame";
176 reg = <0x0 0x90000 0x0 0x1000>;
179 compatible = "arm,gic-v2m-frame";
181 reg = <0x0 0xa0000 0x0 0x1000>;
184 compatible = "arm,gic-v2m-frame";
186 reg = <0x0 0xb0000 0x0 0x1000>;
189 compatible = "arm,gic-v2m-frame";
191 reg = <0x0 0xc0000 0x0 0x1000>;
194 compatible = "arm,gic-v2m-frame";
196 reg = <0x0 0xd0000 0x0 0x1000>;
199 compatible = "arm,gic-v2m-frame";
201 reg = <0x0 0xe0000 0x0 0x1000>;
204 compatible = "arm,gic-v2m-frame";
206 reg = <0x0 0xf0000 0x0 0x1000>;
211 compatible = "arm,armv8-pmuv3";
212 interrupts = <1 12 0xff04>;
216 compatible = "arm,armv8-timer";
217 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
218 <1 13 0xff08>, /* Non-secure Phys IRQ */
219 <1 14 0xff08>, /* Virt IRQ */
220 <1 15 0xff08>; /* Hyp IRQ */
221 clock-frequency = <50000000>;
225 compatible = "simple-bus";
226 #address-cells = <2>;
231 #address-cells = <2>;
236 compatible = "fixed-clock";
238 clock-frequency = <100000000>;
239 clock-output-names = "refclk";
242 pmdpll: pmdpll@170000f0 {
243 compatible = "apm,xgene-pcppll-v2-clock";
245 clocks = <&refclk 0>;
246 reg = <0x0 0x170000f0 0x0 0x10>;
247 clock-output-names = "pmdpll";
250 pmd0clk: pmd0clk@7e200200 {
251 compatible = "apm,xgene-pmd-clock";
253 clocks = <&pmdpll 0>;
254 reg = <0x0 0x7e200200 0x0 0x10>;
255 clock-output-names = "pmd0clk";
258 pmd1clk: pmd1clk@7e200210 {
259 compatible = "apm,xgene-pmd-clock";
261 clocks = <&pmdpll 0>;
262 reg = <0x0 0x7e200210 0x0 0x10>;
263 clock-output-names = "pmd1clk";
266 pmd2clk: pmd2clk@7e200220 {
267 compatible = "apm,xgene-pmd-clock";
269 clocks = <&pmdpll 0>;
270 reg = <0x0 0x7e200220 0x0 0x10>;
271 clock-output-names = "pmd2clk";
274 pmd3clk: pmd3clk@7e200230 {
275 compatible = "apm,xgene-pmd-clock";
277 clocks = <&pmdpll 0>;
278 reg = <0x0 0x7e200230 0x0 0x10>;
279 clock-output-names = "pmd3clk";
282 socpll: socpll@17000120 {
283 compatible = "apm,xgene-socpll-v2-clock";
285 clocks = <&refclk 0>;
286 reg = <0x0 0x17000120 0x0 0x1000>;
287 clock-output-names = "socpll";
290 socplldiv2: socplldiv2 {
291 compatible = "fixed-factor-clock";
293 clocks = <&socpll 0>;
296 clock-output-names = "socplldiv2";
299 ahbclk: ahbclk@17000000 {
300 compatible = "apm,xgene-device-clock";
302 clocks = <&socplldiv2 0>;
303 reg = <0x0 0x17000000 0x0 0x2000>;
304 reg-names = "div-reg";
305 divider-offset = <0x164>;
306 divider-width = <0x5>;
307 divider-shift = <0x0>;
308 clock-output-names = "ahbclk";
311 sbapbclk: sbapbclk@1704c000 {
312 compatible = "apm,xgene-device-clock";
314 clocks = <&ahbclk 0>;
315 reg = <0x0 0x1704c000 0x0 0x2000>;
316 reg-names = "div-reg";
317 divider-offset = <0x10>;
318 divider-width = <0x2>;
319 divider-shift = <0x0>;
320 clock-output-names = "sbapbclk";
323 sdioclk: sdioclk@1f2ac000 {
324 compatible = "apm,xgene-device-clock";
326 clocks = <&socplldiv2 0>;
327 reg = <0x0 0x1f2ac000 0x0 0x1000
328 0x0 0x17000000 0x0 0x2000>;
329 reg-names = "csr-reg", "div-reg";
332 enable-offset = <0x8>;
334 divider-offset = <0x178>;
335 divider-width = <0x8>;
336 divider-shift = <0x0>;
337 clock-output-names = "sdioclk";
340 pcie0clk: pcie0clk@1f2bc000 {
341 compatible = "apm,xgene-device-clock";
343 clocks = <&socplldiv2 0>;
344 reg = <0x0 0x1f2bc000 0x0 0x1000>;
345 reg-names = "csr-reg";
346 clock-output-names = "pcie0clk";
349 pcie1clk: pcie1clk@1f2cc000 {
350 compatible = "apm,xgene-device-clock";
352 clocks = <&socplldiv2 0>;
353 reg = <0x0 0x1f2cc000 0x0 0x1000>;
354 reg-names = "csr-reg";
355 clock-output-names = "pcie1clk";
358 xge0clk: xge0clk@1f61c000 {
359 compatible = "apm,xgene-device-clock";
361 clocks = <&socplldiv2 0>;
362 reg = <0x0 0x1f61c000 0x0 0x1000>;
363 reg-names = "csr-reg";
366 clock-output-names = "xge0clk";
369 xge1clk: xge1clk@1f62c000 {
370 compatible = "apm,xgene-device-clock";
372 clocks = <&socplldiv2 0>;
373 reg = <0x0 0x1f62c000 0x0 0x1000>;
374 reg-names = "csr-reg";
377 clock-output-names = "xge1clk";
380 rngpkaclk: rngpkaclk@17000000 {
381 compatible = "apm,xgene-device-clock";
383 clocks = <&socplldiv2 0>;
384 reg = <0x0 0x17000000 0x0 0x2000>;
385 reg-names = "csr-reg";
388 enable-offset = <0x10>;
389 enable-mask = <0x10>;
390 clock-output-names = "rngpkaclk";
393 i2c4clk: i2c4clk@1704c000 {
394 compatible = "apm,xgene-device-clock";
396 clocks = <&sbapbclk 0>;
397 reg = <0x0 0x1704c000 0x0 0x1000>;
398 reg-names = "csr-reg";
401 enable-offset = <0x8>;
402 enable-mask = <0x40>;
403 clock-output-names = "i2c4clk";
407 scu: system-clk-controller@17000000 {
408 compatible = "apm,xgene-scu","syscon";
409 reg = <0x0 0x17000000 0x0 0x400>;
412 reboot: reboot@17000014 {
413 compatible = "syscon-reboot";
420 compatible = "apm,xgene-csw", "syscon";
421 reg = <0x0 0x7e200000 0x0 0x1000>;
424 mcba: mcba@7e700000 {
425 compatible = "apm,xgene-mcb", "syscon";
426 reg = <0x0 0x7e700000 0x0 0x1000>;
429 mcbb: mcbb@7e720000 {
430 compatible = "apm,xgene-mcb", "syscon";
431 reg = <0x0 0x7e720000 0x0 0x1000>;
434 efuse: efuse@1054a000 {
435 compatible = "apm,xgene-efuse", "syscon";
436 reg = <0x0 0x1054a000 0x0 0x20>;
440 compatible = "apm,xgene-edac";
441 #address-cells = <2>;
445 regmap-mcba = <&mcba>;
446 regmap-mcbb = <&mcbb>;
447 regmap-efuse = <&efuse>;
448 reg = <0x0 0x78800000 0x0 0x100>;
449 interrupts = <0x0 0x20 0x4>,
454 compatible = "apm,xgene-edac-mc";
455 reg = <0x0 0x7e800000 0x0 0x1000>;
456 memory-controller = <0>;
460 compatible = "apm,xgene-edac-mc";
461 reg = <0x0 0x7e840000 0x0 0x1000>;
462 memory-controller = <1>;
466 compatible = "apm,xgene-edac-mc";
467 reg = <0x0 0x7e880000 0x0 0x1000>;
468 memory-controller = <2>;
472 compatible = "apm,xgene-edac-mc";
473 reg = <0x0 0x7e8c0000 0x0 0x1000>;
474 memory-controller = <3>;
478 compatible = "apm,xgene-edac-pmd";
479 reg = <0x0 0x7c000000 0x0 0x200000>;
480 pmd-controller = <0>;
484 compatible = "apm,xgene-edac-pmd";
485 reg = <0x0 0x7c200000 0x0 0x200000>;
486 pmd-controller = <1>;
490 compatible = "apm,xgene-edac-pmd";
491 reg = <0x0 0x7c400000 0x0 0x200000>;
492 pmd-controller = <2>;
496 compatible = "apm,xgene-edac-pmd";
497 reg = <0x0 0x7c600000 0x0 0x200000>;
498 pmd-controller = <3>;
502 compatible = "apm,xgene-edac-l3-v2";
503 reg = <0x0 0x7e600000 0x0 0x1000>;
507 compatible = "apm,xgene-edac-soc";
508 reg = <0x0 0x7e930000 0x0 0x1000>;
513 compatible = "apm,xgene-pmu-v2";
514 #address-cells = <2>;
518 regmap-mcba = <&mcba>;
519 regmap-mcbb = <&mcbb>;
520 reg = <0x0 0x78810000 0x0 0x1000>;
521 interrupts = <0x0 0x22 0x4>;
524 compatible = "apm,xgene-pmu-l3c";
525 reg = <0x0 0x7e610000 0x0 0x1000>;
529 compatible = "apm,xgene-pmu-iob";
530 reg = <0x0 0x7e940000 0x0 0x1000>;
534 compatible = "apm,xgene-pmu-mcb";
535 reg = <0x0 0x7e710000 0x0 0x1000>;
536 enable-bit-index = <0>;
540 compatible = "apm,xgene-pmu-mcb";
541 reg = <0x0 0x7e730000 0x0 0x1000>;
542 enable-bit-index = <1>;
546 compatible = "apm,xgene-pmu-mc";
547 reg = <0x0 0x7e810000 0x0 0x1000>;
548 enable-bit-index = <0>;
552 compatible = "apm,xgene-pmu-mc";
553 reg = <0x0 0x7e850000 0x0 0x1000>;
554 enable-bit-index = <1>;
558 compatible = "apm,xgene-pmu-mc";
559 reg = <0x0 0x7e890000 0x0 0x1000>;
560 enable-bit-index = <2>;
564 compatible = "apm,xgene-pmu-mc";
565 reg = <0x0 0x7e8d0000 0x0 0x1000>;
566 enable-bit-index = <3>;
570 mailbox: mailbox@10540000 {
571 compatible = "apm,xgene-slimpro-mbox";
572 reg = <0x0 0x10540000 0x0 0x8000>;
574 interrupts = <0x0 0x0 0x4
585 compatible = "apm,xgene-slimpro-i2c";
586 mboxes = <&mailbox 0>;
590 compatible = "apm,xgene-slimpro-hwmon";
591 mboxes = <&mailbox 7>;
594 serial0: serial@10600000 {
595 device_type = "serial";
596 compatible = "ns16550";
597 reg = <0 0x10600000 0x0 0x1000>;
599 clock-frequency = <10000000>;
600 interrupt-parent = <&gic>;
601 interrupts = <0x0 0x4c 0x4>;
604 /* Do not change dwusb name, coded for backward compatibility */
605 usb0: dwusb@19000000 {
607 compatible = "snps,dwc3";
608 reg = <0x0 0x19000000 0x0 0x100000>;
609 interrupts = <0x0 0x5d 0x4>;
614 pcie0: pcie@1f2b0000 {
617 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
618 #interrupt-cells = <1>;
620 #address-cells = <3>;
621 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
622 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
623 reg-names = "csr", "cfg";
624 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
625 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */
626 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
627 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
628 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
629 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
630 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
631 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
632 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4
633 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>;
635 clocks = <&pcie0clk 0>;
636 msi-parent = <&v2m0>;
639 pcie1: pcie@1f2c0000 {
642 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
643 #interrupt-cells = <1>;
645 #address-cells = <3>;
646 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
647 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
648 reg-names = "csr", "cfg";
649 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
650 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */
651 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
652 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
653 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
654 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
655 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
656 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
657 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4
658 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>;
660 clocks = <&pcie1clk 0>;
661 msi-parent = <&v2m0>;
664 sata1: sata@1a000000 {
665 compatible = "apm,xgene-ahci-v2";
666 reg = <0x0 0x1a000000 0x0 0x1000>,
667 <0x0 0x1f200000 0x0 0x1000>,
668 <0x0 0x1f20d000 0x0 0x1000>,
669 <0x0 0x1f20e000 0x0 0x1000>;
670 interrupts = <0x0 0x5a 0x4>;
674 sata2: sata@1a200000 {
675 compatible = "apm,xgene-ahci-v2";
676 reg = <0x0 0x1a200000 0x0 0x1000>,
677 <0x0 0x1f210000 0x0 0x1000>,
678 <0x0 0x1f21d000 0x0 0x1000>,
679 <0x0 0x1f21e000 0x0 0x1000>;
680 interrupts = <0x0 0x5b 0x4>;
684 sata3: sata@1a400000 {
685 compatible = "apm,xgene-ahci-v2";
686 reg = <0x0 0x1a400000 0x0 0x1000>,
687 <0x0 0x1f220000 0x0 0x1000>,
688 <0x0 0x1f22d000 0x0 0x1000>,
689 <0x0 0x1f22e000 0x0 0x1000>;
690 interrupts = <0x0 0x5c 0x4>;
695 compatible = "arasan,sdhci-4.9a";
696 reg = <0x0 0x1c000000 0x0 0x100>;
697 interrupts = <0x0 0x49 0x4>;
700 clock-names = "clk_xin", "clk_ahb";
701 clocks = <&sdioclk 0>, <&ahbclk 0>;
704 gfcgpio: gpio@1f63c000 {
705 compatible = "apm,xgene-gpio";
706 reg = <0x0 0x1f63c000 0x0 0x40>;
711 dwgpio: gpio@1c024000 {
712 compatible = "snps,dw-apb-gpio";
713 reg = <0x0 0x1c024000 0x0 0x1000>;
715 #address-cells = <1>;
718 porta: gpio-controller@0 {
719 compatible = "snps,dw-apb-gpio-port";
721 snps,nr-gpios = <32>;
726 sbgpio: gpio@17001000{
727 compatible = "apm,xgene-gpio-sb";
728 reg = <0x0 0x17001000 0x0 0x400>;
731 interrupts = <0x0 0x28 0x1>,
739 interrupt-parent = <&gic>;
740 #interrupt-cells = <2>;
741 interrupt-controller;
747 mdio: mdio@1f610000 {
748 compatible = "apm,xgene-mdio-xfi";
749 #address-cells = <1>;
751 reg = <0x0 0x1f610000 0x0 0xd100>;
752 clocks = <&xge0clk 0>;
755 sgenet0: ethernet@1f610000 {
756 compatible = "apm,xgene2-sgenet";
758 reg = <0x0 0x1f610000 0x0 0xd100>,
759 <0x0 0x1f600000 0x0 0xd100>,
760 <0x0 0x20000000 0x0 0x20000>;
761 interrupts = <0 96 4>,
764 clocks = <&xge0clk 0>;
765 local-mac-address = [00 01 73 00 00 01];
766 phy-connection-type = "sgmii";
767 phy-handle = <&sgenet0phy>;
770 xgenet1: ethernet@1f620000 {
771 compatible = "apm,xgene2-xgenet";
773 reg = <0x0 0x1f620000 0x0 0x10000>,
774 <0x0 0x1f600000 0x0 0xd100>,
775 <0x0 0x20000000 0x0 0x220000>;
776 interrupts = <0 108 4>,
787 clocks = <&xge1clk 0>;
788 local-mac-address = [00 01 73 00 00 02];
789 phy-connection-type = "xgmii";
793 compatible = "apm,xgene-rng";
794 reg = <0x0 0x10520000 0x0 0x100>;
795 interrupts = <0x0 0x41 0x4>;
796 clocks = <&rngpkaclk 0>;
800 #address-cells = <1>;
802 compatible = "snps,designware-i2c";
803 reg = <0x0 0x10511000 0x0 0x1000>;
804 interrupts = <0 0x45 0x4>;
806 clocks = <&sbapbclk 0>;
811 #address-cells = <1>;
813 compatible = "snps,designware-i2c";
814 reg = <0x0 0x10640000 0x0 0x1000>;
815 interrupts = <0 0x3a 0x4>;
816 clocks = <&i2c4clk 0>;