arch/arm64/boot/dts/hisilicon/hi6220.dtsi

   1 /*
   2  * dts file for Hisilicon Hi6220 SoC
   3  *
   4  * Copyright (C) 2015, Hisilicon Ltd.
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/clock/hi6220-clock.h>
   9 #include <dt-bindings/pinctrl/hisi.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 / {
  13         compatible = "hisilicon,hi6220";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         psci {
  19                 compatible = "arm,psci-0.2";
  20                 method = "smc";
  21         };
  22
  23         cpus {
  24                 #address-cells = <2>;
  25                 #size-cells = <0>;
  26
  27                 cpu-map {
  28                         cluster0 {
  29                                 core0 {
  30                                         cpu = <&cpu0>;
  31                                 };
  32                                 core1 {
  33                                         cpu = <&cpu1>;
  34                                 };
  35                                 core2 {
  36                                         cpu = <&cpu2>;
  37                                 };
  38                                 core3 {
  39                                         cpu = <&cpu3>;
  40                                 };
  41                         };
  42                         cluster1 {
  43                                 core0 {
  44                                         cpu = <&cpu4>;
  45                                 };
  46                                 core1 {
  47                                         cpu = <&cpu5>;
  48                                 };
  49                                 core2 {
  50                                         cpu = <&cpu6>;
  51                                 };
  52                                 core3 {
  53                                         cpu = <&cpu7>;
  54                                 };
  55                         };
  56                 };
  57
  58                 idle-states {
  59                         entry-method = "psci";
  60
  61                         CPU_SLEEP: cpu-sleep {
  62                                 compatible = "arm,idle-state";
  63                                 local-timer-stop;
  64                                 arm,psci-suspend-param = <0x0010000>;
  65                                 entry-latency-us = <700>;
  66                                 exit-latency-us = <250>;
  67                                 min-residency-us = <1000>;
  68                         };
  69
  70                         CLUSTER_SLEEP: cluster-sleep {
  71                                 compatible = "arm,idle-state";
  72                                 local-timer-stop;
  73                                 arm,psci-suspend-param = <0x1010000>;
  74                                 entry-latency-us = <1000>;
  75                                 exit-latency-us = <700>;
  76                                 min-residency-us = <2700>;
  77                                 wakeup-latency-us = <1500>;
  78                         };
  79                 };
  80
  81                 cpu0: cpu@0 {
  82                         compatible = "arm,cortex-a53", "arm,armv8";
  83                         device_type = "cpu";
  84                         reg = <0x0 0x0>;
  85                         enable-method = "psci";
  86                         next-level-cache = <&CLUSTER0_L2>;
  87                         clocks = <&stub_clock 0>;
  88                         operating-points-v2 = <&cpu_opp_table>;
  89                         cooling-min-level = <4>;
  90                         cooling-max-level = <0>;
  91                         #cooling-cells = <2>; /* min followed by max */
  92                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  93                         dynamic-power-coefficient = <311>;
  94                 };
  95
  96                 cpu1: cpu@1 {
  97                         compatible = "arm,cortex-a53", "arm,armv8";
  98                         device_type = "cpu";
  99                         reg = <0x0 0x1>;
 100                         enable-method = "psci";
 101                         next-level-cache = <&CLUSTER0_L2>;
 102                         operating-points-v2 = <&cpu_opp_table>;
 103                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 104                 };
 105
 106                 cpu2: cpu@2 {
 107                         compatible = "arm,cortex-a53", "arm,armv8";
 108                         device_type = "cpu";
 109                         reg = <0x0 0x2>;
 110                         enable-method = "psci";
 111                         next-level-cache = <&CLUSTER0_L2>;
 112                         operating-points-v2 = <&cpu_opp_table>;
 113                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 114                 };
 115
 116                 cpu3: cpu@3 {
 117                         compatible = "arm,cortex-a53", "arm,armv8";
 118                         device_type = "cpu";
 119                         reg = <0x0 0x3>;
 120                         enable-method = "psci";
 121                         next-level-cache = <&CLUSTER0_L2>;
 122                         operating-points-v2 = <&cpu_opp_table>;
 123                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 124                 };
 125
 126                 cpu4: cpu@100 {
 127                         compatible = "arm,cortex-a53", "arm,armv8";
 128                         device_type = "cpu";
 129                         reg = <0x0 0x100>;
 130                         enable-method = "psci";
 131                         next-level-cache = <&CLUSTER1_L2>;
 132                         operating-points-v2 = <&cpu_opp_table>;
 133                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 134                 };
 135
 136                 cpu5: cpu@101 {
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         device_type = "cpu";
 139                         reg = <0x0 0x101>;
 140                         enable-method = "psci";
 141                         next-level-cache = <&CLUSTER1_L2>;
 142                         operating-points-v2 = <&cpu_opp_table>;
 143                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 144                 };
 145
 146                 cpu6: cpu@102 {
 147                         compatible = "arm,cortex-a53", "arm,armv8";
 148                         device_type = "cpu";
 149                         reg = <0x0 0x102>;
 150                         enable-method = "psci";
 151                         next-level-cache = <&CLUSTER1_L2>;
 152                         operating-points-v2 = <&cpu_opp_table>;
 153                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 154                 };
 155
 156                 cpu7: cpu@103 {
 157                         compatible = "arm,cortex-a53", "arm,armv8";
 158                         device_type = "cpu";
 159                         reg = <0x0 0x103>;
 160                         enable-method = "psci";
 161                         next-level-cache = <&CLUSTER1_L2>;
 162                         operating-points-v2 = <&cpu_opp_table>;
 163                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 164                 };
 165
 166                 CLUSTER0_L2: l2-cache0 {
 167                         compatible = "cache";
 168                 };
 169
 170                 CLUSTER1_L2: l2-cache1 {
 171                         compatible = "cache";
 172                 };
 173         };
 174
 175         cpu_opp_table: cpu_opp_table {
 176                 compatible = "operating-points-v2";
 177                 opp-shared;
 178
 179                 opp00 {
 180                         opp-hz = /bits/ 64 <208000000>;
 181                         opp-microvolt = <1040000>;
 182                         clock-latency-ns = <500000>;
 183                 };
 184                 opp01 {
 185                         opp-hz = /bits/ 64 <432000000>;
 186                         opp-microvolt = <1040000>;
 187                         clock-latency-ns = <500000>;
 188                 };
 189                 opp02 {
 190                         opp-hz = /bits/ 64 <729000000>;
 191                         opp-microvolt = <1090000>;
 192                         clock-latency-ns = <500000>;
 193                 };
 194                 opp03 {
 195                         opp-hz = /bits/ 64 <960000000>;
 196                         opp-microvolt = <1180000>;
 197                         clock-latency-ns = <500000>;
 198                 };
 199                 opp04 {
 200                         opp-hz = /bits/ 64 <1200000000>;
 201                         opp-microvolt = <1330000>;
 202                         clock-latency-ns = <500000>;
 203                 };
 204         };
 205
 206         gic: interrupt-controller@f6801000 {
 207                 compatible = "arm,gic-400";
 208                 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
 209                       <0x0 0xf6802000 0 0x2000>, /* GICC */
 210                       <0x0 0xf6804000 0 0x2000>, /* GICH */
 211                       <0x0 0xf6806000 0 0x2000>; /* GICV */
 212                 #address-cells = <0>;
 213                 #interrupt-cells = <3>;
 214                 interrupt-controller;
 215                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 216         };
 217
 218         timer {
 219                 compatible = "arm,armv8-timer";
 220                 interrupt-parent = <&gic>;
 221                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 222                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 223                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 224                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 225         };
 226
 227         soc {
 228                 compatible = "simple-bus";
 229                 #address-cells = <2>;
 230                 #size-cells = <2>;
 231                 ranges;
 232
 233                 sram: sram@fff80000 {
 234                         compatible = "hisilicon,hi6220-sramctrl", "syscon";
 235                         reg = <0x0 0xfff80000 0x0 0x12000>;
 236                 };
 237
 238                 ao_ctrl: ao_ctrl@f7800000 {
 239                         compatible = "hisilicon,hi6220-aoctrl", "syscon";
 240                         reg = <0x0 0xf7800000 0x0 0x2000>;
 241                         #clock-cells = <1>;
 242                 };
 243
 244                 sys_ctrl: sys_ctrl@f7030000 {
 245                         compatible = "hisilicon,hi6220-sysctrl", "syscon";
 246                         reg = <0x0 0xf7030000 0x0 0x2000>;
 247                         #clock-cells = <1>;
 248                         #reset-cells = <1>;
 249                 };
 250
 251                 media_ctrl: media_ctrl@f4410000 {
 252                         compatible = "hisilicon,hi6220-mediactrl", "syscon";
 253                         reg = <0x0 0xf4410000 0x0 0x1000>;
 254                         #clock-cells = <1>;
 255                 };
 256
 257                 pm_ctrl: pm_ctrl@f7032000 {
 258                         compatible = "hisilicon,hi6220-pmctrl", "syscon";
 259                         reg = <0x0 0xf7032000 0x0 0x1000>;
 260                         #clock-cells = <1>;
 261                 };
 262
 263                 stub_clock: stub_clock {
 264                         compatible = "hisilicon,hi6220-stub-clk";
 265                         hisilicon,hi6220-clk-sram = <&sram>;
 266                         #clock-cells = <1>;
 267                         mbox-names = "mbox-tx";
 268                         mboxes = <&mailbox 1 0 11>;
 269                 };
 270
 271                 uart0: uart@f8015000 {  /* console */
 272                         compatible = "arm,pl011", "arm,primecell";
 273                         reg = <0x0 0xf8015000 0x0 0x1000>;
 274                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 275                         clocks = <&ao_ctrl HI6220_UART0_PCLK>,
 276                                  <&ao_ctrl HI6220_UART0_PCLK>;
 277                         clock-names = "uartclk", "apb_pclk";
 278                 };
 279
 280                 uart1: uart@f7111000 {
 281                         compatible = "arm,pl011", "arm,primecell";
 282                         reg = <0x0 0xf7111000 0x0 0x1000>;
 283                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 284                         clocks = <&sys_ctrl HI6220_UART1_PCLK>,
 285                                  <&sys_ctrl HI6220_UART1_PCLK>;
 286                         clock-names = "uartclk", "apb_pclk";
 287                         pinctrl-names = "default";
 288                         pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
 289                         status = "disabled";
 290                 };
 291
 292                 uart2: uart@f7112000 {
 293                         compatible = "arm,pl011", "arm,primecell";
 294                         reg = <0x0 0xf7112000 0x0 0x1000>;
 295                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 296                         clocks = <&sys_ctrl HI6220_UART2_PCLK>,
 297                                  <&sys_ctrl HI6220_UART2_PCLK>;
 298                         clock-names = "uartclk", "apb_pclk";
 299                         pinctrl-names = "default";
 300                         pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
 301                         status = "disabled";
 302                 };
 303
 304                 uart3: uart@f7113000 {
 305                         compatible = "arm,pl011", "arm,primecell";
 306                         reg = <0x0 0xf7113000 0x0 0x1000>;
 307                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 308                         clocks = <&sys_ctrl HI6220_UART3_PCLK>,
 309                                  <&sys_ctrl HI6220_UART3_PCLK>;
 310                         clock-names = "uartclk", "apb_pclk";
 311                         pinctrl-names = "default";
 312                         pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
 313                         status = "disabled";
 314                 };
 315
 316                 uart4: uart@f7114000 {
 317                         compatible = "arm,pl011", "arm,primecell";
 318                         reg = <0x0 0xf7114000 0x0 0x1000>;
 319                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 320                         clocks = <&sys_ctrl HI6220_UART4_PCLK>,
 321                                  <&sys_ctrl HI6220_UART4_PCLK>;
 322                         clock-names = "uartclk", "apb_pclk";
 323                         pinctrl-names = "default";
 324                         pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
 325                         status = "disabled";
 326                 };
 327
 328                 dual_timer0: timer@f8008000 {
 329                         compatible = "arm,sp804", "arm,primecell";
 330                         reg = <0x0 0xf8008000 0x0 0x1000>;
 331                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 332                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 333                         clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
 334                                  <&ao_ctrl HI6220_TIMER0_PCLK>,
 335                                  <&ao_ctrl HI6220_TIMER0_PCLK>;
 336                         clock-names = "timer1", "timer2", "apb_pclk";
 337                 };
 338
 339                 pmx0: pinmux@f7010000 {
 340                         compatible = "pinctrl-single";
 341                         reg = <0x0 0xf7010000  0x0 0x27c>;
 342                         #address-cells = <1>;
 343                         #size-cells = <1>;
 344                         #gpio-range-cells = <3>;
 345                         pinctrl-single,register-width = <32>;
 346                         pinctrl-single,function-mask = <7>;
 347                         pinctrl-single,gpio-range = <
 348                                 &range  80  8 MUX_M0 /* gpio  3: [0..7] */
 349                                 &range  88  8 MUX_M0 /* gpio  4: [0..7] */
 350                                 &range  96  8 MUX_M0 /* gpio  5: [0..7] */
 351                                 &range 104  8 MUX_M0 /* gpio  6: [0..7] */
 352                                 &range 112  8 MUX_M0 /* gpio  7: [0..7] */
 353                                 &range 120  2 MUX_M0 /* gpio  8: [0..1] */
 354                                 &range   2  6 MUX_M1 /* gpio  8: [2..7] */
 355                                 &range   8  8 MUX_M1 /* gpio  9: [0..7] */
 356                                 &range   0  1 MUX_M1 /* gpio 10: [0]    */
 357                                 &range  16  7 MUX_M1 /* gpio 10: [1..7] */
 358                                 &range  23  3 MUX_M1 /* gpio 11: [0..2] */
 359                                 &range  28  5 MUX_M1 /* gpio 11: [3..7] */
 360                                 &range  33  3 MUX_M1 /* gpio 12: [0..2] */
 361                                 &range  43  5 MUX_M1 /* gpio 12: [3..7] */
 362                                 &range  48  8 MUX_M1 /* gpio 13: [0..7] */
 363                                 &range  56  8 MUX_M1 /* gpio 14: [0..7] */
 364                                 &range  74  6 MUX_M1 /* gpio 15: [0..5] */
 365                                 &range 122  1 MUX_M1 /* gpio 15: [6]    */
 366                                 &range 126  1 MUX_M1 /* gpio 15: [7]    */
 367                                 &range 127  8 MUX_M1 /* gpio 16: [0..7] */
 368                                 &range 135  8 MUX_M1 /* gpio 17: [0..7] */
 369                                 &range 143  8 MUX_M1 /* gpio 18: [0..7] */
 370                                 &range 151  8 MUX_M1 /* gpio 19: [0..7] */
 371                         >;
 372                         range: gpio-range {
 373                                 #pinctrl-single,gpio-range-cells = <3>;
 374                         };
 375                 };
 376
 377                 pmx1: pinmux@f7010800 {
 378                         compatible = "pinconf-single";
 379                         reg = <0x0 0xf7010800 0x0 0x28c>;
 380                         #address-cells = <1>;
 381                         #size-cells = <1>;
 382                         pinctrl-single,register-width = <32>;
 383                 };
 384
 385                 pmx2: pinmux@f8001800 {
 386                         compatible = "pinconf-single";
 387                         reg = <0x0 0xf8001800 0x0 0x78>;
 388                         #address-cells = <1>;
 389                         #size-cells = <1>;
 390                         pinctrl-single,register-width = <32>;
 391                 };
 392
 393                 gpio0: gpio@f8011000 {
 394                         compatible = "arm,pl061", "arm,primecell";
 395                         reg = <0x0 0xf8011000 0x0 0x1000>;
 396                         interrupts = <0 52 0x4>;
 397                         gpio-controller;
 398                         #gpio-cells = <2>;
 399                         interrupt-controller;
 400                         #interrupt-cells = <2>;
 401                         clocks = <&ao_ctrl 2>;
 402                         clock-names = "apb_pclk";
 403                 };
 404
 405                 gpio1: gpio@f8012000 {
 406                         compatible = "arm,pl061", "arm,primecell";
 407                         reg = <0x0 0xf8012000 0x0 0x1000>;
 408                         interrupts = <0 53 0x4>;
 409                         gpio-controller;
 410                         #gpio-cells = <2>;
 411                         interrupt-controller;
 412                         #interrupt-cells = <2>;
 413                         clocks = <&ao_ctrl 2>;
 414                         clock-names = "apb_pclk";
 415                 };
 416
 417                 gpio2: gpio@f8013000 {
 418                         compatible = "arm,pl061", "arm,primecell";
 419                         reg = <0x0 0xf8013000 0x0 0x1000>;
 420                         interrupts = <0 54 0x4>;
 421                         gpio-controller;
 422                         #gpio-cells = <2>;
 423                         interrupt-controller;
 424                         #interrupt-cells = <2>;
 425                         clocks = <&ao_ctrl 2>;
 426                         clock-names = "apb_pclk";
 427                 };
 428
 429                 gpio3: gpio@f8014000 {
 430                         compatible = "arm,pl061", "arm,primecell";
 431                         reg = <0x0 0xf8014000 0x0 0x1000>;
 432                         interrupts = <0 55 0x4>;
 433                         gpio-controller;
 434                         #gpio-cells = <2>;
 435                         gpio-ranges = <&pmx0 0 80 8>;
 436                         interrupt-controller;
 437                         #interrupt-cells = <2>;
 438                         clocks = <&ao_ctrl 2>;
 439                         clock-names = "apb_pclk";
 440                 };
 441
 442                 gpio4: gpio@f7020000 {
 443                         compatible = "arm,pl061", "arm,primecell";
 444                         reg = <0x0 0xf7020000 0x0 0x1000>;
 445                         interrupts = <0 56 0x4>;
 446                         gpio-controller;
 447                         #gpio-cells = <2>;
 448                         gpio-ranges = <&pmx0 0 88 8>;
 449                         interrupt-controller;
 450                         #interrupt-cells = <2>;
 451                         clocks = <&ao_ctrl 2>;
 452                         clock-names = "apb_pclk";
 453                 };
 454
 455                 gpio5: gpio@f7021000 {
 456                         compatible = "arm,pl061", "arm,primecell";
 457                         reg = <0x0 0xf7021000 0x0 0x1000>;
 458                         interrupts = <0 57 0x4>;
 459                         gpio-controller;
 460                         #gpio-cells = <2>;
 461                         gpio-ranges = <&pmx0 0 96 8>;
 462                         interrupt-controller;
 463                         #interrupt-cells = <2>;
 464                         clocks = <&ao_ctrl 2>;
 465                         clock-names = "apb_pclk";
 466                 };
 467
 468                 gpio6: gpio@f7022000 {
 469                         compatible = "arm,pl061", "arm,primecell";
 470                         reg = <0x0 0xf7022000 0x0 0x1000>;
 471                         interrupts = <0 58 0x4>;
 472                         gpio-controller;
 473                         #gpio-cells = <2>;
 474                         gpio-ranges = <&pmx0 0 104 8>;
 475                         interrupt-controller;
 476                         #interrupt-cells = <2>;
 477                         clocks = <&ao_ctrl 2>;
 478                         clock-names = "apb_pclk";
 479                 };
 480
 481                 gpio7: gpio@f7023000 {
 482                         compatible = "arm,pl061", "arm,primecell";
 483                         reg = <0x0 0xf7023000 0x0 0x1000>;
 484                         interrupts = <0 59 0x4>;
 485                         gpio-controller;
 486                         #gpio-cells = <2>;
 487                         gpio-ranges = <&pmx0 0 112 8>;
 488                         interrupt-controller;
 489                         #interrupt-cells = <2>;
 490                         clocks = <&ao_ctrl 2>;
 491                         clock-names = "apb_pclk";
 492                 };
 493
 494                 gpio8: gpio@f7024000 {
 495                         compatible = "arm,pl061", "arm,primecell";
 496                         reg = <0x0 0xf7024000 0x0 0x1000>;
 497                         interrupts = <0 60 0x4>;
 498                         gpio-controller;
 499                         #gpio-cells = <2>;
 500                         gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
 501                         interrupt-controller;
 502                         #interrupt-cells = <2>;
 503                         clocks = <&ao_ctrl 2>;
 504                         clock-names = "apb_pclk";
 505                 };
 506
 507                 gpio9: gpio@f7025000 {
 508                         compatible = "arm,pl061", "arm,primecell";
 509                         reg = <0x0 0xf7025000 0x0 0x1000>;
 510                         interrupts = <0 61 0x4>;
 511                         gpio-controller;
 512                         #gpio-cells = <2>;
 513                         gpio-ranges = <&pmx0 0 8 8>;
 514                         interrupt-controller;
 515                         #interrupt-cells = <2>;
 516                         clocks = <&ao_ctrl 2>;
 517                         clock-names = "apb_pclk";
 518                 };
 519
 520                 gpio10: gpio@f7026000 {
 521                         compatible = "arm,pl061", "arm,primecell";
 522                         reg = <0x0 0xf7026000 0x0 0x1000>;
 523                         interrupts = <0 62 0x4>;
 524                         gpio-controller;
 525                         #gpio-cells = <2>;
 526                         gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
 527                         interrupt-controller;
 528                         #interrupt-cells = <2>;
 529                         clocks = <&ao_ctrl 2>;
 530                         clock-names = "apb_pclk";
 531                 };
 532
 533                 gpio11: gpio@f7027000 {
 534                         compatible = "arm,pl061", "arm,primecell";
 535                         reg = <0x0 0xf7027000 0x0 0x1000>;
 536                         interrupts = <0 63 0x4>;
 537                         gpio-controller;
 538                         #gpio-cells = <2>;
 539                         gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
 540                         interrupt-controller;
 541                         #interrupt-cells = <2>;
 542                         clocks = <&ao_ctrl 2>;
 543                         clock-names = "apb_pclk";
 544                 };
 545
 546                 gpio12: gpio@f7028000 {
 547                         compatible = "arm,pl061", "arm,primecell";
 548                         reg = <0x0 0xf7028000 0x0 0x1000>;
 549                         interrupts = <0 64 0x4>;
 550                         gpio-controller;
 551                         #gpio-cells = <2>;
 552                         gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
 553                         interrupt-controller;
 554                         #interrupt-cells = <2>;
 555                         clocks = <&ao_ctrl 2>;
 556                         clock-names = "apb_pclk";
 557                 };
 558
 559                 gpio13: gpio@f7029000 {
 560                         compatible = "arm,pl061", "arm,primecell";
 561                         reg = <0x0 0xf7029000 0x0 0x1000>;
 562                         interrupts = <0 65 0x4>;
 563                         gpio-controller;
 564                         #gpio-cells = <2>;
 565                         gpio-ranges = <&pmx0 0 48 8>;
 566                         interrupt-controller;
 567                         #interrupt-cells = <2>;
 568                         clocks = <&ao_ctrl 2>;
 569                         clock-names = "apb_pclk";
 570                 };
 571
 572                 gpio14: gpio@f702a000 {
 573                         compatible = "arm,pl061", "arm,primecell";
 574                         reg = <0x0 0xf702a000 0x0 0x1000>;
 575                         interrupts = <0 66 0x4>;
 576                         gpio-controller;
 577                         #gpio-cells = <2>;
 578                         gpio-ranges = <&pmx0 0 56 8>;
 579                         interrupt-controller;
 580                         #interrupt-cells = <2>;
 581                         clocks = <&ao_ctrl 2>;
 582                         clock-names = "apb_pclk";
 583                 };
 584
 585                 gpio15: gpio@f702b000 {
 586                         compatible = "arm,pl061", "arm,primecell";
 587                         reg = <0x0 0xf702b000 0x0 0x1000>;
 588                         interrupts = <0 67 0x4>;
 589                         gpio-controller;
 590                         #gpio-cells = <2>;
 591                         gpio-ranges = <
 592                                 &pmx0 0 74 6
 593                                 &pmx0 6 122 1
 594                                 &pmx0 7 126 1
 595                         >;
 596                         interrupt-controller;
 597                         #interrupt-cells = <2>;
 598                         clocks = <&ao_ctrl 2>;
 599                         clock-names = "apb_pclk";
 600                 };
 601
 602                 gpio16: gpio@f702c000 {
 603                         compatible = "arm,pl061", "arm,primecell";
 604                         reg = <0x0 0xf702c000 0x0 0x1000>;
 605                         interrupts = <0 68 0x4>;
 606                         gpio-controller;
 607                         #gpio-cells = <2>;
 608                         gpio-ranges = <&pmx0 0 127 8>;
 609                         interrupt-controller;
 610                         #interrupt-cells = <2>;
 611                         clocks = <&ao_ctrl 2>;
 612                         clock-names = "apb_pclk";
 613                 };
 614
 615                 gpio17: gpio@f702d000 {
 616                         compatible = "arm,pl061", "arm,primecell";
 617                         reg = <0x0 0xf702d000 0x0 0x1000>;
 618                         interrupts = <0 69 0x4>;
 619                         gpio-controller;
 620                         #gpio-cells = <2>;
 621                         gpio-ranges = <&pmx0 0 135 8>;
 622                         interrupt-controller;
 623                         #interrupt-cells = <2>;
 624                         clocks = <&ao_ctrl 2>;
 625                         clock-names = "apb_pclk";
 626                 };
 627
 628                 gpio18: gpio@f702e000 {
 629                         compatible = "arm,pl061", "arm,primecell";
 630                         reg = <0x0 0xf702e000 0x0 0x1000>;
 631                         interrupts = <0 70 0x4>;
 632                         gpio-controller;
 633                         #gpio-cells = <2>;
 634                         gpio-ranges = <&pmx0 0 143 8>;
 635                         interrupt-controller;
 636                         #interrupt-cells = <2>;
 637                         clocks = <&ao_ctrl 2>;
 638                         clock-names = "apb_pclk";
 639                 };
 640
 641                 gpio19: gpio@f702f000 {
 642                         compatible = "arm,pl061", "arm,primecell";
 643                         reg = <0x0 0xf702f000 0x0 0x1000>;
 644                         interrupts = <0 71 0x4>;
 645                         gpio-controller;
 646                         #gpio-cells = <2>;
 647                         gpio-ranges = <&pmx0 0 151 8>;
 648                         interrupt-controller;
 649                         #interrupt-cells = <2>;
 650                         clocks = <&ao_ctrl 2>;
 651                         clock-names = "apb_pclk";
 652                 };
 653
 654                 spi0: spi@f7106000 {
 655                         compatible = "arm,pl022", "arm,primecell";
 656                         reg = <0x0 0xf7106000 0x0 0x1000>;
 657                         interrupts = <0 50 4>;
 658                         bus-id = <0>;
 659                         enable-dma = <0>;
 660                         clocks = <&sys_ctrl HI6220_SPI_CLK>;
 661                         clock-names = "apb_pclk";
 662                         pinctrl-names = "default";
 663                         pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
 664                         num-cs = <1>;
 665                         cs-gpios = <&gpio6 2 0>;
 666                         status = "disabled";
 667                 };
 668
 669                 i2c0: i2c@f7100000 {
 670                         compatible = "snps,designware-i2c";
 671                         reg = <0x0 0xf7100000 0x0 0x1000>;
 672                         interrupts = <0 44 4>;
 673                         clocks = <&sys_ctrl HI6220_I2C0_CLK>;
 674                         i2c-sda-hold-time-ns = <300>;
 675                         pinctrl-names = "default";
 676                         pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
 677                         status = "disabled";
 678                 };
 679
 680                 i2c1: i2c@f7101000 {
 681                         compatible = "snps,designware-i2c";
 682                         reg = <0x0 0xf7101000 0x0 0x1000>;
 683                         clocks = <&sys_ctrl HI6220_I2C1_CLK>;
 684                         interrupts = <0 45 4>;
 685                         i2c-sda-hold-time-ns = <300>;
 686                         pinctrl-names = "default";
 687                         pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
 688                         status = "disabled";
 689                 };
 690
 691                 i2c2: i2c@f7102000 {
 692                         compatible = "snps,designware-i2c";
 693                         reg = <0x0 0xf7102000 0x0 0x1000>;
 694                         clocks = <&sys_ctrl HI6220_I2C2_CLK>;
 695                         interrupts = <0 46 4>;
 696                         i2c-sda-hold-time-ns = <300>;
 697                         pinctrl-names = "default";
 698                         pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
 699                         status = "disabled";
 700                 };
 701
 702                 fixed_5v_hub: regulator@0 {
 703                         compatible = "regulator-fixed";
 704                         regulator-name = "fixed_5v_hub";
 705                         regulator-min-microvolt = <5000000>;
 706                         regulator-max-microvolt = <5000000>;
 707                         regulator-boot-on;
 708                         gpio = <&gpio0 7 0>;
 709                         regulator-always-on;
 710                 };
 711
 712                 usb_phy: usbphy {
 713                         compatible = "hisilicon,hi6220-usb-phy";
 714                         #phy-cells = <0>;
 715                         phy-supply = <&fixed_5v_hub>;
 716                         hisilicon,peripheral-syscon = <&sys_ctrl>;
 717                 };
 718
 719                 usb: usb@f72c0000 {
 720                         compatible = "hisilicon,hi6220-usb";
 721                         reg = <0x0 0xf72c0000 0x0 0x40000>;
 722                         phys = <&usb_phy>;
 723                         phy-names = "usb2-phy";
 724                         clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
 725                         clock-names = "otg";
 726                         dr_mode = "otg";
 727                         g-use-dma;
 728                         g-rx-fifo-size = <512>;
 729                         g-np-tx-fifo-size = <128>;
 730                         g-tx-fifo-size = <128 128 128 128 128 128>;
 731                         interrupts = <0 77 0x4>;
 732                 };
 733
 734                 mailbox: mailbox@f7510000 {
 735                         compatible = "hisilicon,hi6220-mbox";
 736                         reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
 737                               <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
 738                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 739                         #mbox-cells = <3>;
 740                 };
 741
 742                 dwmmc_0: dwmmc0@f723d000 {
 743                         compatible = "hisilicon,hi6220-dw-mshc";
 744                         num-slots = <0x1>;
 745                         cap-mmc-highspeed;
 746                         non-removable;
 747                         reg = <0x0 0xf723d000 0x0 0x1000>;
 748                         interrupts = <0x0 0x48 0x4>;
 749                         clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
 750                         clock-names = "ciu", "biu";
 751                         bus-width = <0x8>;
 752                         vmmc-supply = <&ldo19>;
 753                         pinctrl-names = "default";
 754                         pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
 755                                      &emmc_cfg_func &emmc_rst_cfg_func>;
 756                 };
 757
 758                 dwmmc_1: dwmmc1@f723e000 {
 759                         compatible = "hisilicon,hi6220-dw-mshc";
 760                         num-slots = <0x1>;
 761                         card-detect-delay = <200>;
 762                         hisilicon,peripheral-syscon = <&ao_ctrl>;
 763                         cap-sd-highspeed;
 764                         reg = <0x0 0xf723e000 0x0 0x1000>;
 765                         interrupts = <0x0 0x49 0x4>;
 766                         #address-cells = <0x1>;
 767                         #size-cells = <0x0>;
 768                         clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
 769                         clock-names = "ciu", "biu";
 770                         vqmmc-supply = <&ldo7>;
 771                         vmmc-supply = <&ldo10>;
 772                         bus-width = <0x4>;
 773                         disable-wp;
 774                         cd-gpios = <&gpio1 0 1>;
 775                         pinctrl-names = "default", "idle";
 776                         pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
 777                         pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
 778                 };
 779
 780                 dwmmc_2: dwmmc2@f723f000 {
 781                         compatible = "hisilicon,hi6220-dw-mshc";
 782                         num-slots = <0x1>;
 783                         reg = <0x0 0xf723f000 0x0 0x1000>;
 784                         interrupts = <0x0 0x4a 0x4>;
 785                         clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
 786                         clock-names = "ciu", "biu";
 787                         bus-width = <0x4>;
 788                         broken-cd;
 789                         pinctrl-names = "default", "idle";
 790                         pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
 791                         pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
 792                 };
 793
 794                 tsensor: tsensor@0,f7030700 {
 795                         compatible = "hisilicon,tsensor";
 796                         reg = <0x0 0xf7030700 0x0 0x1000>;
 797                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 798                         clocks = <&sys_ctrl 22>;
 799                         clock-names = "thermal_clk";
 800                         #thermal-sensor-cells = <1>;
 801                 };
 802
 803                 thermal-zones {
 804
 805                         cls0: cls0 {
 806                                 polling-delay = <1000>;
 807                                 polling-delay-passive = <100>;
 808                                 sustainable-power = <3326>;
 809
 810                                 /* sensor ID */
 811                                 thermal-sensors = <&tsensor 2>;
 812
 813                                 trips {
 814                                         threshold: trip-point@0 {
 815                                                 temperature = <65000>;
 816                                                 hysteresis = <0>;
 817                                                 type = "passive";
 818                                         };
 819
 820                                         target: trip-point@1 {
 821                                                 temperature = <75000>;
 822                                                 hysteresis = <0>;
 823                                                 type = "passive";
 824                                         };
 825                                 };
 826
 827                                 cooling-maps {
 828                                         map0 {
 829                                                 trip = <&target>;
 830                                                 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 831                                         };
 832                                 };
 833                         };
 834                 };
 835         };
 836 };