2 * dts file for Hisilicon Hi6220 SoC
4 * Copyright (C) 2015, Hisilicon Ltd.
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/reset/hisi,hi6220-resets.h>
9 #include <dt-bindings/clock/hi6220-clock.h>
10 #include <dt-bindings/pinctrl/hisi.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "hisilicon,hi6220";
15 interrupt-parent = <&gic>;
20 compatible = "arm,psci-0.2";
60 entry-method = "psci";
62 CPU_SLEEP: cpu-sleep {
63 compatible = "arm,idle-state";
65 arm,psci-suspend-param = <0x0010000>;
66 entry-latency-us = <700>;
67 exit-latency-us = <250>;
68 min-residency-us = <1000>;
71 CLUSTER_SLEEP: cluster-sleep {
72 compatible = "arm,idle-state";
74 arm,psci-suspend-param = <0x1010000>;
75 entry-latency-us = <1000>;
76 exit-latency-us = <700>;
77 min-residency-us = <2700>;
78 wakeup-latency-us = <1500>;
83 compatible = "arm,cortex-a53", "arm,armv8";
86 enable-method = "psci";
87 next-level-cache = <&CLUSTER0_L2>;
88 clocks = <&stub_clock 0>;
89 operating-points-v2 = <&cpu_opp_table>;
90 cooling-min-level = <4>;
91 cooling-max-level = <0>;
92 #cooling-cells = <2>; /* min followed by max */
93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
94 dynamic-power-coefficient = <311>;
98 compatible = "arm,cortex-a53", "arm,armv8";
101 enable-method = "psci";
102 next-level-cache = <&CLUSTER0_L2>;
103 operating-points-v2 = <&cpu_opp_table>;
104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
108 compatible = "arm,cortex-a53", "arm,armv8";
111 enable-method = "psci";
112 next-level-cache = <&CLUSTER0_L2>;
113 operating-points-v2 = <&cpu_opp_table>;
114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
118 compatible = "arm,cortex-a53", "arm,armv8";
121 enable-method = "psci";
122 next-level-cache = <&CLUSTER0_L2>;
123 operating-points-v2 = <&cpu_opp_table>;
124 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
128 compatible = "arm,cortex-a53", "arm,armv8";
131 enable-method = "psci";
132 next-level-cache = <&CLUSTER1_L2>;
133 operating-points-v2 = <&cpu_opp_table>;
134 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
138 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 next-level-cache = <&CLUSTER1_L2>;
143 operating-points-v2 = <&cpu_opp_table>;
144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
148 compatible = "arm,cortex-a53", "arm,armv8";
151 enable-method = "psci";
152 next-level-cache = <&CLUSTER1_L2>;
153 operating-points-v2 = <&cpu_opp_table>;
154 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
158 compatible = "arm,cortex-a53", "arm,armv8";
161 enable-method = "psci";
162 next-level-cache = <&CLUSTER1_L2>;
163 operating-points-v2 = <&cpu_opp_table>;
164 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
167 CLUSTER0_L2: l2-cache0 {
168 compatible = "cache";
171 CLUSTER1_L2: l2-cache1 {
172 compatible = "cache";
176 cpu_opp_table: cpu_opp_table {
177 compatible = "operating-points-v2";
181 opp-hz = /bits/ 64 <208000000>;
182 opp-microvolt = <1040000>;
183 clock-latency-ns = <500000>;
186 opp-hz = /bits/ 64 <432000000>;
187 opp-microvolt = <1040000>;
188 clock-latency-ns = <500000>;
191 opp-hz = /bits/ 64 <729000000>;
192 opp-microvolt = <1090000>;
193 clock-latency-ns = <500000>;
196 opp-hz = /bits/ 64 <960000000>;
197 opp-microvolt = <1180000>;
198 clock-latency-ns = <500000>;
201 opp-hz = /bits/ 64 <1200000000>;
202 opp-microvolt = <1330000>;
203 clock-latency-ns = <500000>;
207 gic: interrupt-controller@f6801000 {
208 compatible = "arm,gic-400";
209 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
210 <0x0 0xf6802000 0 0x2000>, /* GICC */
211 <0x0 0xf6804000 0 0x2000>, /* GICH */
212 <0x0 0xf6806000 0 0x2000>; /* GICV */
213 #address-cells = <0>;
214 #interrupt-cells = <3>;
215 interrupt-controller;
216 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
220 compatible = "arm,armv8-timer";
221 interrupt-parent = <&gic>;
222 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
223 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
224 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
225 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
229 compatible = "simple-bus";
230 #address-cells = <2>;
234 sram: sram@fff80000 {
235 compatible = "hisilicon,hi6220-sramctrl", "syscon";
236 reg = <0x0 0xfff80000 0x0 0x12000>;
239 ao_ctrl: ao_ctrl@f7800000 {
240 compatible = "hisilicon,hi6220-aoctrl", "syscon";
241 reg = <0x0 0xf7800000 0x0 0x2000>;
245 sys_ctrl: sys_ctrl@f7030000 {
246 compatible = "hisilicon,hi6220-sysctrl", "syscon";
247 reg = <0x0 0xf7030000 0x0 0x2000>;
252 media_ctrl: media_ctrl@f4410000 {
253 compatible = "hisilicon,hi6220-mediactrl", "syscon";
254 reg = <0x0 0xf4410000 0x0 0x1000>;
259 pm_ctrl: pm_ctrl@f7032000 {
260 compatible = "hisilicon,hi6220-pmctrl", "syscon";
261 reg = <0x0 0xf7032000 0x0 0x1000>;
265 stub_clock: stub_clock {
266 compatible = "hisilicon,hi6220-stub-clk";
267 hisilicon,hi6220-clk-sram = <&sram>;
269 mbox-names = "mbox-tx";
270 mboxes = <&mailbox 1 0 11>;
273 uart0: uart@f8015000 { /* console */
274 compatible = "arm,pl011", "arm,primecell";
275 reg = <0x0 0xf8015000 0x0 0x1000>;
276 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&ao_ctrl HI6220_UART0_PCLK>,
278 <&ao_ctrl HI6220_UART0_PCLK>;
279 clock-names = "uartclk", "apb_pclk";
282 uart1: uart@f7111000 {
283 compatible = "arm,pl011", "arm,primecell";
284 reg = <0x0 0xf7111000 0x0 0x1000>;
285 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
287 <&sys_ctrl HI6220_UART1_PCLK>;
288 clock-names = "uartclk", "apb_pclk";
289 pinctrl-names = "default";
290 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
294 uart2: uart@f7112000 {
295 compatible = "arm,pl011", "arm,primecell";
296 reg = <0x0 0xf7112000 0x0 0x1000>;
297 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
299 <&sys_ctrl HI6220_UART2_PCLK>;
300 clock-names = "uartclk", "apb_pclk";
301 pinctrl-names = "default";
302 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
306 uart3: uart@f7113000 {
307 compatible = "arm,pl011", "arm,primecell";
308 reg = <0x0 0xf7113000 0x0 0x1000>;
309 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
311 <&sys_ctrl HI6220_UART3_PCLK>;
312 clock-names = "uartclk", "apb_pclk";
313 pinctrl-names = "default";
314 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
318 uart4: uart@f7114000 {
319 compatible = "arm,pl011", "arm,primecell";
320 reg = <0x0 0xf7114000 0x0 0x1000>;
321 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
323 <&sys_ctrl HI6220_UART4_PCLK>;
324 clock-names = "uartclk", "apb_pclk";
325 pinctrl-names = "default";
326 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
330 dual_timer0: timer@f8008000 {
331 compatible = "arm,sp804", "arm,primecell";
332 reg = <0x0 0xf8008000 0x0 0x1000>;
333 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
336 <&ao_ctrl HI6220_TIMER0_PCLK>,
337 <&ao_ctrl HI6220_TIMER0_PCLK>;
338 clock-names = "timer1", "timer2", "apb_pclk";
342 compatible = "arm,pl031", "arm,primecell";
343 reg = <0x0 0xf8003000 0x0 0x1000>;
344 interrupts = <0 12 4>;
345 clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
346 clock-names = "apb_pclk";
350 compatible = "arm,pl031", "arm,primecell";
351 reg = <0x0 0xf8004000 0x0 0x1000>;
352 interrupts = <0 8 4>;
353 clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
354 clock-names = "apb_pclk";
357 pmx0: pinmux@f7010000 {
358 compatible = "pinctrl-single";
359 reg = <0x0 0xf7010000 0x0 0x27c>;
360 #address-cells = <1>;
362 #gpio-range-cells = <3>;
363 pinctrl-single,register-width = <32>;
364 pinctrl-single,function-mask = <7>;
365 pinctrl-single,gpio-range = <
366 &range 80 8 MUX_M0 /* gpio 3: [0..7] */
367 &range 88 8 MUX_M0 /* gpio 4: [0..7] */
368 &range 96 8 MUX_M0 /* gpio 5: [0..7] */
369 &range 104 8 MUX_M0 /* gpio 6: [0..7] */
370 &range 112 8 MUX_M0 /* gpio 7: [0..7] */
371 &range 120 2 MUX_M0 /* gpio 8: [0..1] */
372 &range 2 6 MUX_M1 /* gpio 8: [2..7] */
373 &range 8 8 MUX_M1 /* gpio 9: [0..7] */
374 &range 0 1 MUX_M1 /* gpio 10: [0] */
375 &range 16 7 MUX_M1 /* gpio 10: [1..7] */
376 &range 23 3 MUX_M1 /* gpio 11: [0..2] */
377 &range 28 5 MUX_M1 /* gpio 11: [3..7] */
378 &range 33 3 MUX_M1 /* gpio 12: [0..2] */
379 &range 43 5 MUX_M1 /* gpio 12: [3..7] */
380 &range 48 8 MUX_M1 /* gpio 13: [0..7] */
381 &range 56 8 MUX_M1 /* gpio 14: [0..7] */
382 &range 74 6 MUX_M1 /* gpio 15: [0..5] */
383 &range 122 1 MUX_M1 /* gpio 15: [6] */
384 &range 126 1 MUX_M1 /* gpio 15: [7] */
385 &range 127 8 MUX_M1 /* gpio 16: [0..7] */
386 &range 135 8 MUX_M1 /* gpio 17: [0..7] */
387 &range 143 8 MUX_M1 /* gpio 18: [0..7] */
388 &range 151 8 MUX_M1 /* gpio 19: [0..7] */
391 #pinctrl-single,gpio-range-cells = <3>;
395 pmx1: pinmux@f7010800 {
396 compatible = "pinconf-single";
397 reg = <0x0 0xf7010800 0x0 0x28c>;
398 #address-cells = <1>;
400 pinctrl-single,register-width = <32>;
403 pmx2: pinmux@f8001800 {
404 compatible = "pinconf-single";
405 reg = <0x0 0xf8001800 0x0 0x78>;
406 #address-cells = <1>;
408 pinctrl-single,register-width = <32>;
411 gpio0: gpio@f8011000 {
412 compatible = "arm,pl061", "arm,primecell";
413 reg = <0x0 0xf8011000 0x0 0x1000>;
414 interrupts = <0 52 0x4>;
417 interrupt-controller;
418 #interrupt-cells = <2>;
419 clocks = <&ao_ctrl 2>;
420 clock-names = "apb_pclk";
423 gpio1: gpio@f8012000 {
424 compatible = "arm,pl061", "arm,primecell";
425 reg = <0x0 0xf8012000 0x0 0x1000>;
426 interrupts = <0 53 0x4>;
429 interrupt-controller;
430 #interrupt-cells = <2>;
431 clocks = <&ao_ctrl 2>;
432 clock-names = "apb_pclk";
435 gpio2: gpio@f8013000 {
436 compatible = "arm,pl061", "arm,primecell";
437 reg = <0x0 0xf8013000 0x0 0x1000>;
438 interrupts = <0 54 0x4>;
441 interrupt-controller;
442 #interrupt-cells = <2>;
443 clocks = <&ao_ctrl 2>;
444 clock-names = "apb_pclk";
447 gpio3: gpio@f8014000 {
448 compatible = "arm,pl061", "arm,primecell";
449 reg = <0x0 0xf8014000 0x0 0x1000>;
450 interrupts = <0 55 0x4>;
453 gpio-ranges = <&pmx0 0 80 8>;
454 interrupt-controller;
455 #interrupt-cells = <2>;
456 clocks = <&ao_ctrl 2>;
457 clock-names = "apb_pclk";
460 gpio4: gpio@f7020000 {
461 compatible = "arm,pl061", "arm,primecell";
462 reg = <0x0 0xf7020000 0x0 0x1000>;
463 interrupts = <0 56 0x4>;
466 gpio-ranges = <&pmx0 0 88 8>;
467 interrupt-controller;
468 #interrupt-cells = <2>;
469 clocks = <&ao_ctrl 2>;
470 clock-names = "apb_pclk";
473 gpio5: gpio@f7021000 {
474 compatible = "arm,pl061", "arm,primecell";
475 reg = <0x0 0xf7021000 0x0 0x1000>;
476 interrupts = <0 57 0x4>;
479 gpio-ranges = <&pmx0 0 96 8>;
480 interrupt-controller;
481 #interrupt-cells = <2>;
482 clocks = <&ao_ctrl 2>;
483 clock-names = "apb_pclk";
486 gpio6: gpio@f7022000 {
487 compatible = "arm,pl061", "arm,primecell";
488 reg = <0x0 0xf7022000 0x0 0x1000>;
489 interrupts = <0 58 0x4>;
492 gpio-ranges = <&pmx0 0 104 8>;
493 interrupt-controller;
494 #interrupt-cells = <2>;
495 clocks = <&ao_ctrl 2>;
496 clock-names = "apb_pclk";
499 gpio7: gpio@f7023000 {
500 compatible = "arm,pl061", "arm,primecell";
501 reg = <0x0 0xf7023000 0x0 0x1000>;
502 interrupts = <0 59 0x4>;
505 gpio-ranges = <&pmx0 0 112 8>;
506 interrupt-controller;
507 #interrupt-cells = <2>;
508 clocks = <&ao_ctrl 2>;
509 clock-names = "apb_pclk";
512 gpio8: gpio@f7024000 {
513 compatible = "arm,pl061", "arm,primecell";
514 reg = <0x0 0xf7024000 0x0 0x1000>;
515 interrupts = <0 60 0x4>;
518 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
519 interrupt-controller;
520 #interrupt-cells = <2>;
521 clocks = <&ao_ctrl 2>;
522 clock-names = "apb_pclk";
525 gpio9: gpio@f7025000 {
526 compatible = "arm,pl061", "arm,primecell";
527 reg = <0x0 0xf7025000 0x0 0x1000>;
528 interrupts = <0 61 0x4>;
531 gpio-ranges = <&pmx0 0 8 8>;
532 interrupt-controller;
533 #interrupt-cells = <2>;
534 clocks = <&ao_ctrl 2>;
535 clock-names = "apb_pclk";
538 gpio10: gpio@f7026000 {
539 compatible = "arm,pl061", "arm,primecell";
540 reg = <0x0 0xf7026000 0x0 0x1000>;
541 interrupts = <0 62 0x4>;
544 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
545 interrupt-controller;
546 #interrupt-cells = <2>;
547 clocks = <&ao_ctrl 2>;
548 clock-names = "apb_pclk";
551 gpio11: gpio@f7027000 {
552 compatible = "arm,pl061", "arm,primecell";
553 reg = <0x0 0xf7027000 0x0 0x1000>;
554 interrupts = <0 63 0x4>;
557 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
558 interrupt-controller;
559 #interrupt-cells = <2>;
560 clocks = <&ao_ctrl 2>;
561 clock-names = "apb_pclk";
564 gpio12: gpio@f7028000 {
565 compatible = "arm,pl061", "arm,primecell";
566 reg = <0x0 0xf7028000 0x0 0x1000>;
567 interrupts = <0 64 0x4>;
570 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
573 clocks = <&ao_ctrl 2>;
574 clock-names = "apb_pclk";
577 gpio13: gpio@f7029000 {
578 compatible = "arm,pl061", "arm,primecell";
579 reg = <0x0 0xf7029000 0x0 0x1000>;
580 interrupts = <0 65 0x4>;
583 gpio-ranges = <&pmx0 0 48 8>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
586 clocks = <&ao_ctrl 2>;
587 clock-names = "apb_pclk";
590 gpio14: gpio@f702a000 {
591 compatible = "arm,pl061", "arm,primecell";
592 reg = <0x0 0xf702a000 0x0 0x1000>;
593 interrupts = <0 66 0x4>;
596 gpio-ranges = <&pmx0 0 56 8>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
599 clocks = <&ao_ctrl 2>;
600 clock-names = "apb_pclk";
603 gpio15: gpio@f702b000 {
604 compatible = "arm,pl061", "arm,primecell";
605 reg = <0x0 0xf702b000 0x0 0x1000>;
606 interrupts = <0 67 0x4>;
614 interrupt-controller;
615 #interrupt-cells = <2>;
616 clocks = <&ao_ctrl 2>;
617 clock-names = "apb_pclk";
620 gpio16: gpio@f702c000 {
621 compatible = "arm,pl061", "arm,primecell";
622 reg = <0x0 0xf702c000 0x0 0x1000>;
623 interrupts = <0 68 0x4>;
626 gpio-ranges = <&pmx0 0 127 8>;
627 interrupt-controller;
628 #interrupt-cells = <2>;
629 clocks = <&ao_ctrl 2>;
630 clock-names = "apb_pclk";
633 gpio17: gpio@f702d000 {
634 compatible = "arm,pl061", "arm,primecell";
635 reg = <0x0 0xf702d000 0x0 0x1000>;
636 interrupts = <0 69 0x4>;
639 gpio-ranges = <&pmx0 0 135 8>;
640 interrupt-controller;
641 #interrupt-cells = <2>;
642 clocks = <&ao_ctrl 2>;
643 clock-names = "apb_pclk";
646 gpio18: gpio@f702e000 {
647 compatible = "arm,pl061", "arm,primecell";
648 reg = <0x0 0xf702e000 0x0 0x1000>;
649 interrupts = <0 70 0x4>;
652 gpio-ranges = <&pmx0 0 143 8>;
653 interrupt-controller;
654 #interrupt-cells = <2>;
655 clocks = <&ao_ctrl 2>;
656 clock-names = "apb_pclk";
659 gpio19: gpio@f702f000 {
660 compatible = "arm,pl061", "arm,primecell";
661 reg = <0x0 0xf702f000 0x0 0x1000>;
662 interrupts = <0 71 0x4>;
665 gpio-ranges = <&pmx0 0 151 8>;
666 interrupt-controller;
667 #interrupt-cells = <2>;
668 clocks = <&ao_ctrl 2>;
669 clock-names = "apb_pclk";
673 compatible = "arm,pl022", "arm,primecell";
674 reg = <0x0 0xf7106000 0x0 0x1000>;
675 interrupts = <0 50 4>;
678 clocks = <&sys_ctrl HI6220_SPI_CLK>;
679 clock-names = "apb_pclk";
680 pinctrl-names = "default";
681 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
683 cs-gpios = <&gpio6 2 0>;
688 compatible = "snps,designware-i2c";
689 reg = <0x0 0xf7100000 0x0 0x1000>;
690 interrupts = <0 44 4>;
691 clocks = <&sys_ctrl HI6220_I2C0_CLK>;
692 i2c-sda-hold-time-ns = <300>;
693 pinctrl-names = "default";
694 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
699 compatible = "snps,designware-i2c";
700 reg = <0x0 0xf7101000 0x0 0x1000>;
701 clocks = <&sys_ctrl HI6220_I2C1_CLK>;
702 interrupts = <0 45 4>;
703 i2c-sda-hold-time-ns = <300>;
704 pinctrl-names = "default";
705 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
710 compatible = "snps,designware-i2c";
711 reg = <0x0 0xf7102000 0x0 0x1000>;
712 clocks = <&sys_ctrl HI6220_I2C2_CLK>;
713 interrupts = <0 46 4>;
714 i2c-sda-hold-time-ns = <300>;
715 pinctrl-names = "default";
716 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
720 fixed_5v_hub: regulator@0 {
721 compatible = "regulator-fixed";
722 regulator-name = "fixed_5v_hub";
723 regulator-min-microvolt = <5000000>;
724 regulator-max-microvolt = <5000000>;
731 compatible = "hisilicon,hi6220-usb-phy";
733 phy-supply = <&fixed_5v_hub>;
734 hisilicon,peripheral-syscon = <&sys_ctrl>;
738 compatible = "hisilicon,hi6220-usb";
739 reg = <0x0 0xf72c0000 0x0 0x40000>;
741 phy-names = "usb2-phy";
742 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
746 g-rx-fifo-size = <512>;
747 g-np-tx-fifo-size = <128>;
748 g-tx-fifo-size = <128 128 128 128 128 128>;
749 interrupts = <0 77 0x4>;
752 mailbox: mailbox@f7510000 {
753 compatible = "hisilicon,hi6220-mbox";
754 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
755 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
756 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
760 dwmmc_0: dwmmc0@f723d000 {
761 compatible = "hisilicon,hi6220-dw-mshc";
765 reg = <0x0 0xf723d000 0x0 0x1000>;
766 interrupts = <0x0 0x48 0x4>;
767 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
768 clock-names = "ciu", "biu";
770 vmmc-supply = <&ldo19>;
771 pinctrl-names = "default";
772 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
773 &emmc_cfg_func &emmc_rst_cfg_func>;
776 dwmmc_1: dwmmc1@f723e000 {
777 compatible = "hisilicon,hi6220-dw-mshc";
779 card-detect-delay = <200>;
780 hisilicon,peripheral-syscon = <&ao_ctrl>;
782 reg = <0x0 0xf723e000 0x0 0x1000>;
783 interrupts = <0x0 0x49 0x4>;
784 #address-cells = <0x1>;
786 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
787 clock-names = "ciu", "biu";
788 vqmmc-supply = <&ldo7>;
789 vmmc-supply = <&ldo10>;
792 cd-gpios = <&gpio1 0 1>;
793 pinctrl-names = "default", "idle";
794 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
795 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
798 dwmmc_2: dwmmc2@f723f000 {
799 compatible = "hisilicon,hi6220-dw-mshc";
801 reg = <0x0 0xf723f000 0x0 0x1000>;
802 interrupts = <0x0 0x4a 0x4>;
803 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
804 clock-names = "ciu", "biu";
807 pinctrl-names = "default", "idle";
808 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
809 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
812 tsensor: tsensor@0,f7030700 {
813 compatible = "hisilicon,tsensor";
814 reg = <0x0 0xf7030700 0x0 0x1000>;
815 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&sys_ctrl 22>;
817 clock-names = "thermal_clk";
818 #thermal-sensor-cells = <1>;
824 polling-delay = <1000>;
825 polling-delay-passive = <100>;
826 sustainable-power = <3326>;
829 thermal-sensors = <&tsensor 2>;
832 threshold: trip-point@0 {
833 temperature = <65000>;
838 target: trip-point@1 {
839 temperature = <75000>;
848 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;