2 * dts file for Hisilicon D02 Development Board
4 * Copyright (C) 2014,2015 Hisilicon Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip05-d02";
16 interrupt-parent = <&gic>;
21 compatible = "arm,psci-0.2";
90 compatible = "arm,cortex-a57", "arm,armv8";
92 enable-method = "psci";
93 next-level-cache = <&cluster0_l2>;
98 compatible = "arm,cortex-a57", "arm,armv8";
100 enable-method = "psci";
101 next-level-cache = <&cluster0_l2>;
106 compatible = "arm,cortex-a57", "arm,armv8";
108 enable-method = "psci";
109 next-level-cache = <&cluster0_l2>;
114 compatible = "arm,cortex-a57", "arm,armv8";
116 enable-method = "psci";
117 next-level-cache = <&cluster0_l2>;
122 compatible = "arm,cortex-a57", "arm,armv8";
124 enable-method = "psci";
125 next-level-cache = <&cluster1_l2>;
130 compatible = "arm,cortex-a57", "arm,armv8";
132 enable-method = "psci";
133 next-level-cache = <&cluster1_l2>;
138 compatible = "arm,cortex-a57", "arm,armv8";
140 enable-method = "psci";
141 next-level-cache = <&cluster1_l2>;
146 compatible = "arm,cortex-a57", "arm,armv8";
148 enable-method = "psci";
149 next-level-cache = <&cluster1_l2>;
154 compatible = "arm,cortex-a57", "arm,armv8";
156 enable-method = "psci";
157 next-level-cache = <&cluster2_l2>;
162 compatible = "arm,cortex-a57", "arm,armv8";
164 enable-method = "psci";
165 next-level-cache = <&cluster2_l2>;
170 compatible = "arm,cortex-a57", "arm,armv8";
172 enable-method = "psci";
173 next-level-cache = <&cluster2_l2>;
178 compatible = "arm,cortex-a57", "arm,armv8";
180 enable-method = "psci";
181 next-level-cache = <&cluster2_l2>;
186 compatible = "arm,cortex-a57", "arm,armv8";
188 enable-method = "psci";
189 next-level-cache = <&cluster3_l2>;
194 compatible = "arm,cortex-a57", "arm,armv8";
196 enable-method = "psci";
197 next-level-cache = <&cluster3_l2>;
202 compatible = "arm,cortex-a57", "arm,armv8";
204 enable-method = "psci";
205 next-level-cache = <&cluster3_l2>;
210 compatible = "arm,cortex-a57", "arm,armv8";
212 enable-method = "psci";
213 next-level-cache = <&cluster3_l2>;
216 cluster0_l2: l2-cache0 {
217 compatible = "cache";
220 cluster1_l2: l2-cache1 {
221 compatible = "cache";
224 cluster2_l2: l2-cache2 {
225 compatible = "cache";
228 cluster3_l2: l2-cache3 {
229 compatible = "cache";
233 gic: interrupt-controller@8d000000 {
234 compatible = "arm,gic-v3";
235 #interrupt-cells = <3>;
236 #address-cells = <2>;
239 interrupt-controller;
240 #redistributor-regions = <1>;
241 redistributor-stride = <0x0 0x30000>;
242 reg = <0x0 0x8d000000 0 0x10000>, /* GICD */
243 <0x0 0x8d100000 0 0x300000>, /* GICR */
244 <0x0 0xfe000000 0 0x10000>, /* GICC */
245 <0x0 0xfe010000 0 0x10000>, /* GICH */
246 <0x0 0xfe020000 0 0x10000>; /* GICV */
247 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
249 its_peri: interrupt-controller@8c000000 {
250 compatible = "arm,gic-v3-its";
253 reg = <0x0 0x8c000000 0x0 0x40000>;
256 its_m3: interrupt-controller@a3000000 {
257 compatible = "arm,gic-v3-its";
260 reg = <0x0 0xa3000000 0x0 0x40000>;
263 its_pcie: interrupt-controller@b7000000 {
264 compatible = "arm,gic-v3-its";
267 reg = <0x0 0xb7000000 0x0 0x40000>;
270 its_dsa: interrupt-controller@c6000000 {
271 compatible = "arm,gic-v3-its";
274 reg = <0x0 0xc6000000 0x0 0x40000>;
279 compatible = "arm,armv8-timer";
280 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
281 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
282 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
283 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
287 compatible = "arm,cortex-a57-pmu";
288 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
292 compatible = "simple-bus";
293 #address-cells = <2>;
297 refclk200mhz: refclk200mhz {
298 compatible = "fixed-clock";
300 clock-frequency = <200000000>;
303 peri_c_subctrl: syscon@80000000 {
304 compatible = "hisilicon,hip05-perisubc", "syscon";
305 reg = < 0x0 0x80000000 0x0 0x10000>;
308 uart0: uart@80300000 {
309 compatible = "snps,dw-apb-uart";
310 reg = <0x0 0x80300000 0x0 0x10000>;
311 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&refclk200mhz>;
313 clock-names = "apb_pclk";
319 uart1: uart@80310000 {
320 compatible = "snps,dw-apb-uart";
321 reg = <0x0 0x80310000 0x0 0x10000>;
322 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&refclk200mhz>;
324 clock-names = "apb_pclk";
330 lbc: localbus@80380000 {
331 compatible = "hisilicon,hisi-localbus", "simple-bus";
332 reg = <0x0 0x80380000 0x0 0x10000>;
336 peri_gpio0: gpio@802e0000 {
337 #address-cells = <1>;
339 compatible = "snps,dw-apb-gpio";
340 reg = <0x0 0x802e0000 0x0 0x10000>;
343 porta: gpio-controller@0 {
344 compatible = "snps,dw-apb-gpio-port";
347 snps,nr-gpios = <32>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
351 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
355 peri_gpio1: gpio@802f0000 {
356 #address-cells = <1>;
358 compatible = "snps,dw-apb-gpio";
359 reg = <0x0 0x802f0000 0x0 0x10000>;
362 portb: gpio-controller@0 {
363 compatible = "snps,dw-apb-gpio-port";
366 snps,nr-gpios = <32>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
370 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;