2 * dts file for Hisilicon D02 Development Board
4 * Copyright (C) 2014,2015 Hisilicon Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip05-d02";
16 interrupt-parent = <&gic>;
21 compatible = "arm,psci-0.2";
90 compatible = "arm,cortex-a57", "arm,armv8";
92 enable-method = "psci";
93 next-level-cache = <&cluster0_l2>;
98 compatible = "arm,cortex-a57", "arm,armv8";
100 enable-method = "psci";
101 next-level-cache = <&cluster0_l2>;
106 compatible = "arm,cortex-a57", "arm,armv8";
108 enable-method = "psci";
109 next-level-cache = <&cluster0_l2>;
114 compatible = "arm,cortex-a57", "arm,armv8";
116 enable-method = "psci";
117 next-level-cache = <&cluster0_l2>;
122 compatible = "arm,cortex-a57", "arm,armv8";
124 enable-method = "psci";
125 next-level-cache = <&cluster1_l2>;
130 compatible = "arm,cortex-a57", "arm,armv8";
132 enable-method = "psci";
133 next-level-cache = <&cluster1_l2>;
138 compatible = "arm,cortex-a57", "arm,armv8";
140 enable-method = "psci";
141 next-level-cache = <&cluster1_l2>;
146 compatible = "arm,cortex-a57", "arm,armv8";
148 enable-method = "psci";
149 next-level-cache = <&cluster1_l2>;
154 compatible = "arm,cortex-a57", "arm,armv8";
156 enable-method = "psci";
157 next-level-cache = <&cluster2_l2>;
162 compatible = "arm,cortex-a57", "arm,armv8";
164 enable-method = "psci";
165 next-level-cache = <&cluster2_l2>;
170 compatible = "arm,cortex-a57", "arm,armv8";
172 enable-method = "psci";
173 next-level-cache = <&cluster2_l2>;
178 compatible = "arm,cortex-a57", "arm,armv8";
180 enable-method = "psci";
181 next-level-cache = <&cluster2_l2>;
186 compatible = "arm,cortex-a57", "arm,armv8";
188 enable-method = "psci";
189 next-level-cache = <&cluster3_l2>;
194 compatible = "arm,cortex-a57", "arm,armv8";
196 enable-method = "psci";
197 next-level-cache = <&cluster3_l2>;
202 compatible = "arm,cortex-a57", "arm,armv8";
204 enable-method = "psci";
205 next-level-cache = <&cluster3_l2>;
210 compatible = "arm,cortex-a57", "arm,armv8";
212 enable-method = "psci";
213 next-level-cache = <&cluster3_l2>;
216 cluster0_l2: l2-cache0 {
217 compatible = "cache";
220 cluster1_l2: l2-cache1 {
221 compatible = "cache";
224 cluster2_l2: l2-cache2 {
225 compatible = "cache";
228 cluster3_l2: l2-cache3 {
229 compatible = "cache";
233 gic: interrupt-controller@8d000000 {
234 compatible = "arm,gic-v3";
235 #interrupt-cells = <3>;
236 #address-cells = <2>;
239 interrupt-controller;
240 #redistributor-regions = <1>;
241 redistributor-stride = <0x0 0x30000>;
242 reg = <0x0 0x8d000000 0 0x10000>, /* GICD */
243 <0x0 0x8d100000 0 0x300000>, /* GICR */
244 <0x0 0xfe000000 0 0x10000>, /* GICC */
245 <0x0 0xfe010000 0 0x10000>, /* GICH */
246 <0x0 0xfe020000 0 0x10000>; /* GICV */
247 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
249 its_peri: interrupt-controller@8c000000 {
250 compatible = "arm,gic-v3-its";
252 reg = <0x0 0x8c000000 0x0 0x40000>;
255 its_m3: interrupt-controller@a3000000 {
256 compatible = "arm,gic-v3-its";
258 reg = <0x0 0xa3000000 0x0 0x40000>;
261 its_pcie: interrupt-controller@b7000000 {
262 compatible = "arm,gic-v3-its";
264 reg = <0x0 0xb7000000 0x0 0x40000>;
267 its_dsa: interrupt-controller@c6000000 {
268 compatible = "arm,gic-v3-its";
270 reg = <0x0 0xc6000000 0x0 0x40000>;
275 compatible = "arm,armv8-timer";
276 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
277 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
278 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
279 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
283 compatible = "arm,cortex-a57-pmu";
284 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
288 compatible = "simple-bus";
289 #address-cells = <2>;
293 refclk200mhz: refclk200mhz {
294 compatible = "fixed-clock";
296 clock-frequency = <200000000>;
299 peri_c_subctrl: syscon@80000000 {
300 compatible = "hisilicon,hip05-perisubc", "syscon";
301 reg = < 0x0 0x80000000 0x0 0x10000>;
304 uart0: uart@80300000 {
305 compatible = "snps,dw-apb-uart";
306 reg = <0x0 0x80300000 0x0 0x10000>;
307 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&refclk200mhz>;
309 clock-names = "apb_pclk";
315 uart1: uart@80310000 {
316 compatible = "snps,dw-apb-uart";
317 reg = <0x0 0x80310000 0x0 0x10000>;
318 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&refclk200mhz>;
320 clock-names = "apb_pclk";
326 peri_gpio0: gpio@802e0000 {
327 #address-cells = <1>;
329 compatible = "snps,dw-apb-gpio";
330 reg = <0x0 0x802e0000 0x0 0x10000>;
333 porta: gpio-controller@0 {
334 compatible = "snps,dw-apb-gpio-port";
337 snps,nr-gpios = <32>;
339 interrupt-controller;
340 #interrupt-cells = <2>;
341 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
345 peri_gpio1: gpio@802f0000 {
346 #address-cells = <1>;
348 compatible = "snps,dw-apb-gpio";
349 reg = <0x0 0x802f0000 0x0 0x10000>;
352 portb: gpio-controller@0 {
353 compatible = "snps,dw-apb-gpio-port";
356 snps,nr-gpios = <32>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
360 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;