arch/arm64/boot/dts/lg/lg1312.dtsi

   1 /*
   2  * dts file for lg1312 SoC
   3  *
   4  * Copyright (C) 2016, LG Electronics
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         compatible = "lge,lg1312";
  15         interrupt-parent = <&gic>;
  16
  17         cpus {
  18                 #address-cells = <2>;
  19                 #size-cells = <0>;
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a53", "arm,armv8";
  24                         reg = <0x0 0x0>;
  25                         next-level-cache = <&L2_0>;
  26                 };
  27                 cpu1: cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a53", "arm,armv8";
  30                         reg = <0x0 0x1>;
  31                         enable-method = "psci";
  32                         next-level-cache = <&L2_0>;
  33                 };
  34                 cpu2: cpu@2 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a53", "arm,armv8";
  37                         reg = <0x0 0x2>;
  38                         enable-method = "psci";
  39                         next-level-cache = <&L2_0>;
  40                 };
  41                 cpu3: cpu@3 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a53", "arm,armv8";
  44                         reg = <0x0 0x3>;
  45                         enable-method = "psci";
  46                         next-level-cache = <&L2_0>;
  47                 };
  48                 L2_0: l2-cache0 {
  49                         compatible = "cache";
  50                 };
  51         };
  52
  53         psci {
  54                 compatible  = "arm,psci-0.2", "arm,psci";
  55                 method = "smc";
  56                 cpu_suspend = <0x84000001>;
  57                 cpu_off = <0x84000002>;
  58                 cpu_on = <0x84000003>;
  59         };
  60
  61         gic: interrupt-controller@c0001000 {
  62                 #interrupt-cells = <3>;
  63                 compatible = "arm,gic-400";
  64                 interrupt-controller;
  65                 reg = <0x0 0xc0001000 0x1000>,
  66                       <0x0 0xc0002000 0x2000>,
  67                       <0x0 0xc0004000 0x2000>,
  68                       <0x0 0xc0006000 0x2000>;
  69         };
  70
  71         pmu {
  72                 compatible = "arm,cortex-a53-pmu";
  73                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
  74                              <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
  77                 interrupt-affinity = <&cpu0>,
  78                                      <&cpu1>,
  79                                      <&cpu2>,
  80                                      <&cpu3>;
  81         };
  82
  83         timer {
  84                 compatible = "arm,armv8-timer";
  85                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
  86                               IRQ_TYPE_LEVEL_LOW)>,
  87                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
  88                               IRQ_TYPE_LEVEL_LOW)>,
  89                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
  90                               IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
  92                               IRQ_TYPE_LEVEL_LOW)>;
  93         };
  94
  95         clk_bus: clk_bus {
  96                 #clock-cells = <0>;
  97
  98                 compatible = "fixed-clock";
  99                 clock-frequency = <198000000>;
 100                 clock-output-names = "BUSCLK";
 101         };
 102
 103         soc {
 104                 #address-cells = <2>;
 105                 #size-cells = <1>;
 106
 107                 compatible = "simple-bus";
 108                 interrupt-parent = <&gic>;
 109                 ranges;
 110
 111                 eth0: ethernet@c1b00000 {
 112                         compatible = "cdns,gem";
 113                         reg = <0x0 0xc1b00000 0x1000>;
 114                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 115                         clocks = <&clk_bus>, <&clk_bus>;
 116                         clock-names = "hclk", "pclk";
 117                         phy-mode = "rmii";
 118                         /* Filled in by boot */
 119                         mac-address = [ 00 00 00 00 00 00 ];
 120                 };
 121         };
 122
 123         amba {
 124                 #address-cells = <2>;
 125                 #size-cells = <1>;
 126                 #interrupts-cells = <3>;
 127
 128                 compatible = "simple-bus";
 129                 interrupt-parent = <&gic>;
 130                 ranges;
 131
 132                 timers: timer@fd100000 {
 133                         compatible = "arm,sp804";
 134                         reg = <0x0 0xfd100000 0x1000>;
 135                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 136                         clocks = <&clk_bus>;
 137                         clock-names = "apb_pclk";
 138                 };
 139                 wdog: watchdog@fd200000 {
 140                         compatible = "arm,sp805", "arm,primecell";
 141                         reg = <0x0 0xfd200000 0x1000>;
 142                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 143                         clocks = <&clk_bus>;
 144                         clock-names = "apb_pclk";
 145                 };
 146                 uart0: serial@fe000000 {
 147                         compatible = "arm,pl011", "arm,primecell";
 148                         reg = <0x0 0xfe000000 0x1000>;
 149                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 150                         clocks = <&clk_bus>;
 151                         clock-names = "apb_pclk";
 152                         status="disabled";
 153                 };
 154                 uart1: serial@fe100000 {
 155                         compatible = "arm,pl011", "arm,primecell";
 156                         reg = <0x0 0xfe100000 0x1000>;
 157                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 158                         clocks = <&clk_bus>;
 159                         clock-names = "apb_pclk";
 160                         status="disabled";
 161                 };
 162                 uart2: serial@fe200000 {
 163                         compatible = "arm,pl011", "arm,primecell";
 164                         reg = <0x0 0xfe200000 0x1000>;
 165                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 166                         clocks = <&clk_bus>;
 167                         clock-names = "apb_pclk";
 168                         status="disabled";
 169                 };
 170                 spi0: ssp@fe800000 {
 171                         compatible = "arm,pl022", "arm,primecell";
 172                         reg = <0x0 0xfe800000 0x1000>;
 173                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 174                         clocks = <&clk_bus>;
 175                         clock-names = "apb_pclk";
 176                 };
 177                 spi1: ssp@fe900000 {
 178                         compatible = "arm,pl022", "arm,primecell";
 179                         reg = <0x0 0xfe900000 0x1000>;
 180                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 181                         clocks = <&clk_bus>;
 182                         clock-names = "apb_pclk";
 183                 };
 184                 dmac0: dma@c1128000 {
 185                         compatible = "arm,pl330", "arm,primecell";
 186                         reg = <0x0 0xc1128000 0x1000>;
 187                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 188                         clocks = <&clk_bus>;
 189                         clock-names = "apb_pclk";
 190                 };
 191                 gpio0: gpio@fd400000 {
 192                         #gpio-cells = <2>;
 193                         compatible = "arm,pl061", "arm,primecell";
 194                         gpio-controller;
 195                         reg = <0x0 0xfd400000 0x1000>;
 196                         clocks = <&clk_bus>;
 197                         clock-names = "apb_pclk";
 198                         status="disabled";
 199                 };
 200                 gpio1: gpio@fd410000 {
 201                         #gpio-cells = <2>;
 202                         compatible = "arm,pl061", "arm,primecell";
 203                         gpio-controller;
 204                         reg = <0x0 0xfd410000 0x1000>;
 205                         clocks = <&clk_bus>;
 206                         clock-names = "apb_pclk";
 207                         status="disabled";
 208                 };
 209                 gpio2: gpio@fd420000 {
 210                         #gpio-cells = <2>;
 211                         compatible = "arm,pl061", "arm,primecell";
 212                         gpio-controller;
 213                         reg = <0x0 0xfd420000 0x1000>;
 214                         clocks = <&clk_bus>;
 215                         clock-names = "apb_pclk";
 216                         status="disabled";
 217                 };
 218                 gpio3: gpio@fd430000 {
 219                         #gpio-cells = <2>;
 220                         compatible = "arm,pl061", "arm,primecell";
 221                         gpio-controller;
 222                         reg = <0x0 0xfd430000 0x1000>;
 223                         clocks = <&clk_bus>;
 224                         clock-names = "apb_pclk";
 225                 };
 226                 gpio4: gpio@fd440000 {
 227                         #gpio-cells = <2>;
 228                         compatible = "arm,pl061", "arm,primecell";
 229                         gpio-controller;
 230                         reg = <0x0 0xfd440000 0x1000>;
 231                         clocks = <&clk_bus>;
 232                         clock-names = "apb_pclk";
 233                         status="disabled";
 234                 };
 235                 gpio5: gpio@fd450000 {
 236                         #gpio-cells = <2>;
 237                         compatible = "arm,pl061", "arm,primecell";
 238                         gpio-controller;
 239                         reg = <0x0 0xfd450000 0x1000>;
 240                         clocks = <&clk_bus>;
 241                         clock-names = "apb_pclk";
 242                         status="disabled";
 243                 };
 244                 gpio6: gpio@fd460000 {
 245                         #gpio-cells = <2>;
 246                         compatible = "arm,pl061", "arm,primecell";
 247                         gpio-controller;
 248                         reg = <0x0 0xfd460000 0x1000>;
 249                         clocks = <&clk_bus>;
 250                         clock-names = "apb_pclk";
 251                         status="disabled";
 252                 };
 253                 gpio7: gpio@fd470000 {
 254                         #gpio-cells = <2>;
 255                         compatible = "arm,pl061", "arm,primecell";
 256                         gpio-controller;
 257                         reg = <0x0 0xfd470000 0x1000>;
 258                         clocks = <&clk_bus>;
 259                         clock-names = "apb_pclk";
 260                         status="disabled";
 261                 };
 262                 gpio8: gpio@fd480000 {
 263                         #gpio-cells = <2>;
 264                         compatible = "arm,pl061", "arm,primecell";
 265                         gpio-controller;
 266                         reg = <0x0 0xfd480000 0x1000>;
 267                         clocks = <&clk_bus>;
 268                         clock-names = "apb_pclk";
 269                         status="disabled";
 270                 };
 271                 gpio9: gpio@fd490000 {
 272                         #gpio-cells = <2>;
 273                         compatible = "arm,pl061", "arm,primecell";
 274                         gpio-controller;
 275                         reg = <0x0 0xfd490000 0x1000>;
 276                         clocks = <&clk_bus>;
 277                         clock-names = "apb_pclk";
 278                         status="disabled";
 279                 };
 280                 gpio10: gpio@fd4a0000 {
 281                         #gpio-cells = <2>;
 282                         compatible = "arm,pl061", "arm,primecell";
 283                         gpio-controller;
 284                         reg = <0x0 0xfd4a0000 0x1000>;
 285                         clocks = <&clk_bus>;
 286                         clock-names = "apb_pclk";
 287                         status="disabled";
 288                 };
 289                 gpio11: gpio@fd4b0000 {
 290                         #gpio-cells = <2>;
 291                         compatible = "arm,pl061", "arm,primecell";
 292                         gpio-controller;
 293                         reg = <0x0 0xfd4b0000 0x1000>;
 294                         clocks = <&clk_bus>;
 295                         clock-names = "apb_pclk";
 296                 };
 297                 gpio12: gpio@fd4c0000 {
 298                         #gpio-cells = <2>;
 299                         compatible = "arm,pl061", "arm,primecell";
 300                         gpio-controller;
 301                         reg = <0x0 0xfd4c0000 0x1000>;
 302                         clocks = <&clk_bus>;
 303                         clock-names = "apb_pclk";
 304                         status="disabled";
 305                 };
 306                 gpio13: gpio@fd4d0000 {
 307                         #gpio-cells = <2>;
 308                         compatible = "arm,pl061", "arm,primecell";
 309                         gpio-controller;
 310                         reg = <0x0 0xfd4d0000 0x1000>;
 311                         clocks = <&clk_bus>;
 312                         clock-names = "apb_pclk";
 313                         status="disabled";
 314                 };
 315                 gpio14: gpio@fd4e0000 {
 316                         #gpio-cells = <2>;
 317                         compatible = "arm,pl061", "arm,primecell";
 318                         gpio-controller;
 319                         reg = <0x0 0xfd4e0000 0x1000>;
 320                         clocks = <&clk_bus>;
 321                         clock-names = "apb_pclk";
 322                         status="disabled";
 323                 };
 324                 gpio15: gpio@fd4f0000 {
 325                         #gpio-cells = <2>;
 326                         compatible = "arm,pl061", "arm,primecell";
 327                         gpio-controller;
 328                         reg = <0x0 0xfd4f0000 0x1000>;
 329                         clocks = <&clk_bus>;
 330                         clock-names = "apb_pclk";
 331                         status="disabled";
 332                 };
 333                 gpio16: gpio@fd500000 {
 334                         #gpio-cells = <2>;
 335                         compatible = "arm,pl061", "arm,primecell";
 336                         gpio-controller;
 337                         reg = <0x0 0xfd500000 0x1000>;
 338                         clocks = <&clk_bus>;
 339                         clock-names = "apb_pclk";
 340                         status="disabled";
 341                 };
 342                 gpio17: gpio@fd510000 {
 343                         #gpio-cells = <2>;
 344                         compatible = "arm,pl061", "arm,primecell";
 345                         gpio-controller;
 346                         reg = <0x0 0xfd510000 0x1000>;
 347                         clocks = <&clk_bus>;
 348                         clock-names = "apb_pclk";
 349                 };
 350         };
 351 };