arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Eddie Huang <eddie.huang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/clock/mt8173-clk.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/phy/phy.h>
  18 #include <dt-bindings/power/mt8173-power.h>
  19 #include <dt-bindings/reset/mt8173-resets.h>
  20 #include "mt8173-pinfunc.h"
  21
  22 / {
  23         compatible = "mediatek,mt8173";
  24         interrupt-parent = <&sysirq>;
  25         #address-cells = <2>;
  26         #size-cells = <2>;
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu-map {
  33                         cluster0 {
  34                                 core0 {
  35                                         cpu = <&cpu0>;
  36                                 };
  37                                 core1 {
  38                                         cpu = <&cpu1>;
  39                                 };
  40                         };
  41
  42                         cluster1 {
  43                                 core0 {
  44                                         cpu = <&cpu2>;
  45                                 };
  46                                 core1 {
  47                                         cpu = <&cpu3>;
  48                                 };
  49                         };
  50                 };
  51
  52                 cpu0: cpu@0 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a53";
  55                         reg = <0x000>;
  56                         enable-method = "psci";
  57                         cpu-idle-states = <&CPU_SLEEP_0>;
  58                 };
  59
  60                 cpu1: cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53";
  63                         reg = <0x001>;
  64                         enable-method = "psci";
  65                         cpu-idle-states = <&CPU_SLEEP_0>;
  66                 };
  67
  68                 cpu2: cpu@100 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a57";
  71                         reg = <0x100>;
  72                         enable-method = "psci";
  73                         cpu-idle-states = <&CPU_SLEEP_0>;
  74                 };
  75
  76                 cpu3: cpu@101 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a57";
  79                         reg = <0x101>;
  80                         enable-method = "psci";
  81                         cpu-idle-states = <&CPU_SLEEP_0>;
  82                 };
  83
  84                 idle-states {
  85                         entry-method = "psci";
  86
  87                         CPU_SLEEP_0: cpu-sleep-0 {
  88                                 compatible = "arm,idle-state";
  89                                 local-timer-stop;
  90                                 entry-latency-us = <639>;
  91                                 exit-latency-us = <680>;
  92                                 min-residency-us = <1088>;
  93                                 arm,psci-suspend-param = <0x0010000>;
  94                         };
  95                 };
  96         };
  97
  98         psci {
  99                 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
 100                 method = "smc";
 101                 cpu_suspend   = <0x84000001>;
 102                 cpu_off       = <0x84000002>;
 103                 cpu_on        = <0x84000003>;
 104         };
 105
 106         clk26m: oscillator@0 {
 107                 compatible = "fixed-clock";
 108                 #clock-cells = <0>;
 109                 clock-frequency = <26000000>;
 110                 clock-output-names = "clk26m";
 111         };
 112
 113         clk32k: oscillator@1 {
 114                 compatible = "fixed-clock";
 115                 #clock-cells = <0>;
 116                 clock-frequency = <32000>;
 117                 clock-output-names = "clk32k";
 118         };
 119
 120         cpum_ck: oscillator@2 {
 121                 compatible = "fixed-clock";
 122                 #clock-cells = <0>;
 123                 clock-frequency = <0>;
 124                 clock-output-names = "cpum_ck";
 125         };
 126
 127         timer {
 128                 compatible = "arm,armv8-timer";
 129                 interrupt-parent = <&gic>;
 130                 interrupts = <GIC_PPI 13
 131                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 132                              <GIC_PPI 14
 133                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 134                              <GIC_PPI 11
 135                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 136                              <GIC_PPI 10
 137                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 138         };
 139
 140         soc {
 141                 #address-cells = <2>;
 142                 #size-cells = <2>;
 143                 compatible = "simple-bus";
 144                 ranges;
 145
 146                 topckgen: clock-controller@10000000 {
 147                         compatible = "mediatek,mt8173-topckgen";
 148                         reg = <0 0x10000000 0 0x1000>;
 149                         #clock-cells = <1>;
 150                 };
 151
 152                 infracfg: power-controller@10001000 {
 153                         compatible = "mediatek,mt8173-infracfg", "syscon";
 154                         reg = <0 0x10001000 0 0x1000>;
 155                         #clock-cells = <1>;
 156                         #reset-cells = <1>;
 157                 };
 158
 159                 pericfg: power-controller@10003000 {
 160                         compatible = "mediatek,mt8173-pericfg", "syscon";
 161                         reg = <0 0x10003000 0 0x1000>;
 162                         #clock-cells = <1>;
 163                         #reset-cells = <1>;
 164                 };
 165
 166                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 167                         compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
 168                         reg = <0 0x10005000 0 0x1000>;
 169                 };
 170
 171                 pio: pinctrl@0x10005000 {
 172                         compatible = "mediatek,mt8173-pinctrl";
 173                         reg = <0 0x1000b000 0 0x1000>;
 174                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
 175                         pins-are-numbered;
 176                         gpio-controller;
 177                         #gpio-cells = <2>;
 178                         interrupt-controller;
 179                         #interrupt-cells = <2>;
 180                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 181                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 182                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 183
 184                         i2c0_pins_a: i2c0 {
 185                                 pins1 {
 186                                         pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
 187                                                  <MT8173_PIN_46_SCL0__FUNC_SCL0>;
 188                                         bias-disable;
 189                                 };
 190                         };
 191
 192                         i2c1_pins_a: i2c1 {
 193                                 pins1 {
 194                                         pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
 195                                                  <MT8173_PIN_126_SCL1__FUNC_SCL1>;
 196                                         bias-disable;
 197                                 };
 198                         };
 199
 200                         i2c2_pins_a: i2c2 {
 201                                 pins1 {
 202                                         pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
 203                                                  <MT8173_PIN_44_SCL2__FUNC_SCL2>;
 204                                         bias-disable;
 205                                 };
 206                         };
 207
 208                         i2c3_pins_a: i2c3 {
 209                                 pins1 {
 210                                         pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
 211                                                  <MT8173_PIN_107_SCL3__FUNC_SCL3>;
 212                                         bias-disable;
 213                                 };
 214                         };
 215
 216                         i2c4_pins_a: i2c4 {
 217                                 pins1 {
 218                                         pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
 219                                                  <MT8173_PIN_134_SCL4__FUNC_SCL4>;
 220                                         bias-disable;
 221                                 };
 222                         };
 223
 224                         i2c6_pins_a: i2c6 {
 225                                 pins1 {
 226                                         pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
 227                                                  <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
 228                                         bias-disable;
 229                                 };
 230                         };
 231                 };
 232
 233                 scpsys: scpsys@10006000 {
 234                         compatible = "mediatek,mt8173-scpsys";
 235                         #power-domain-cells = <1>;
 236                         reg = <0 0x10006000 0 0x1000>;
 237                         clocks = <&clk26m>,
 238                                  <&topckgen CLK_TOP_MM_SEL>,
 239                                  <&topckgen CLK_TOP_VENC_SEL>,
 240                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
 241                         clock-names = "mfg", "mm", "venc", "venc_lt";
 242                         infracfg = <&infracfg>;
 243                 };
 244
 245                 watchdog: watchdog@10007000 {
 246                         compatible = "mediatek,mt8173-wdt",
 247                                      "mediatek,mt6589-wdt";
 248                         reg = <0 0x10007000 0 0x100>;
 249                 };
 250
 251                 timer: timer@10008000 {
 252                         compatible = "mediatek,mt8173-timer",
 253                                      "mediatek,mt6577-timer";
 254                         reg = <0 0x10008000 0 0x1000>;
 255                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
 256                         clocks = <&infracfg CLK_INFRA_CLK_13M>,
 257                                  <&topckgen CLK_TOP_RTC_SEL>;
 258                 };
 259
 260                 pwrap: pwrap@1000d000 {
 261                         compatible = "mediatek,mt8173-pwrap";
 262                         reg = <0 0x1000d000 0 0x1000>;
 263                         reg-names = "pwrap";
 264                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 265                         resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
 266                         reset-names = "pwrap";
 267                         clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
 268                         clock-names = "spi", "wrap";
 269                 };
 270
 271                 sysirq: intpol-controller@10200620 {
 272                         compatible = "mediatek,mt8173-sysirq",
 273                                      "mediatek,mt6577-sysirq";
 274                         interrupt-controller;
 275                         #interrupt-cells = <3>;
 276                         interrupt-parent = <&gic>;
 277                         reg = <0 0x10200620 0 0x20>;
 278                 };
 279
 280                 efuse: efuse@10206000 {
 281                         compatible = "mediatek,mt8173-efuse";
 282                         reg = <0 0x10206000 0 0x1000>;
 283                 };
 284
 285                 apmixedsys: clock-controller@10209000 {
 286                         compatible = "mediatek,mt8173-apmixedsys";
 287                         reg = <0 0x10209000 0 0x1000>;
 288                         #clock-cells = <1>;
 289                 };
 290
 291                 gic: interrupt-controller@10220000 {
 292                         compatible = "arm,gic-400";
 293                         #interrupt-cells = <3>;
 294                         interrupt-parent = <&gic>;
 295                         interrupt-controller;
 296                         reg = <0 0x10221000 0 0x1000>,
 297                               <0 0x10222000 0 0x2000>,
 298                               <0 0x10224000 0 0x2000>,
 299                               <0 0x10226000 0 0x2000>;
 300                         interrupts = <GIC_PPI 9
 301                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 302                 };
 303
 304                 uart0: serial@11002000 {
 305                         compatible = "mediatek,mt8173-uart",
 306                                      "mediatek,mt6577-uart";
 307                         reg = <0 0x11002000 0 0x400>;
 308                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 309                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 310                         clock-names = "baud", "bus";
 311                         status = "disabled";
 312                 };
 313
 314                 uart1: serial@11003000 {
 315                         compatible = "mediatek,mt8173-uart",
 316                                      "mediatek,mt6577-uart";
 317                         reg = <0 0x11003000 0 0x400>;
 318                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 319                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 320                         clock-names = "baud", "bus";
 321                         status = "disabled";
 322                 };
 323
 324                 uart2: serial@11004000 {
 325                         compatible = "mediatek,mt8173-uart",
 326                                      "mediatek,mt6577-uart";
 327                         reg = <0 0x11004000 0 0x400>;
 328                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 329                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 330                         clock-names = "baud", "bus";
 331                         status = "disabled";
 332                 };
 333
 334                 uart3: serial@11005000 {
 335                         compatible = "mediatek,mt8173-uart",
 336                                      "mediatek,mt6577-uart";
 337                         reg = <0 0x11005000 0 0x400>;
 338                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 339                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 340                         clock-names = "baud", "bus";
 341                         status = "disabled";
 342                 };
 343
 344                 i2c0: i2c@11007000 {
 345                         compatible = "mediatek,mt8173-i2c";
 346                         reg = <0 0x11007000 0 0x70>,
 347                               <0 0x11000100 0 0x80>;
 348                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
 349                         clock-div = <16>;
 350                         clocks = <&pericfg CLK_PERI_I2C0>,
 351                                  <&pericfg CLK_PERI_AP_DMA>;
 352                         clock-names = "main", "dma";
 353                         pinctrl-names = "default";
 354                         pinctrl-0 = <&i2c0_pins_a>;
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         status = "disabled";
 358                 };
 359
 360                 i2c1: i2c@11008000 {
 361                         compatible = "mediatek,mt8173-i2c";
 362                         reg = <0 0x11008000 0 0x70>,
 363                               <0 0x11000180 0 0x80>;
 364                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 365                         clock-div = <16>;
 366                         clocks = <&pericfg CLK_PERI_I2C1>,
 367                                  <&pericfg CLK_PERI_AP_DMA>;
 368                         clock-names = "main", "dma";
 369                         pinctrl-names = "default";
 370                         pinctrl-0 = <&i2c1_pins_a>;
 371                         #address-cells = <1>;
 372                         #size-cells = <0>;
 373                         status = "disabled";
 374                 };
 375
 376                 i2c2: i2c@11009000 {
 377                         compatible = "mediatek,mt8173-i2c";
 378                         reg = <0 0x11009000 0 0x70>,
 379                               <0 0x11000200 0 0x80>;
 380                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 381                         clock-div = <16>;
 382                         clocks = <&pericfg CLK_PERI_I2C2>,
 383                                  <&pericfg CLK_PERI_AP_DMA>;
 384                         clock-names = "main", "dma";
 385                         pinctrl-names = "default";
 386                         pinctrl-0 = <&i2c2_pins_a>;
 387                         #address-cells = <1>;
 388                         #size-cells = <0>;
 389                         status = "disabled";
 390                 };
 391
 392                 spi: spi@1100a000 {
 393                         compatible = "mediatek,mt8173-spi";
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                         reg = <0 0x1100a000 0 0x1000>;
 397                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
 398                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 399                                  <&topckgen CLK_TOP_SPI_SEL>,
 400                                  <&pericfg CLK_PERI_SPI0>;
 401                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 402                         status = "disabled";
 403                 };
 404
 405                 nor_flash: spi@1100d000 {
 406                         compatible = "mediatek,mt8173-nor";
 407                         reg = <0 0x1100d000 0 0xe0>;
 408                         clocks = <&pericfg CLK_PERI_SPI>,
 409                                  <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
 410                         clock-names = "spi", "sf";
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         status = "disabled";
 414                 };
 415
 416                 i2c3: i2c@11010000 {
 417                         compatible = "mediatek,mt8173-i2c";
 418                         reg = <0 0x11010000 0 0x70>,
 419                               <0 0x11000280 0 0x80>;
 420                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 421                         clock-div = <16>;
 422                         clocks = <&pericfg CLK_PERI_I2C3>,
 423                                  <&pericfg CLK_PERI_AP_DMA>;
 424                         clock-names = "main", "dma";
 425                         pinctrl-names = "default";
 426                         pinctrl-0 = <&i2c3_pins_a>;
 427                         #address-cells = <1>;
 428                         #size-cells = <0>;
 429                         status = "disabled";
 430                 };
 431
 432                 i2c4: i2c@11011000 {
 433                         compatible = "mediatek,mt8173-i2c";
 434                         reg = <0 0x11011000 0 0x70>,
 435                               <0 0x11000300 0 0x80>;
 436                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 437                         clock-div = <16>;
 438                         clocks = <&pericfg CLK_PERI_I2C4>,
 439                                  <&pericfg CLK_PERI_AP_DMA>;
 440                         clock-names = "main", "dma";
 441                         pinctrl-names = "default";
 442                         pinctrl-0 = <&i2c4_pins_a>;
 443                         #address-cells = <1>;
 444                         #size-cells = <0>;
 445                         status = "disabled";
 446                 };
 447
 448                 i2c6: i2c@11013000 {
 449                         compatible = "mediatek,mt8173-i2c";
 450                         reg = <0 0x11013000 0 0x70>,
 451                               <0 0x11000080 0 0x80>;
 452                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 453                         clock-div = <16>;
 454                         clocks = <&pericfg CLK_PERI_I2C6>,
 455                                  <&pericfg CLK_PERI_AP_DMA>;
 456                         clock-names = "main", "dma";
 457                         pinctrl-names = "default";
 458                         pinctrl-0 = <&i2c6_pins_a>;
 459                         #address-cells = <1>;
 460                         #size-cells = <0>;
 461                         status = "disabled";
 462                 };
 463
 464                 afe: audio-controller@11220000  {
 465                         compatible = "mediatek,mt8173-afe-pcm";
 466                         reg = <0 0x11220000 0 0x1000>;
 467                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
 468                         power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
 469                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 470                                  <&topckgen CLK_TOP_AUDIO_SEL>,
 471                                  <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 472                                  <&topckgen CLK_TOP_APLL1_DIV0>,
 473                                  <&topckgen CLK_TOP_APLL2_DIV0>,
 474                                  <&topckgen CLK_TOP_I2S0_M_SEL>,
 475                                  <&topckgen CLK_TOP_I2S1_M_SEL>,
 476                                  <&topckgen CLK_TOP_I2S2_M_SEL>,
 477                                  <&topckgen CLK_TOP_I2S3_M_SEL>,
 478                                  <&topckgen CLK_TOP_I2S3_B_SEL>;
 479                         clock-names = "infra_sys_audio_clk",
 480                                       "top_pdn_audio",
 481                                       "top_pdn_aud_intbus",
 482                                       "bck0",
 483                                       "bck1",
 484                                       "i2s0_m",
 485                                       "i2s1_m",
 486                                       "i2s2_m",
 487                                       "i2s3_m",
 488                                       "i2s3_b";
 489                         assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
 490                                           <&topckgen CLK_TOP_AUD_2_SEL>;
 491                         assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
 492                                                  <&topckgen CLK_TOP_APLL2>;
 493                 };
 494
 495                 mmc0: mmc@11230000 {
 496                         compatible = "mediatek,mt8173-mmc",
 497                                      "mediatek,mt8135-mmc";
 498                         reg = <0 0x11230000 0 0x1000>;
 499                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
 500                         clocks = <&pericfg CLK_PERI_MSDC30_0>,
 501                                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
 502                         clock-names = "source", "hclk";
 503                         status = "disabled";
 504                 };
 505
 506                 mmc1: mmc@11240000 {
 507                         compatible = "mediatek,mt8173-mmc",
 508                                      "mediatek,mt8135-mmc";
 509                         reg = <0 0x11240000 0 0x1000>;
 510                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 511                         clocks = <&pericfg CLK_PERI_MSDC30_1>,
 512                                  <&topckgen CLK_TOP_AXI_SEL>;
 513                         clock-names = "source", "hclk";
 514                         status = "disabled";
 515                 };
 516
 517                 mmc2: mmc@11250000 {
 518                         compatible = "mediatek,mt8173-mmc",
 519                                      "mediatek,mt8135-mmc";
 520                         reg = <0 0x11250000 0 0x1000>;
 521                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
 522                         clocks = <&pericfg CLK_PERI_MSDC30_2>,
 523                                  <&topckgen CLK_TOP_AXI_SEL>;
 524                         clock-names = "source", "hclk";
 525                         status = "disabled";
 526                 };
 527
 528                 mmc3: mmc@11260000 {
 529                         compatible = "mediatek,mt8173-mmc",
 530                                      "mediatek,mt8135-mmc";
 531                         reg = <0 0x11260000 0 0x1000>;
 532                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
 533                         clocks = <&pericfg CLK_PERI_MSDC30_3>,
 534                                  <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
 535                         clock-names = "source", "hclk";
 536                         status = "disabled";
 537                 };
 538
 539                 usb30: usb@11270000 {
 540                         compatible = "mediatek,mt8173-xhci";
 541                         reg = <0 0x11270000 0 0x1000>,
 542                               <0 0x11280700 0 0x0100>;
 543                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
 544                         power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 545                         clocks = <&topckgen CLK_TOP_USB30_SEL>,
 546                                  <&pericfg CLK_PERI_USB0>,
 547                                  <&pericfg CLK_PERI_USB1>;
 548                         clock-names = "sys_ck",
 549                                       "wakeup_deb_p0",
 550                                       "wakeup_deb_p1";
 551                         phys = <&phy_port0 PHY_TYPE_USB3>,
 552                                <&phy_port1 PHY_TYPE_USB2>;
 553                         mediatek,syscon-wakeup = <&pericfg>;
 554                         status = "okay";
 555                 };
 556
 557                 u3phy: usb-phy@11290000 {
 558                         compatible = "mediatek,mt8173-u3phy";
 559                         reg = <0 0x11290000 0 0x800>;
 560                         clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 561                         clock-names = "u3phya_ref";
 562                         #address-cells = <2>;
 563                         #size-cells = <2>;
 564                         ranges;
 565                         status = "okay";
 566
 567                         phy_port0: port@11290800 {
 568                                 reg = <0 0x11290800 0 0x800>;
 569                                 #phy-cells = <1>;
 570                                 status = "okay";
 571                         };
 572
 573                         phy_port1: port@11291000 {
 574                                 reg = <0 0x11291000 0 0x800>;
 575                                 #phy-cells = <1>;
 576                                 status = "okay";
 577                         };
 578                 };
 579
 580                 mmsys: clock-controller@14000000 {
 581                         compatible = "mediatek,mt8173-mmsys", "syscon";
 582                         reg = <0 0x14000000 0 0x1000>;
 583                         #clock-cells = <1>;
 584                 };
 585
 586                 pwm0: pwm@1401e000 {
 587                         compatible = "mediatek,mt8173-disp-pwm",
 588                                      "mediatek,mt6595-disp-pwm";
 589                         reg = <0 0x1401e000 0 0x1000>;
 590                         #pwm-cells = <2>;
 591                         clocks = <&mmsys CLK_MM_DISP_PWM026M>,
 592                                  <&mmsys CLK_MM_DISP_PWM0MM>;
 593                         clock-names = "main", "mm";
 594                         status = "disabled";
 595                 };
 596
 597                 pwm1: pwm@1401f000 {
 598                         compatible = "mediatek,mt8173-disp-pwm",
 599                                      "mediatek,mt6595-disp-pwm";
 600                         reg = <0 0x1401f000 0 0x1000>;
 601                         #pwm-cells = <2>;
 602                         clocks = <&mmsys CLK_MM_DISP_PWM126M>,
 603                                  <&mmsys CLK_MM_DISP_PWM1MM>;
 604                         clock-names = "main", "mm";
 605                         status = "disabled";
 606                 };
 607
 608                 imgsys: clock-controller@15000000 {
 609                         compatible = "mediatek,mt8173-imgsys", "syscon";
 610                         reg = <0 0x15000000 0 0x1000>;
 611                         #clock-cells = <1>;
 612                 };
 613
 614                 vdecsys: clock-controller@16000000 {
 615                         compatible = "mediatek,mt8173-vdecsys", "syscon";
 616                         reg = <0 0x16000000 0 0x1000>;
 617                         #clock-cells = <1>;
 618                 };
 619
 620                 vencsys: clock-controller@18000000 {
 621                         compatible = "mediatek,mt8173-vencsys", "syscon";
 622                         reg = <0 0x18000000 0 0x1000>;
 623                         #clock-cells = <1>;
 624                 };
 625
 626                 vencltsys: clock-controller@19000000 {
 627                         compatible = "mediatek,mt8173-vencltsys", "syscon";
 628                         reg = <0 0x19000000 0 0x1000>;
 629                         #clock-cells = <1>;
 630                 };
 631         };
 632 };
 633