arch/arm64/boot/dts/nvidia/tegra132.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/memory/tegra124-mc.h>
   4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7
   8 / {
   9         compatible = "nvidia,tegra132", "nvidia,tegra124";
  10         interrupt-parent = <&lic>;
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         pcie-controller@01003000 {
  15                 compatible = "nvidia,tegra124-pcie";
  16                 device_type = "pci";
  17                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  18                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  19                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  20                 reg-names = "pads", "afi", "cs";
  21                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  22                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  23                 interrupt-names = "intr", "msi";
  24
  25                 #interrupt-cells = <1>;
  26                 interrupt-map-mask = <0 0 0 0>;
  27                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  28
  29                 bus-range = <0x00 0xff>;
  30                 #address-cells = <3>;
  31                 #size-cells = <2>;
  32
  33                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  34                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  35                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  36                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  37                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  38
  39                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  40                          <&tegra_car TEGRA124_CLK_AFI>,
  41                          <&tegra_car TEGRA124_CLK_PLL_E>,
  42                          <&tegra_car TEGRA124_CLK_CML0>;
  43                 clock-names = "pex", "afi", "pll_e", "cml";
  44                 resets = <&tegra_car 70>,
  45                          <&tegra_car 72>,
  46                          <&tegra_car 74>;
  47                 reset-names = "pex", "afi", "pcie_x";
  48                 status = "disabled";
  49
  50                 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
  51                 phy-names = "pcie";
  52
  53                 pci@1,0 {
  54                         device_type = "pci";
  55                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  56                         reg = <0x000800 0 0 0 0>;
  57                         status = "disabled";
  58
  59                         #address-cells = <3>;
  60                         #size-cells = <2>;
  61                         ranges;
  62
  63                         nvidia,num-lanes = <2>;
  64                 };
  65
  66                 pci@2,0 {
  67                         device_type = "pci";
  68                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  69                         reg = <0x001000 0 0 0 0>;
  70                         status = "disabled";
  71
  72                         #address-cells = <3>;
  73                         #size-cells = <2>;
  74                         ranges;
  75
  76                         nvidia,num-lanes = <1>;
  77                 };
  78         };
  79
  80         host1x@50000000 {
  81                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  82                 reg = <0x0 0x50000000 0x0 0x00034000>;
  83                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  84                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  85                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  86                 clock-names = "host1x";
  87                 resets = <&tegra_car 28>;
  88                 reset-names = "host1x";
  89
  90                 #address-cells = <2>;
  91                 #size-cells = <2>;
  92
  93                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  94
  95                 dc@54200000 {
  96                         compatible = "nvidia,tegra124-dc";
  97                         reg = <0x0 0x54200000 0x0 0x00040000>;
  98                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  99                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
 100                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 101                         clock-names = "dc", "parent";
 102                         resets = <&tegra_car 27>;
 103                         reset-names = "dc";
 104
 105                         iommus = <&mc TEGRA_SWGROUP_DC>;
 106
 107                         nvidia,head = <0>;
 108                 };
 109
 110                 dc@54240000 {
 111                         compatible = "nvidia,tegra124-dc";
 112                         reg = <0x0 0x54240000 0x0 0x00040000>;
 113                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 114                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
 115                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 116                         clock-names = "dc", "parent";
 117                         resets = <&tegra_car 26>;
 118                         reset-names = "dc";
 119
 120                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 121
 122                         nvidia,head = <1>;
 123                 };
 124
 125                 hdmi@54280000 {
 126                         compatible = "nvidia,tegra124-hdmi";
 127                         reg = <0x0 0x54280000 0x0 0x00040000>;
 128                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 129                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
 130                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
 131                         clock-names = "hdmi", "parent";
 132                         resets = <&tegra_car 51>;
 133                         reset-names = "hdmi";
 134                         status = "disabled";
 135                 };
 136
 137                 sor@54540000 {
 138                         compatible = "nvidia,tegra124-sor";
 139                         reg = <0x0 0x54540000 0x0 0x00040000>;
 140                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 141                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
 142                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
 143                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
 144                                  <&tegra_car TEGRA124_CLK_CLK_M>;
 145                         clock-names = "sor", "parent", "dp", "safe";
 146                         resets = <&tegra_car 182>;
 147                         reset-names = "sor";
 148                         status = "disabled";
 149                 };
 150
 151                 dpaux: dpaux@545c0000 {
 152                         compatible = "nvidia,tegra124-dpaux";
 153                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 154                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 155                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
 156                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
 157                         clock-names = "dpaux", "parent";
 158                         resets = <&tegra_car 181>;
 159                         reset-names = "dpaux";
 160                         status = "disabled";
 161                 };
 162         };
 163
 164         gic: interrupt-controller@50041000 {
 165                 compatible = "arm,cortex-a15-gic";
 166                 #interrupt-cells = <3>;
 167                 interrupt-controller;
 168                 reg = <0x0 0x50041000 0x0 0x1000>,
 169                       <0x0 0x50042000 0x0 0x2000>,
 170                       <0x0 0x50044000 0x0 0x2000>,
 171                       <0x0 0x50046000 0x0 0x2000>;
 172                 interrupts = <GIC_PPI 9
 173                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 174                 interrupt-parent = <&gic>;
 175         };
 176
 177         gpu@57000000 {
 178                 compatible = "nvidia,gk20a";
 179                 reg = <0x0 0x57000000 0x0 0x01000000>,
 180                       <0x0 0x58000000 0x0 0x01000000>;
 181                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 183                 interrupt-names = "stall", "nonstall";
 184                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 185                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 186                 clock-names = "gpu", "pwr";
 187                 resets = <&tegra_car 184>;
 188                 reset-names = "gpu";
 189                 status = "disabled";
 190         };
 191
 192         lic: interrupt-controller@60004000 {
 193                 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
 194                 reg = <0x0 0x60004000 0x0 0x100>,
 195                       <0x0 0x60004100 0x0 0x100>,
 196                       <0x0 0x60004200 0x0 0x100>,
 197                       <0x0 0x60004300 0x0 0x100>,
 198                       <0x0 0x60004400 0x0 0x100>;
 199                 interrupt-controller;
 200                 #interrupt-cells = <3>;
 201                 interrupt-parent = <&gic>;
 202         };
 203
 204         timer@60005000 {
 205                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 206                 reg = <0x0 0x60005000 0x0 0x400>;
 207                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 208                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 209                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 214                 clock-names = "timer";
 215         };
 216
 217         tegra_car: clock@60006000 {
 218                 compatible = "nvidia,tegra132-car";
 219                 reg = <0x0 0x60006000 0x0 0x1000>;
 220                 #clock-cells = <1>;
 221                 #reset-cells = <1>;
 222                 nvidia,external-memory-controller = <&emc>;
 223         };
 224
 225         flow-controller@60007000 {
 226                 compatible = "nvidia,tegra124-flowctrl";
 227                 reg = <0x0 0x60007000 0x0 0x1000>;
 228         };
 229
 230         actmon@6000c800 {
 231                 compatible = "nvidia,tegra124-actmon";
 232                 reg = <0x0 0x6000c800 0x0 0x400>;
 233                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
 235                          <&tegra_car TEGRA124_CLK_EMC>;
 236                 clock-names = "actmon", "emc";
 237                 resets = <&tegra_car 119>;
 238                 reset-names = "actmon";
 239         };
 240
 241         gpio: gpio@6000d000 {
 242                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 243                 reg = <0x0 0x6000d000 0x0 0x1000>;
 244                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 245                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 246                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 247                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 248                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 249                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 250                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 251                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 252                 #gpio-cells = <2>;
 253                 gpio-controller;
 254                 #interrupt-cells = <2>;
 255                 interrupt-controller;
 256         };
 257
 258         apbdma: dma@60020000 {
 259                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 260                 reg = <0x0 0x60020000 0x0 0x1400>;
 261                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 271                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 282                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 284                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 285                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 288                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 293                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 294                 clock-names = "dma";
 295                 resets = <&tegra_car 34>;
 296                 reset-names = "dma";
 297                 #dma-cells = <1>;
 298         };
 299
 300         apbmisc@70000800 {
 301                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 302                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 303                       <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
 304         };
 305
 306         pinmux: pinmux@70000868 {
 307                 compatible = "nvidia,tegra124-pinmux";
 308                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 309                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
 310                       <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
 311         };
 312
 313         /*
 314          * There are two serial driver i.e. 8250 based simple serial
 315          * driver and APB DMA based serial driver for higher baudrate
 316          * and performance. To enable the 8250 based driver, the compatible
 317          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 318          * the APB DMA based serial driver, the compatible is
 319          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 320          */
 321         uarta: serial@70006000 {
 322                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 323                 reg = <0x0 0x70006000 0x0 0x40>;
 324                 reg-shift = <2>;
 325                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 326                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 327                 clock-names = "serial";
 328                 resets = <&tegra_car 6>;
 329                 reset-names = "serial";
 330                 dmas = <&apbdma 8>, <&apbdma 8>;
 331                 dma-names = "rx", "tx";
 332                 status = "disabled";
 333         };
 334
 335         uartb: serial@70006040 {
 336                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 337                 reg = <0x0 0x70006040 0x0 0x40>;
 338                 reg-shift = <2>;
 339                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 341                 clock-names = "serial";
 342                 resets = <&tegra_car 7>;
 343                 reset-names = "serial";
 344                 dmas = <&apbdma 9>, <&apbdma 9>;
 345                 dma-names = "rx", "tx";
 346                 status = "disabled";
 347         };
 348
 349         uartc: serial@70006200 {
 350                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 351                 reg = <0x0 0x70006200 0x0 0x40>;
 352                 reg-shift = <2>;
 353                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 354                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 355                 clock-names = "serial";
 356                 resets = <&tegra_car 55>;
 357                 reset-names = "serial";
 358                 dmas = <&apbdma 10>, <&apbdma 10>;
 359                 dma-names = "rx", "tx";
 360                 status = "disabled";
 361         };
 362
 363         uartd: serial@70006300 {
 364                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 365                 reg = <0x0 0x70006300 0x0 0x40>;
 366                 reg-shift = <2>;
 367                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 368                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 369                 clock-names = "serial";
 370                 resets = <&tegra_car 65>;
 371                 reset-names = "serial";
 372                 dmas = <&apbdma 19>, <&apbdma 19>;
 373                 dma-names = "rx", "tx";
 374                 status = "disabled";
 375         };
 376
 377         pwm: pwm@7000a000 {
 378                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 379                 reg = <0x0 0x7000a000 0x0 0x100>;
 380                 #pwm-cells = <2>;
 381                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 382                 clock-names = "pwm";
 383                 resets = <&tegra_car 17>;
 384                 reset-names = "pwm";
 385                 status = "disabled";
 386         };
 387
 388         i2c@7000c000 {
 389                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 390                 reg = <0x0 0x7000c000 0x0 0x100>;
 391                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 395                 clock-names = "div-clk";
 396                 resets = <&tegra_car 12>;
 397                 reset-names = "i2c";
 398                 dmas = <&apbdma 21>, <&apbdma 21>;
 399                 dma-names = "rx", "tx";
 400                 status = "disabled";
 401         };
 402
 403         i2c@7000c400 {
 404                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 405                 reg = <0x0 0x7000c400 0x0 0x100>;
 406                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 410                 clock-names = "div-clk";
 411                 resets = <&tegra_car 54>;
 412                 reset-names = "i2c";
 413                 dmas = <&apbdma 22>, <&apbdma 22>;
 414                 dma-names = "rx", "tx";
 415                 status = "disabled";
 416         };
 417
 418         i2c@7000c500 {
 419                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 420                 reg = <0x0 0x7000c500 0x0 0x100>;
 421                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 422                 #address-cells = <1>;
 423                 #size-cells = <0>;
 424                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 425                 clock-names = "div-clk";
 426                 resets = <&tegra_car 67>;
 427                 reset-names = "i2c";
 428                 dmas = <&apbdma 23>, <&apbdma 23>;
 429                 dma-names = "rx", "tx";
 430                 status = "disabled";
 431         };
 432
 433         i2c@7000c700 {
 434                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 435                 reg = <0x0 0x7000c700 0x0 0x100>;
 436                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 440                 clock-names = "div-clk";
 441                 resets = <&tegra_car 103>;
 442                 reset-names = "i2c";
 443                 dmas = <&apbdma 26>, <&apbdma 26>;
 444                 dma-names = "rx", "tx";
 445                 status = "disabled";
 446         };
 447
 448         i2c@7000d000 {
 449                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 450                 reg = <0x0 0x7000d000 0x0 0x100>;
 451                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 452                 #address-cells = <1>;
 453                 #size-cells = <0>;
 454                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 455                 clock-names = "div-clk";
 456                 resets = <&tegra_car 47>;
 457                 reset-names = "i2c";
 458                 dmas = <&apbdma 24>, <&apbdma 24>;
 459                 dma-names = "rx", "tx";
 460                 status = "disabled";
 461         };
 462
 463         i2c@7000d100 {
 464                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 465                 reg = <0x0 0x7000d100 0x0 0x100>;
 466                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 467                 #address-cells = <1>;
 468                 #size-cells = <0>;
 469                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 470                 clock-names = "div-clk";
 471                 resets = <&tegra_car 166>;
 472                 reset-names = "i2c";
 473                 dmas = <&apbdma 30>, <&apbdma 30>;
 474                 dma-names = "rx", "tx";
 475                 status = "disabled";
 476         };
 477
 478         spi@7000d400 {
 479                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 480                 reg = <0x0 0x7000d400 0x0 0x200>;
 481                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 482                 #address-cells = <1>;
 483                 #size-cells = <0>;
 484                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 485                 clock-names = "spi";
 486                 resets = <&tegra_car 41>;
 487                 reset-names = "spi";
 488                 dmas = <&apbdma 15>, <&apbdma 15>;
 489                 dma-names = "rx", "tx";
 490                 status = "disabled";
 491         };
 492
 493         spi@7000d600 {
 494                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 495                 reg = <0x0 0x7000d600 0x0 0x200>;
 496                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 497                 #address-cells = <1>;
 498                 #size-cells = <0>;
 499                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 500                 clock-names = "spi";
 501                 resets = <&tegra_car 44>;
 502                 reset-names = "spi";
 503                 dmas = <&apbdma 16>, <&apbdma 16>;
 504                 dma-names = "rx", "tx";
 505                 status = "disabled";
 506         };
 507
 508         spi@7000d800 {
 509                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 510                 reg = <0x0 0x7000d800 0x0 0x200>;
 511                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 512                 #address-cells = <1>;
 513                 #size-cells = <0>;
 514                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 515                 clock-names = "spi";
 516                 resets = <&tegra_car 46>;
 517                 reset-names = "spi";
 518                 dmas = <&apbdma 17>, <&apbdma 17>;
 519                 dma-names = "rx", "tx";
 520                 status = "disabled";
 521         };
 522
 523         spi@7000da00 {
 524                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 525                 reg = <0x0 0x7000da00 0x0 0x200>;
 526                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 530                 clock-names = "spi";
 531                 resets = <&tegra_car 68>;
 532                 reset-names = "spi";
 533                 dmas = <&apbdma 18>, <&apbdma 18>;
 534                 dma-names = "rx", "tx";
 535                 status = "disabled";
 536         };
 537
 538         spi@7000dc00 {
 539                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 540                 reg = <0x0 0x7000dc00 0x0 0x200>;
 541                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 545                 clock-names = "spi";
 546                 resets = <&tegra_car 104>;
 547                 reset-names = "spi";
 548                 dmas = <&apbdma 27>, <&apbdma 27>;
 549                 dma-names = "rx", "tx";
 550                 status = "disabled";
 551         };
 552
 553         spi@7000de00 {
 554                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 555                 reg = <0x0 0x7000de00 0x0 0x200>;
 556                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 560                 clock-names = "spi";
 561                 resets = <&tegra_car 105>;
 562                 reset-names = "spi";
 563                 dmas = <&apbdma 28>, <&apbdma 28>;
 564                 dma-names = "rx", "tx";
 565                 status = "disabled";
 566         };
 567
 568         rtc@7000e000 {
 569                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 570                 reg = <0x0 0x7000e000 0x0 0x100>;
 571                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 572                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 573                 clock-names = "rtc";
 574         };
 575
 576         pmc@7000e400 {
 577                 compatible = "nvidia,tegra124-pmc";
 578                 reg = <0x0 0x7000e400 0x0 0x400>;
 579                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 580                 clock-names = "pclk", "clk32k_in";
 581         };
 582
 583         fuse@7000f800 {
 584                 compatible = "nvidia,tegra124-efuse";
 585                 reg = <0x0 0x7000f800 0x0 0x400>;
 586                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 587                 clock-names = "fuse";
 588                 resets = <&tegra_car 39>;
 589                 reset-names = "fuse";
 590         };
 591
 592         mc: memory-controller@70019000 {
 593                 compatible = "nvidia,tegra132-mc";
 594                 reg = <0x0 0x70019000 0x0 0x1000>;
 595                 clocks = <&tegra_car TEGRA124_CLK_MC>;
 596                 clock-names = "mc";
 597
 598                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 599
 600                 #iommu-cells = <1>;
 601         };
 602
 603         emc: emc@7001b000 {
 604                 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
 605                 reg = <0x0 0x7001b000 0x0 0x1000>;
 606
 607                 nvidia,memory-controller = <&mc>;
 608         };
 609
 610         sata@70020000 {
 611                 compatible = "nvidia,tegra124-ahci";
 612                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 613                       <0x0 0x70020000 0x0 0x7000>; /* SATA */
 614                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 615                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 616                          <&tegra_car TEGRA124_CLK_SATA_OOB>,
 617                          <&tegra_car TEGRA124_CLK_CML1>,
 618                          <&tegra_car TEGRA124_CLK_PLL_E>;
 619                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 620                 resets = <&tegra_car 124>,
 621                          <&tegra_car 123>,
 622                          <&tegra_car 129>;
 623                 reset-names = "sata", "sata-oob", "sata-cold";
 624                 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
 625                 phy-names = "sata-phy";
 626                 status = "disabled";
 627         };
 628
 629         hda@70030000 {
 630                 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
 631                              "nvidia,tegra30-hda";
 632                 reg = <0x0 0x70030000 0x0 0x10000>;
 633                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 634                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 635                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 636                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 637                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 638                 resets = <&tegra_car 125>, /* hda */
 639                          <&tegra_car 128>, /* hda2hdmi */
 640                          <&tegra_car 111>; /* hda2codec_2x */
 641                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 642                 status = "disabled";
 643         };
 644
 645         padctl: padctl@7009f000 {
 646                 compatible = "nvidia,tegra132-xusb-padctl",
 647                              "nvidia,tegra124-xusb-padctl";
 648                 reg = <0x0 0x7009f000 0x0 0x1000>;
 649                 resets = <&tegra_car 142>;
 650                 reset-names = "padctl";
 651
 652                 #phy-cells = <1>;
 653
 654                 phys {
 655                         pcie-0 {
 656                                 status = "disabled";
 657                         };
 658
 659                         sata-0 {
 660                                 status = "disabled";
 661                         };
 662
 663                         usb3-0 {
 664                                 status = "disabled";
 665                         };
 666
 667                         usb3-1 {
 668                                 status = "disabled";
 669                         };
 670
 671                         utmi-0 {
 672                                 status = "disabled";
 673                         };
 674
 675                         utmi-1 {
 676                                 status = "disabled";
 677                         };
 678
 679                         utmi-2 {
 680                                 status = "disabled";
 681                         };
 682                 };
 683         };
 684
 685         sdhci@700b0000 {
 686                 compatible = "nvidia,tegra124-sdhci";
 687                 reg = <0x0 0x700b0000 0x0 0x200>;
 688                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 689                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 690                 clock-names = "sdhci";
 691                 resets = <&tegra_car 14>;
 692                 reset-names = "sdhci";
 693                 status = "disabled";
 694         };
 695
 696         sdhci@700b0200 {
 697                 compatible = "nvidia,tegra124-sdhci";
 698                 reg = <0x0 0x700b0200 0x0 0x200>;
 699                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 700                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 701                 clock-names = "sdhci";
 702                 resets = <&tegra_car 9>;
 703                 reset-names = "sdhci";
 704                 status = "disabled";
 705         };
 706
 707         sdhci@700b0400 {
 708                 compatible = "nvidia,tegra124-sdhci";
 709                 reg = <0x0 0x700b0400 0x0 0x200>;
 710                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 711                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 712                 clock-names = "sdhci";
 713                 resets = <&tegra_car 69>;
 714                 reset-names = "sdhci";
 715                 status = "disabled";
 716         };
 717
 718         sdhci@700b0600 {
 719                 compatible = "nvidia,tegra124-sdhci";
 720                 reg = <0x0 0x700b0600 0x0 0x200>;
 721                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 722                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 723                 clock-names = "sdhci";
 724                 resets = <&tegra_car 15>;
 725                 reset-names = "sdhci";
 726                 status = "disabled";
 727         };
 728
 729         soctherm: thermal-sensor@700e2000 {
 730                 compatible = "nvidia,tegra124-soctherm";
 731                 reg = <0x0 0x700e2000 0x0 0x1000>;
 732                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 733                 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
 734                         <&tegra_car TEGRA124_CLK_SOC_THERM>;
 735                 clock-names = "tsensor", "soctherm";
 736                 resets = <&tegra_car 78>;
 737                 reset-names = "soctherm";
 738                 #thermal-sensor-cells = <1>;
 739         };
 740
 741         ahub@70300000 {
 742                 compatible = "nvidia,tegra124-ahub";
 743                 reg = <0x0 0x70300000 0x0 0x200>,
 744                       <0x0 0x70300800 0x0 0x800>,
 745                       <0x0 0x70300200 0x0 0x600>;
 746                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 747                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 748                          <&tegra_car TEGRA124_CLK_APBIF>;
 749                 clock-names = "d_audio", "apbif";
 750                 resets = <&tegra_car 106>, /* d_audio */
 751                          <&tegra_car 107>, /* apbif */
 752                          <&tegra_car 30>,  /* i2s0 */
 753                          <&tegra_car 11>,  /* i2s1 */
 754                          <&tegra_car 18>,  /* i2s2 */
 755                          <&tegra_car 101>, /* i2s3 */
 756                          <&tegra_car 102>, /* i2s4 */
 757                          <&tegra_car 108>, /* dam0 */
 758                          <&tegra_car 109>, /* dam1 */
 759                          <&tegra_car 110>, /* dam2 */
 760                          <&tegra_car 10>,  /* spdif */
 761                          <&tegra_car 153>, /* amx */
 762                          <&tegra_car 185>, /* amx1 */
 763                          <&tegra_car 154>, /* adx */
 764                          <&tegra_car 180>, /* adx1 */
 765                          <&tegra_car 186>, /* afc0 */
 766                          <&tegra_car 187>, /* afc1 */
 767                          <&tegra_car 188>, /* afc2 */
 768                          <&tegra_car 189>, /* afc3 */
 769                          <&tegra_car 190>, /* afc4 */
 770                          <&tegra_car 191>; /* afc5 */
 771                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 772                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 773                               "spdif", "amx", "amx1", "adx", "adx1",
 774                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 775                 dmas = <&apbdma 1>, <&apbdma 1>,
 776                        <&apbdma 2>, <&apbdma 2>,
 777                        <&apbdma 3>, <&apbdma 3>,
 778                        <&apbdma 4>, <&apbdma 4>,
 779                        <&apbdma 6>, <&apbdma 6>,
 780                        <&apbdma 7>, <&apbdma 7>,
 781                        <&apbdma 12>, <&apbdma 12>,
 782                        <&apbdma 13>, <&apbdma 13>,
 783                        <&apbdma 14>, <&apbdma 14>,
 784                        <&apbdma 29>, <&apbdma 29>;
 785                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 786                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 787                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 788                             "rx9", "tx9";
 789                 ranges;
 790                 #address-cells = <2>;
 791                 #size-cells = <2>;
 792
 793                 tegra_i2s0: i2s@70301000 {
 794                         compatible = "nvidia,tegra124-i2s";
 795                         reg = <0x0 0x70301000 0x0 0x100>;
 796                         nvidia,ahub-cif-ids = <4 4>;
 797                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 798                         clock-names = "i2s";
 799                         resets = <&tegra_car 30>;
 800                         reset-names = "i2s";
 801                         status = "disabled";
 802                 };
 803
 804                 tegra_i2s1: i2s@70301100 {
 805                         compatible = "nvidia,tegra124-i2s";
 806                         reg = <0x0 0x70301100 0x0 0x100>;
 807                         nvidia,ahub-cif-ids = <5 5>;
 808                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 809                         clock-names = "i2s";
 810                         resets = <&tegra_car 11>;
 811                         reset-names = "i2s";
 812                         status = "disabled";
 813                 };
 814
 815                 tegra_i2s2: i2s@70301200 {
 816                         compatible = "nvidia,tegra124-i2s";
 817                         reg = <0x0 0x70301200 0x0 0x100>;
 818                         nvidia,ahub-cif-ids = <6 6>;
 819                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 820                         clock-names = "i2s";
 821                         resets = <&tegra_car 18>;
 822                         reset-names = "i2s";
 823                         status = "disabled";
 824                 };
 825
 826                 tegra_i2s3: i2s@70301300 {
 827                         compatible = "nvidia,tegra124-i2s";
 828                         reg = <0x0 0x70301300 0x0 0x100>;
 829                         nvidia,ahub-cif-ids = <7 7>;
 830                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 831                         clock-names = "i2s";
 832                         resets = <&tegra_car 101>;
 833                         reset-names = "i2s";
 834                         status = "disabled";
 835                 };
 836
 837                 tegra_i2s4: i2s@70301400 {
 838                         compatible = "nvidia,tegra124-i2s";
 839                         reg = <0x0 0x70301400 0x0 0x100>;
 840                         nvidia,ahub-cif-ids = <8 8>;
 841                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 842                         clock-names = "i2s";
 843                         resets = <&tegra_car 102>;
 844                         reset-names = "i2s";
 845                         status = "disabled";
 846                 };
 847         };
 848
 849         usb@7d000000 {
 850                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 851                 reg = <0x0 0x7d000000 0x0 0x4000>;
 852                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 853                 phy_type = "utmi";
 854                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
 855                 clock-names = "usb";
 856                 resets = <&tegra_car 22>;
 857                 reset-names = "usb";
 858                 nvidia,phy = <&phy1>;
 859                 status = "disabled";
 860         };
 861
 862         phy1: usb-phy@7d000000 {
 863                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 864                 reg = <0x0 0x7d000000 0x0 0x4000>,
 865                       <0x0 0x7d000000 0x0 0x4000>;
 866                 phy_type = "utmi";
 867                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
 868                          <&tegra_car TEGRA124_CLK_PLL_U>,
 869                          <&tegra_car TEGRA124_CLK_USBD>;
 870                 clock-names = "reg", "pll_u", "utmi-pads";
 871                 resets = <&tegra_car 22>, <&tegra_car 22>;
 872                 reset-names = "usb", "utmi-pads";
 873                 nvidia,hssync-start-delay = <0>;
 874                 nvidia,idle-wait-delay = <17>;
 875                 nvidia,elastic-limit = <16>;
 876                 nvidia,term-range-adj = <6>;
 877                 nvidia,xcvr-setup = <9>;
 878                 nvidia,xcvr-lsfslew = <0>;
 879                 nvidia,xcvr-lsrslew = <3>;
 880                 nvidia,hssquelch-level = <2>;
 881                 nvidia,hsdiscon-level = <5>;
 882                 nvidia,xcvr-hsslew = <12>;
 883                 nvidia,has-utmi-pad-registers;
 884                 status = "disabled";
 885         };
 886
 887         usb@7d004000 {
 888                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 889                 reg = <0x0 0x7d004000 0x0 0x4000>;
 890                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 891                 phy_type = "utmi";
 892                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
 893                 clock-names = "usb";
 894                 resets = <&tegra_car 58>;
 895                 reset-names = "usb";
 896                 nvidia,phy = <&phy2>;
 897                 status = "disabled";
 898         };
 899
 900         phy2: usb-phy@7d004000 {
 901                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 902                 reg = <0x0 0x7d004000 0x0 0x4000>,
 903                       <0x0 0x7d000000 0x0 0x4000>;
 904                 phy_type = "utmi";
 905                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
 906                          <&tegra_car TEGRA124_CLK_PLL_U>,
 907                          <&tegra_car TEGRA124_CLK_USBD>;
 908                 clock-names = "reg", "pll_u", "utmi-pads";
 909                 resets = <&tegra_car 58>, <&tegra_car 22>;
 910                 reset-names = "usb", "utmi-pads";
 911                 nvidia,hssync-start-delay = <0>;
 912                 nvidia,idle-wait-delay = <17>;
 913                 nvidia,elastic-limit = <16>;
 914                 nvidia,term-range-adj = <6>;
 915                 nvidia,xcvr-setup = <9>;
 916                 nvidia,xcvr-lsfslew = <0>;
 917                 nvidia,xcvr-lsrslew = <3>;
 918                 nvidia,hssquelch-level = <2>;
 919                 nvidia,hsdiscon-level = <5>;
 920                 nvidia,xcvr-hsslew = <12>;
 921                 status = "disabled";
 922         };
 923
 924         usb@7d008000 {
 925                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 926                 reg = <0x0 0x7d008000 0x0 0x4000>;
 927                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 928                 phy_type = "utmi";
 929                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
 930                 clock-names = "usb";
 931                 resets = <&tegra_car 59>;
 932                 reset-names = "usb";
 933                 nvidia,phy = <&phy3>;
 934                 status = "disabled";
 935         };
 936
 937         phy3: usb-phy@7d008000 {
 938                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 939                 reg = <0x0 0x7d008000 0x0 0x4000>,
 940                       <0x0 0x7d000000 0x0 0x4000>;
 941                 phy_type = "utmi";
 942                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
 943                          <&tegra_car TEGRA124_CLK_PLL_U>,
 944                          <&tegra_car TEGRA124_CLK_USBD>;
 945                 clock-names = "reg", "pll_u", "utmi-pads";
 946                 resets = <&tegra_car 59>, <&tegra_car 22>;
 947                 reset-names = "usb", "utmi-pads";
 948                 nvidia,hssync-start-delay = <0>;
 949                 nvidia,idle-wait-delay = <17>;
 950                 nvidia,elastic-limit = <16>;
 951                 nvidia,term-range-adj = <6>;
 952                 nvidia,xcvr-setup = <9>;
 953                 nvidia,xcvr-lsfslew = <0>;
 954                 nvidia,xcvr-lsrslew = <3>;
 955                 nvidia,hssquelch-level = <2>;
 956                 nvidia,hsdiscon-level = <5>;
 957                 nvidia,xcvr-hsslew = <12>;
 958                 status = "disabled";
 959         };
 960
 961         cpus {
 962                 #address-cells = <1>;
 963                 #size-cells = <0>;
 964
 965                 cpu@0 {
 966                         device_type = "cpu";
 967                         compatible = "nvidia,denver", "arm,armv8";
 968                         reg = <0>;
 969                 };
 970
 971                 cpu@1 {
 972                         device_type = "cpu";
 973                         compatible = "nvidia,denver", "arm,armv8";
 974                         reg = <1>;
 975                 };
 976         };
 977
 978         timer {
 979                 compatible = "arm,armv7-timer";
 980                 interrupts = <GIC_PPI 13
 981                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 982                              <GIC_PPI 14
 983                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 984                              <GIC_PPI 11
 985                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 986                              <GIC_PPI 10
 987                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 988                 interrupt-parent = <&gic>;
 989         };
 990 };