arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17
  18 / {
  19         model = "Qualcomm Technologies, Inc. MSM8916";
  20         compatible = "qcom,msm8916";
  21
  22         interrupt-parent = <&intc>;
  23
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         aliases {
  28                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  29                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  30         };
  31
  32         chosen { };
  33
  34         memory {
  35                 device_type = "memory";
  36                 /* We expect the bootloader to fill in the reg */
  37                 reg = <0 0 0 0>;
  38         };
  39
  40         reserved-memory {
  41                 #address-cells = <2>;
  42                 #size-cells = <2>;
  43                 ranges;
  44
  45                 tz-apps@86000000 {
  46                         reg = <0x0 0x86000000 0x0 0x300000>;
  47                         no-map;
  48                 };
  49
  50                 smem_mem: smem_region@86300000 {
  51                         reg = <0x0 0x86300000 0x0 0x100000>;
  52                         no-map;
  53                 };
  54
  55                 hypervisor@86400000 {
  56                         reg = <0x0 0x86400000 0x0 0x100000>;
  57                         no-map;
  58                 };
  59
  60                 tz@86500000 {
  61                         reg = <0x0 0x86500000 0x0 0x180000>;
  62                         no-map;
  63                 };
  64
  65                 reserved@8668000 {
  66                         reg = <0x0 0x86680000 0x0 0x80000>;
  67                         no-map;
  68                 };
  69
  70                 rmtfs@86700000 {
  71                         reg = <0x0 0x86700000 0x0 0xe0000>;
  72                         no-map;
  73                 };
  74
  75                 rfsa@867e00000 {
  76                         reg = <0x0 0x867e0000 0x0 0x20000>;
  77                         no-map;
  78                 };
  79
  80                 mpss@86800000 {
  81                         reg = <0x0 0x86800000 0x0 0x2b00000>;
  82                         no-map;
  83                 };
  84
  85                 wcnss@89300000 {
  86                         reg = <0x0 0x89300000 0x0 0x600000>;
  87                         no-map;
  88                 };
  89
  90                 mba_mem: mba@8ea00000 {
  91                         no-map;
  92                         reg = <0 0x8ea00000 0 0x100000>;
  93                 };
  94         };
  95
  96         cpus {
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99
 100                 CPU0: cpu@0 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53", "arm,armv8";
 103                         reg = <0x0>;
 104                         next-level-cache = <&L2_0>;
 105                         enable-method = "psci";
 106                         cpu-idle-states = <&CPU_SPC>;
 107                 };
 108
 109                 CPU1: cpu@1 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x1>;
 113                         next-level-cache = <&L2_0>;
 114                         enable-method = "psci";
 115                         cpu-idle-states = <&CPU_SPC>;
 116                 };
 117
 118                 CPU2: cpu@2 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a53", "arm,armv8";
 121                         reg = <0x2>;
 122                         next-level-cache = <&L2_0>;
 123                         enable-method = "psci";
 124                         cpu-idle-states = <&CPU_SPC>;
 125                 };
 126
 127                 CPU3: cpu@3 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x3>;
 131                         next-level-cache = <&L2_0>;
 132                         enable-method = "psci";
 133                         cpu-idle-states = <&CPU_SPC>;
 134                 };
 135
 136                 L2_0: l2-cache {
 137                       compatible = "cache";
 138                       cache-level = <2>;
 139                 };
 140
 141                 idle-states {
 142                         CPU_SPC: spc {
 143                                 compatible = "arm,idle-state";
 144                                 arm,psci-suspend-param = <0x40000002>;
 145                                 entry-latency-us = <130>;
 146                                 exit-latency-us = <150>;
 147                                 min-residency-us = <2000>;
 148                                 local-timer-stop;
 149                         };
 150                 };
 151         };
 152
 153         psci {
 154                 compatible = "arm,psci-1.0";
 155                 method = "smc";
 156         };
 157
 158         pmu {
 159                 compatible = "arm,armv8-pmuv3";
 160                 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
 161         };
 162
 163         timer {
 164                 compatible = "arm,armv8-timer";
 165                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 166                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 169         };
 170
 171         clocks {
 172                 xo_board: xo_board {
 173                         compatible = "fixed-clock";
 174                         #clock-cells = <0>;
 175                         clock-frequency = <19200000>;
 176                 };
 177
 178                 sleep_clk: sleep_clk {
 179                         compatible = "fixed-clock";
 180                         #clock-cells = <0>;
 181                         clock-frequency = <32768>;
 182                 };
 183         };
 184
 185         smem {
 186                 compatible = "qcom,smem";
 187
 188                 memory-region = <&smem_mem>;
 189                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 190
 191                 hwlocks = <&tcsr_mutex 3>;
 192         };
 193
 194         firmware {
 195                 scm: scm {
 196                         compatible = "qcom,scm";
 197                         clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
 198                         clock-names = "core", "bus", "iface";
 199                         #reset-cells = <1>;
 200                 };
 201         };
 202
 203         soc: soc {
 204                 #address-cells = <1>;
 205                 #size-cells = <1>;
 206                 ranges = <0 0 0 0xffffffff>;
 207                 compatible = "simple-bus";
 208
 209                 restart@4ab000 {
 210                         compatible = "qcom,pshold";
 211                         reg = <0x4ab000 0x4>;
 212                 };
 213
 214                 msmgpio: pinctrl@1000000 {
 215                         compatible = "qcom,msm8916-pinctrl";
 216                         reg = <0x1000000 0x300000>;
 217                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 218                         gpio-controller;
 219                         #gpio-cells = <2>;
 220                         interrupt-controller;
 221                         #interrupt-cells = <2>;
 222                 };
 223
 224                 gcc: clock-controller@1800000 {
 225                         compatible = "qcom,gcc-msm8916";
 226                         #clock-cells = <1>;
 227                         #reset-cells = <1>;
 228                         #power-domain-cells = <1>;
 229                         reg = <0x1800000 0x80000>;
 230                 };
 231
 232                 tcsr_mutex_regs: syscon@1905000 {
 233                         compatible = "syscon";
 234                         reg = <0x1905000 0x20000>;
 235                 };
 236
 237                 tcsr_mutex: hwlock {
 238                         compatible = "qcom,tcsr-mutex";
 239                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 240                         #hwlock-cells = <1>;
 241                 };
 242
 243                 rpm_msg_ram: memory@60000 {
 244                         compatible = "qcom,rpm-msg-ram";
 245                         reg = <0x60000 0x8000>;
 246                 };
 247
 248                 blsp1_uart1: serial@78af000 {
 249                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 250                         reg = <0x78af000 0x200>;
 251                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 252                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 253                         clock-names = "core", "iface";
 254                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 255                         dma-names = "rx", "tx";
 256                         status = "disabled";
 257                 };
 258
 259                 apcs: syscon@b011000 {
 260                         compatible = "syscon";
 261                         reg = <0x0b011000 0x1000>;
 262                 };
 263
 264                 blsp1_uart2: serial@78b0000 {
 265                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 266                         reg = <0x78b0000 0x200>;
 267                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 268                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 269                         clock-names = "core", "iface";
 270                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 271                         dma-names = "rx", "tx";
 272                         status = "disabled";
 273                 };
 274
 275                 blsp_dma: dma@7884000 {
 276                         compatible = "qcom,bam-v1.7.0";
 277                         reg = <0x07884000 0x23000>;
 278                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 280                         clock-names = "bam_clk";
 281                         #dma-cells = <1>;
 282                         qcom,ee = <0>;
 283                         status = "disabled";
 284                 };
 285
 286                 blsp_spi1: spi@78b5000 {
 287                         compatible = "qcom,spi-qup-v2.2.1";
 288                         reg = <0x078b5000 0x600>;
 289                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 290                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 291                                  <&gcc GCC_BLSP1_AHB_CLK>;
 292                         clock-names = "core", "iface";
 293                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 294                         dma-names = "rx", "tx";
 295                         pinctrl-names = "default", "sleep";
 296                         pinctrl-0 = <&spi1_default>;
 297                         pinctrl-1 = <&spi1_sleep>;
 298                         #address-cells = <1>;
 299                         #size-cells = <0>;
 300                         status = "disabled";
 301                 };
 302
 303                 blsp_spi2: spi@78b6000 {
 304                         compatible = "qcom,spi-qup-v2.2.1";
 305                         reg = <0x078b6000 0x600>;
 306                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 307                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 308                                  <&gcc GCC_BLSP1_AHB_CLK>;
 309                         clock-names = "core", "iface";
 310                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 311                         dma-names = "rx", "tx";
 312                         pinctrl-names = "default", "sleep";
 313                         pinctrl-0 = <&spi2_default>;
 314                         pinctrl-1 = <&spi2_sleep>;
 315                         #address-cells = <1>;
 316                         #size-cells = <0>;
 317                         status = "disabled";
 318                 };
 319
 320                 blsp_spi3: spi@78b7000 {
 321                         compatible = "qcom,spi-qup-v2.2.1";
 322                         reg = <0x078b7000 0x600>;
 323                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 324                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 325                                  <&gcc GCC_BLSP1_AHB_CLK>;
 326                         clock-names = "core", "iface";
 327                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 328                         dma-names = "rx", "tx";
 329                         pinctrl-names = "default", "sleep";
 330                         pinctrl-0 = <&spi3_default>;
 331                         pinctrl-1 = <&spi3_sleep>;
 332                         #address-cells = <1>;
 333                         #size-cells = <0>;
 334                         status = "disabled";
 335                 };
 336
 337                 blsp_spi4: spi@78b8000 {
 338                         compatible = "qcom,spi-qup-v2.2.1";
 339                         reg = <0x078b8000 0x600>;
 340                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 341                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 342                                  <&gcc GCC_BLSP1_AHB_CLK>;
 343                         clock-names = "core", "iface";
 344                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 345                         dma-names = "rx", "tx";
 346                         pinctrl-names = "default", "sleep";
 347                         pinctrl-0 = <&spi4_default>;
 348                         pinctrl-1 = <&spi4_sleep>;
 349                         #address-cells = <1>;
 350                         #size-cells = <0>;
 351                         status = "disabled";
 352                 };
 353
 354                 blsp_spi5: spi@78b9000 {
 355                         compatible = "qcom,spi-qup-v2.2.1";
 356                         reg = <0x078b9000 0x600>;
 357                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 358                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 359                                  <&gcc GCC_BLSP1_AHB_CLK>;
 360                         clock-names = "core", "iface";
 361                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 362                         dma-names = "rx", "tx";
 363                         pinctrl-names = "default", "sleep";
 364                         pinctrl-0 = <&spi5_default>;
 365                         pinctrl-1 = <&spi5_sleep>;
 366                         #address-cells = <1>;
 367                         #size-cells = <0>;
 368                         status = "disabled";
 369                 };
 370
 371                 blsp_spi6: spi@78ba000 {
 372                         compatible = "qcom,spi-qup-v2.2.1";
 373                         reg = <0x078ba000 0x600>;
 374                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 375                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 376                                  <&gcc GCC_BLSP1_AHB_CLK>;
 377                         clock-names = "core", "iface";
 378                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 379                         dma-names = "rx", "tx";
 380                         pinctrl-names = "default", "sleep";
 381                         pinctrl-0 = <&spi6_default>;
 382                         pinctrl-1 = <&spi6_sleep>;
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         status = "disabled";
 386                 };
 387
 388                 blsp_i2c2: i2c@78b6000 {
 389                         compatible = "qcom,i2c-qup-v2.2.1";
 390                         reg = <0x78b6000 0x1000>;
 391                         interrupts = <GIC_SPI 96 0>;
 392                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 393                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 394                         clock-names = "iface", "core";
 395                         pinctrl-names = "default", "sleep";
 396                         pinctrl-0 = <&i2c2_default>;
 397                         pinctrl-1 = <&i2c2_sleep>;
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                         status = "disabled";
 401                 };
 402
 403                 blsp_i2c4: i2c@78b8000 {
 404                         compatible = "qcom,i2c-qup-v2.2.1";
 405                         reg = <0x78b8000 0x1000>;
 406                         interrupts = <GIC_SPI 98 0>;
 407                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 408                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 409                         clock-names = "iface", "core";
 410                         pinctrl-names = "default", "sleep";
 411                         pinctrl-0 = <&i2c4_default>;
 412                         pinctrl-1 = <&i2c4_sleep>;
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         status = "disabled";
 416                 };
 417
 418                 blsp_i2c6: i2c@78ba000 {
 419                         compatible = "qcom,i2c-qup-v2.2.1";
 420                         reg = <0x78ba000 0x1000>;
 421                         interrupts = <GIC_SPI 100 0>;
 422                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 423                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 424                         clock-names = "iface", "core";
 425                         pinctrl-names = "default", "sleep";
 426                         pinctrl-0 = <&i2c6_default>;
 427                         pinctrl-1 = <&i2c6_sleep>;
 428                         #address-cells = <1>;
 429                         #size-cells = <0>;
 430                         status = "disabled";
 431                 };
 432
 433                 lpass: lpass@07708000 {
 434                         status = "disabled";
 435                         compatible = "qcom,lpass-cpu-apq8016";
 436                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 437                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
 438                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
 439                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 440                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 441                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 442                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
 443
 444                         clock-names = "ahbix-clk",
 445                                         "pcnoc-mport-clk",
 446                                         "pcnoc-sway-clk",
 447                                         "mi2s-bit-clk0",
 448                                         "mi2s-bit-clk1",
 449                                         "mi2s-bit-clk2",
 450                                         "mi2s-bit-clk3";
 451                         #sound-dai-cells = <1>;
 452
 453                         interrupts = <0 160 0>;
 454                         interrupt-names = "lpass-irq-lpaif";
 455                         reg = <0x07708000 0x10000>;
 456                         reg-names = "lpass-lpaif";
 457                 };
 458
 459                 sdhc_1: sdhci@07824000 {
 460                         compatible = "qcom,sdhci-msm-v4";
 461                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 462                         reg-names = "hc_mem", "core_mem";
 463
 464                         interrupts = <0 123 0>, <0 138 0>;
 465                         interrupt-names = "hc_irq", "pwr_irq";
 466                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 467                                  <&gcc GCC_SDCC1_AHB_CLK>;
 468                         clock-names = "core", "iface";
 469                         bus-width = <8>;
 470                         non-removable;
 471                         status = "disabled";
 472                 };
 473
 474                 sdhc_2: sdhci@07864000 {
 475                         compatible = "qcom,sdhci-msm-v4";
 476                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 477                         reg-names = "hc_mem", "core_mem";
 478
 479                         interrupts = <0 125 0>, <0 221 0>;
 480                         interrupt-names = "hc_irq", "pwr_irq";
 481                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 482                                  <&gcc GCC_SDCC2_AHB_CLK>;
 483                         clock-names = "core", "iface";
 484                         bus-width = <4>;
 485                         status = "disabled";
 486                 };
 487
 488                 usb_dev: usb@78d9000 {
 489                         compatible = "qcom,ci-hdrc";
 490                         reg = <0x78d9000 0x400>;
 491                         dr_mode = "peripheral";
 492                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 493                         usb-phy = <&usb_otg>;
 494                         status = "disabled";
 495                 };
 496
 497                 usb_host: ehci@78d9000 {
 498                         compatible = "qcom,ehci-host";
 499                         reg = <0x78d9000 0x400>;
 500                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 501                         usb-phy = <&usb_otg>;
 502                         status = "disabled";
 503                 };
 504
 505                 usb_otg: phy@78d9000 {
 506                         compatible = "qcom,usb-otg-snps";
 507                         reg = <0x78d9000 0x400>;
 508                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
 509                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 510
 511                         qcom,vdd-levels = <500000 1000000 1320000>;
 512                         qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 513                         dr_mode = "peripheral";
 514                         qcom,otg-control = <2>; // PMIC
 515                         qcom,manual-pullup;
 516
 517                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 518                                  <&gcc GCC_USB_HS_SYSTEM_CLK>,
 519                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 520                         clock-names = "iface", "core", "sleep";
 521
 522                         resets = <&gcc GCC_USB2A_PHY_BCR>,
 523                                  <&gcc GCC_USB_HS_BCR>;
 524                         reset-names = "phy", "link";
 525                         status = "disabled";
 526                 };
 527
 528                 intc: interrupt-controller@b000000 {
 529                         compatible = "qcom,msm-qgic2";
 530                         interrupt-controller;
 531                         #interrupt-cells = <3>;
 532                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 533                 };
 534
 535                 timer@b020000 {
 536                         #address-cells = <1>;
 537                         #size-cells = <1>;
 538                         ranges;
 539                         compatible = "arm,armv7-timer-mem";
 540                         reg = <0xb020000 0x1000>;
 541                         clock-frequency = <19200000>;
 542
 543                         frame@b021000 {
 544                                 frame-number = <0>;
 545                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 546                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 547                                 reg = <0xb021000 0x1000>,
 548                                       <0xb022000 0x1000>;
 549                         };
 550
 551                         frame@b023000 {
 552                                 frame-number = <1>;
 553                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 554                                 reg = <0xb023000 0x1000>;
 555                                 status = "disabled";
 556                         };
 557
 558                         frame@b024000 {
 559                                 frame-number = <2>;
 560                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 561                                 reg = <0xb024000 0x1000>;
 562                                 status = "disabled";
 563                         };
 564
 565                         frame@b025000 {
 566                                 frame-number = <3>;
 567                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 568                                 reg = <0xb025000 0x1000>;
 569                                 status = "disabled";
 570                         };
 571
 572                         frame@b026000 {
 573                                 frame-number = <4>;
 574                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 575                                 reg = <0xb026000 0x1000>;
 576                                 status = "disabled";
 577                         };
 578
 579                         frame@b027000 {
 580                                 frame-number = <5>;
 581                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 582                                 reg = <0xb027000 0x1000>;
 583                                 status = "disabled";
 584                         };
 585
 586                         frame@b028000 {
 587                                 frame-number = <6>;
 588                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 589                                 reg = <0xb028000 0x1000>;
 590                                 status = "disabled";
 591                         };
 592                 };
 593
 594                 spmi_bus: spmi@200f000 {
 595                         compatible = "qcom,spmi-pmic-arb";
 596                         reg = <0x200f000 0x001000>,
 597                               <0x2400000 0x400000>,
 598                               <0x2c00000 0x400000>,
 599                               <0x3800000 0x200000>,
 600                               <0x200a000 0x002100>;
 601                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 602                         interrupt-names = "periph_irq";
 603                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 604                         qcom,ee = <0>;
 605                         qcom,channel = <0>;
 606                         #address-cells = <2>;
 607                         #size-cells = <0>;
 608                         interrupt-controller;
 609                         #interrupt-cells = <4>;
 610                 };
 611
 612                 rng@22000 {
 613                         compatible = "qcom,prng";
 614                         reg = <0x00022000 0x200>;
 615                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 616                         clock-names = "core";
 617                 };
 618         };
 619
 620         smd {
 621                 compatible = "qcom,smd";
 622
 623                 rpm {
 624                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 625                         qcom,ipc = <&apcs 8 0>;
 626                         qcom,smd-edge = <15>;
 627
 628                         rpm_requests {
 629                                 compatible = "qcom,rpm-msm8916";
 630                                 qcom,smd-channels = "rpm_requests";
 631
 632                                 rpmcc: qcom,rpmcc {
 633                                         compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
 634                                         #clock-cells = <1>;
 635                                 };
 636
 637                                 smd_rpm_regulators: pm8916-regulators {
 638                                         compatible = "qcom,rpm-pm8916-regulators";
 639
 640                                         pm8916_s1: s1 {};
 641                                         pm8916_s3: s3 {};
 642                                         pm8916_s4: s4 {};
 643
 644                                         pm8916_l1: l1 {};
 645                                         pm8916_l2: l2 {};
 646                                         pm8916_l3: l3 {};
 647                                         pm8916_l4: l4 {};
 648                                         pm8916_l5: l5 {};
 649                                         pm8916_l6: l6 {};
 650                                         pm8916_l7: l7 {};
 651                                         pm8916_l8: l8 {};
 652                                         pm8916_l9: l9 {};
 653                                         pm8916_l10: l10 {};
 654                                         pm8916_l11: l11 {};
 655                                         pm8916_l12: l12 {};
 656                                         pm8916_l13: l13 {};
 657                                         pm8916_l14: l14 {};
 658                                         pm8916_l15: l15 {};
 659                                         pm8916_l16: l16 {};
 660                                         pm8916_l17: l17 {};
 661                                         pm8916_l18: l18 {};
 662                                 };
 663                         };
 664                 };
 665         };
 666
 667         hexagon-smp2p {
 668                 compatible = "qcom,smp2p";
 669                 qcom,smem = <435>, <428>;
 670
 671                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
 672
 673                 qcom,ipc = <&apcs 8 14>;
 674
 675                 qcom,local-pid = <0>;
 676                 qcom,remote-pid = <1>;
 677
 678                 hexagon_smp2p_out: master-kernel {
 679                         qcom,entry-name = "master-kernel";
 680
 681                         #qcom,smem-state-cells = <1>;
 682                 };
 683
 684                 hexagon_smp2p_in: slave-kernel {
 685                         qcom,entry-name = "slave-kernel";
 686
 687                         interrupt-controller;
 688                         #interrupt-cells = <2>;
 689                 };
 690         };
 691
 692         wcnss-smp2p {
 693                 compatible = "qcom,smp2p";
 694                 qcom,smem = <451>, <431>;
 695
 696                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
 697
 698                 qcom,ipc = <&apcs 8 18>;
 699
 700                 qcom,local-pid = <0>;
 701                 qcom,remote-pid = <4>;
 702
 703                 wcnss_smp2p_out: master-kernel {
 704                         qcom,entry-name = "master-kernel";
 705
 706                         #qcom,smem-state-cells = <1>;
 707                 };
 708
 709                 wcnss_smp2p_in: slave-kernel {
 710                         qcom,entry-name = "slave-kernel";
 711
 712                         interrupt-controller;
 713                         #interrupt-cells = <2>;
 714                 };
 715         };
 716
 717         smsm {
 718                 compatible = "qcom,smsm";
 719
 720                 #address-cells = <1>;
 721                 #size-cells = <0>;
 722
 723                 qcom,ipc-1 = <&apcs 0 13>;
 724                 qcom,ipc-6 = <&apcs 0 19>;
 725
 726                 apps_smsm: apps@0 {
 727                         reg = <0>;
 728
 729                         #qcom,smem-state-cells = <1>;
 730                 };
 731
 732                 hexagon_smsm: hexagon@1 {
 733                         reg = <1>;
 734                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
 735
 736                         interrupt-controller;
 737                         #interrupt-cells = <2>;
 738                 };
 739
 740                 wcnss_smsm: wcnss@6 {
 741                         reg = <6>;
 742                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
 743
 744                         interrupt-controller;
 745                         #interrupt-cells = <2>;
 746                 };
 747         };
 748 };
 749
 750 #include "msm8916-pins.dtsi"