arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  15 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
  16
  17 / {
  18         model = "Qualcomm Technologies, Inc. MSM8996";
  19
  20         interrupt-parent = <&intc>;
  21
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         chosen { };
  26
  27         memory {
  28                 device_type = "memory";
  29                 /* We expect the bootloader to fill in the reg */
  30                 reg = <0 0 0 0>;
  31         };
  32
  33         cpus {
  34                 #address-cells = <2>;
  35                 #size-cells = <0>;
  36
  37                 CPU0: cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "qcom,kryo";
  40                         reg = <0x0 0x0>;
  41                         enable-method = "psci";
  42                         next-level-cache = <&L2_0>;
  43                         L2_0: l2-cache {
  44                               compatible = "cache";
  45                               cache-level = <2>;
  46                         };
  47                 };
  48
  49                 CPU1: cpu@1 {
  50                         device_type = "cpu";
  51                         compatible = "qcom,kryo";
  52                         reg = <0x0 0x1>;
  53                         enable-method = "psci";
  54                         next-level-cache = <&L2_0>;
  55                 };
  56
  57                 CPU2: cpu@100 {
  58                         device_type = "cpu";
  59                         compatible = "qcom,kryo";
  60                         reg = <0x0 0x100>;
  61                         enable-method = "psci";
  62                         next-level-cache = <&L2_1>;
  63                         L2_1: l2-cache {
  64                               compatible = "cache";
  65                               cache-level = <2>;
  66                         };
  67                 };
  68
  69                 CPU3: cpu@101 {
  70                         device_type = "cpu";
  71                         compatible = "qcom,kryo";
  72                         reg = <0x0 0x101>;
  73                         enable-method = "psci";
  74                         next-level-cache = <&L2_1>;
  75                 };
  76
  77                 cpu-map {
  78                         cluster0 {
  79                                 core0 {
  80                                         cpu = <&CPU0>;
  81                                 };
  82
  83                                 core1 {
  84                                         cpu = <&CPU1>;
  85                                 };
  86                         };
  87
  88                         cluster1 {
  89                                 core0 {
  90                                         cpu = <&CPU2>;
  91                                 };
  92
  93                                 core1 {
  94                                         cpu = <&CPU3>;
  95                                 };
  96                         };
  97                 };
  98         };
  99
 100         timer {
 101                 compatible = "arm,armv8-timer";
 102                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 103                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 104                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 105                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 106         };
 107
 108         clocks {
 109                 xo_board {
 110                         compatible = "fixed-clock";
 111                         #clock-cells = <0>;
 112                         clock-frequency = <19200000>;
 113                         clock-output-names = "xo_board";
 114                 };
 115
 116                 sleep_clk {
 117                         compatible = "fixed-clock";
 118                         #clock-cells = <0>;
 119                         clock-frequency = <32764>;
 120                         clock-output-names = "sleep_clk";
 121                 };
 122         };
 123
 124         psci {
 125                 compatible = "arm,psci-1.0";
 126                 method = "smc";
 127         };
 128
 129         soc: soc {
 130                 #address-cells = <1>;
 131                 #size-cells = <1>;
 132                 ranges = <0 0 0 0xffffffff>;
 133                 compatible = "simple-bus";
 134
 135                 intc: interrupt-controller@9bc0000 {
 136                         compatible = "arm,gic-v3";
 137                         #interrupt-cells = <3>;
 138                         interrupt-controller;
 139                         #redistributor-regions = <1>;
 140                         redistributor-stride = <0x0 0x40000>;
 141                         reg = <0x09bc0000 0x10000>,
 142                               <0x09c00000 0x100000>;
 143                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 144                 };
 145
 146                 gcc: clock-controller@300000 {
 147                         compatible = "qcom,gcc-msm8996";
 148                         #clock-cells = <1>;
 149                         #reset-cells = <1>;
 150                         #power-domain-cells = <1>;
 151                         reg = <0x300000 0x90000>;
 152                 };
 153
 154                 blsp2_uart1: serial@75b0000 {
 155                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 156                         reg = <0x75b0000 0x1000>;
 157                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 158                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 159                                  <&gcc GCC_BLSP2_AHB_CLK>;
 160                         clock-names = "core", "iface";
 161                         status = "disabled";
 162                 };
 163
 164                 pinctrl@1010000 {
 165                         compatible = "qcom,msm8996-pinctrl";
 166                         reg = <0x01010000 0x300000>;
 167                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 168                         gpio-controller;
 169                         #gpio-cells = <2>;
 170                         interrupt-controller;
 171                         #interrupt-cells = <2>;
 172                 };
 173
 174                 timer@09840000 {
 175                         #address-cells = <1>;
 176                         #size-cells = <1>;
 177                         ranges;
 178                         compatible = "arm,armv7-timer-mem";
 179                         reg = <0x09840000 0x1000>;
 180                         clock-frequency = <19200000>;
 181
 182                         frame@9850000 {
 183                                 frame-number = <0>;
 184                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 185                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 186                                 reg = <0x09850000 0x1000>,
 187                                       <0x09860000 0x1000>;
 188                         };
 189
 190                         frame@9870000 {
 191                                 frame-number = <1>;
 192                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 193                                 reg = <0x09870000 0x1000>;
 194                                 status = "disabled";
 195                         };
 196
 197                         frame@9880000 {
 198                                 frame-number = <2>;
 199                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 200                                 reg = <0x09880000 0x1000>;
 201                                 status = "disabled";
 202                         };
 203
 204                         frame@9890000 {
 205                                 frame-number = <3>;
 206                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 207                                 reg = <0x09890000 0x1000>;
 208                                 status = "disabled";
 209                         };
 210
 211                         frame@98a0000 {
 212                                 frame-number = <4>;
 213                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 214                                 reg = <0x098a0000 0x1000>;
 215                                 status = "disabled";
 216                         };
 217
 218                         frame@98b0000 {
 219                                 frame-number = <5>;
 220                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 221                                 reg = <0x098b0000 0x1000>;
 222                                 status = "disabled";
 223                         };
 224
 225                         frame@98c0000 {
 226                                 frame-number = <6>;
 227                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 228                                 reg = <0x098c0000 0x1000>;
 229                                 status = "disabled";
 230                         };
 231                 };
 232
 233                 spmi_bus: qcom,spmi@400f000 {
 234                         compatible = "qcom,spmi-pmic-arb";
 235                         reg = <0x400f000 0x1000>,
 236                               <0x4400000 0x800000>,
 237                               <0x4c00000 0x800000>,
 238                               <0x5800000 0x200000>,
 239                               <0x400a000 0x002100>;
 240                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 241                         interrupt-names = "periph_irq";
 242                         interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
 243                         qcom,ee = <0>;
 244                         qcom,channel = <0>;
 245                         #address-cells = <2>;
 246                         #size-cells = <0>;
 247                         interrupt-controller;
 248                         #interrupt-cells = <4>;
 249                 };
 250
 251                 mmcc: clock-controller@8c0000 {
 252                         compatible = "qcom,mmcc-msm8996";
 253                         #clock-cells = <1>;
 254                         #reset-cells = <1>;
 255                         #power-domain-cells = <1>;
 256                         reg = <0x8c0000 0x40000>;
 257                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 258                                           <&mmcc MMPLL1_PLL>,
 259                                           <&mmcc MMPLL3_PLL>,
 260                                           <&mmcc MMPLL4_PLL>,
 261                                           <&mmcc MMPLL5_PLL>;
 262                         assigned-clock-rates = <624000000>,
 263                                                <810000000>,
 264                                                <980000000>,
 265                                                <960000000>,
 266                                                <825000000>;
 267                 };
 268         };
 269 };