2 * Device Tree Source for the r8a7796 SoC
4 * Copyright (C) 2016 Renesas Electronics Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/r8a7796-sysc.h>
16 compatible = "renesas,r8a7796";
21 compatible = "arm,psci-0.2";
29 /* 1 core only at this point */
31 compatible = "arm,cortex-a57", "arm,armv8";
34 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
35 next-level-cache = <&L2_CA57>;
36 enable-method = "psci";
39 L2_CA57: cache-controller@0 {
42 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
49 compatible = "fixed-clock";
51 /* This value must be overridden by the board */
52 clock-frequency = <0>;
56 compatible = "fixed-clock";
58 /* This value must be overridden by the board */
59 clock-frequency = <0>;
62 /* External SCIF clock - to be overridden by boards that provide it */
64 compatible = "fixed-clock";
66 clock-frequency = <0>;
70 compatible = "simple-bus";
71 interrupt-parent = <&gic>;
76 gic: interrupt-controller@f1010000 {
77 compatible = "arm,gic-400";
78 #interrupt-cells = <3>;
81 reg = <0x0 0xf1010000 0 0x1000>,
82 <0x0 0xf1020000 0 0x20000>,
83 <0x0 0xf1040000 0 0x20000>,
84 <0x0 0xf1060000 0 0x20000>;
85 interrupts = <GIC_PPI 9
86 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
90 compatible = "arm,armv8-timer";
91 interrupts = <GIC_PPI 13
92 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
94 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
96 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
98 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
101 wdt0: watchdog@e6020000 {
102 compatible = "renesas,r8a7796-wdt",
103 "renesas,rcar-gen3-wdt";
104 reg = <0 0xe6020000 0 0x0c>;
105 clocks = <&cpg CPG_MOD 402>;
106 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
110 gpio0: gpio@e6050000 {
111 compatible = "renesas,gpio-r8a7796",
113 reg = <0 0xe6050000 0 0x50>;
114 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
117 gpio-ranges = <&pfc 0 0 16>;
118 #interrupt-cells = <2>;
119 interrupt-controller;
120 clocks = <&cpg CPG_MOD 912>;
121 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
124 gpio1: gpio@e6051000 {
125 compatible = "renesas,gpio-r8a7796",
127 reg = <0 0xe6051000 0 0x50>;
128 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
131 gpio-ranges = <&pfc 0 32 29>;
132 #interrupt-cells = <2>;
133 interrupt-controller;
134 clocks = <&cpg CPG_MOD 911>;
135 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
138 gpio2: gpio@e6052000 {
139 compatible = "renesas,gpio-r8a7796",
141 reg = <0 0xe6052000 0 0x50>;
142 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
145 gpio-ranges = <&pfc 0 64 15>;
146 #interrupt-cells = <2>;
147 interrupt-controller;
148 clocks = <&cpg CPG_MOD 910>;
149 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
152 gpio3: gpio@e6053000 {
153 compatible = "renesas,gpio-r8a7796",
155 reg = <0 0xe6053000 0 0x50>;
156 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
159 gpio-ranges = <&pfc 0 96 16>;
160 #interrupt-cells = <2>;
161 interrupt-controller;
162 clocks = <&cpg CPG_MOD 909>;
163 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
166 gpio4: gpio@e6054000 {
167 compatible = "renesas,gpio-r8a7796",
169 reg = <0 0xe6054000 0 0x50>;
170 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
173 gpio-ranges = <&pfc 0 128 18>;
174 #interrupt-cells = <2>;
175 interrupt-controller;
176 clocks = <&cpg CPG_MOD 908>;
177 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
180 gpio5: gpio@e6055000 {
181 compatible = "renesas,gpio-r8a7796",
183 reg = <0 0xe6055000 0 0x50>;
184 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
187 gpio-ranges = <&pfc 0 160 26>;
188 #interrupt-cells = <2>;
189 interrupt-controller;
190 clocks = <&cpg CPG_MOD 907>;
191 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
194 gpio6: gpio@e6055400 {
195 compatible = "renesas,gpio-r8a7796",
197 reg = <0 0xe6055400 0 0x50>;
198 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
201 gpio-ranges = <&pfc 0 192 32>;
202 #interrupt-cells = <2>;
203 interrupt-controller;
204 clocks = <&cpg CPG_MOD 906>;
205 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
208 gpio7: gpio@e6055800 {
209 compatible = "renesas,gpio-r8a7796",
211 reg = <0 0xe6055800 0 0x50>;
212 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
215 gpio-ranges = <&pfc 0 224 4>;
216 #interrupt-cells = <2>;
217 interrupt-controller;
218 clocks = <&cpg CPG_MOD 905>;
219 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
222 pfc: pin-controller@e6060000 {
223 compatible = "renesas,pfc-r8a7796";
224 reg = <0 0xe6060000 0 0x50c>;
227 cpg: clock-controller@e6150000 {
228 compatible = "renesas,r8a7796-cpg-mssr";
229 reg = <0 0xe6150000 0 0x1000>;
230 clocks = <&extal_clk>, <&extalr_clk>;
231 clock-names = "extal", "extalr";
233 #power-domain-cells = <0>;
236 sysc: system-controller@e6180000 {
237 compatible = "renesas,r8a7796-sysc";
238 reg = <0 0xe6180000 0 0x0400>;
239 #power-domain-cells = <1>;
242 scif2: serial@e6e88000 {
243 compatible = "renesas,scif-r8a7796",
244 "renesas,rcar-gen3-scif", "renesas,scif";
245 reg = <0 0xe6e88000 0 64>;
246 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&cpg CPG_MOD 310>,
248 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
250 clock-names = "fck", "brg_int", "scif_clk";
251 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;