2 * Device Tree Source for the r8a7796 SoC
4 * Copyright (C) 2016 Renesas Electronics Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/r8a7796-sysc.h>
16 compatible = "renesas,r8a7796";
21 compatible = "arm,psci-0.2";
29 /* 1 core only at this point */
31 compatible = "arm,cortex-a57", "arm,armv8";
34 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
35 next-level-cache = <&L2_CA57>;
36 enable-method = "psci";
39 L2_CA57: cache-controller@0 {
42 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
49 compatible = "fixed-clock";
51 /* This value must be overridden by the board */
52 clock-frequency = <0>;
56 compatible = "fixed-clock";
58 /* This value must be overridden by the board */
59 clock-frequency = <0>;
62 /* External SCIF clock - to be overridden by boards that provide it */
64 compatible = "fixed-clock";
66 clock-frequency = <0>;
70 compatible = "simple-bus";
71 interrupt-parent = <&gic>;
76 gic: interrupt-controller@f1010000 {
77 compatible = "arm,gic-400";
78 #interrupt-cells = <3>;
81 reg = <0x0 0xf1010000 0 0x1000>,
82 <0x0 0xf1020000 0 0x20000>,
83 <0x0 0xf1040000 0 0x20000>,
84 <0x0 0xf1060000 0 0x20000>;
85 interrupts = <GIC_PPI 9
86 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
90 compatible = "arm,armv8-timer";
91 interrupts = <GIC_PPI 13
92 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
94 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
96 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
98 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
101 wdt0: watchdog@e6020000 {
102 compatible = "renesas,r8a7796-wdt",
103 "renesas,rcar-gen3-wdt";
104 reg = <0 0xe6020000 0 0x0c>;
105 clocks = <&cpg CPG_MOD 402>;
106 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
110 cpg: clock-controller@e6150000 {
111 compatible = "renesas,r8a7796-cpg-mssr";
112 reg = <0 0xe6150000 0 0x1000>;
113 clocks = <&extal_clk>, <&extalr_clk>;
114 clock-names = "extal", "extalr";
116 #power-domain-cells = <0>;
119 sysc: system-controller@e6180000 {
120 compatible = "renesas,r8a7796-sysc";
121 reg = <0 0xe6180000 0 0x0400>;
122 #power-domain-cells = <1>;
125 scif2: serial@e6e88000 {
126 compatible = "renesas,scif-r8a7796",
127 "renesas,rcar-gen3-scif", "renesas,scif";
128 reg = <0 0xe6e88000 0 64>;
129 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&cpg CPG_MOD 310>,
131 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
133 clock-names = "fck", "brg_int", "scif_clk";
134 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;