arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 i2c6 = &i2c6;
  66                 i2c7 = &i2c7;
  67                 i2c8 = &i2c8;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73         };
  74
  75         cpus {
  76                 #address-cells = <2>;
  77                 #size-cells = <0>;
  78
  79                 cpu-map {
  80                         cluster0 {
  81                                 core0 {
  82                                         cpu = <&cpu_l0>;
  83                                 };
  84                                 core1 {
  85                                         cpu = <&cpu_l1>;
  86                                 };
  87                                 core2 {
  88                                         cpu = <&cpu_l2>;
  89                                 };
  90                                 core3 {
  91                                         cpu = <&cpu_l3>;
  92                                 };
  93                         };
  94
  95                         cluster1 {
  96                                 core0 {
  97                                         cpu = <&cpu_b0>;
  98                                 };
  99                                 core1 {
 100                                         cpu = <&cpu_b1>;
 101                                 };
 102                         };
 103                 };
 104
 105                 cpu_l0: cpu@0 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53", "arm,armv8";
 108                         reg = <0x0 0x0>;
 109                         enable-method = "psci";
 110                         #cooling-cells = <2>; /* min followed by max */
 111                         clocks = <&cru ARMCLKL>;
 112                 };
 113
 114                 cpu_l1: cpu@1 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a53", "arm,armv8";
 117                         reg = <0x0 0x1>;
 118                         enable-method = "psci";
 119                         clocks = <&cru ARMCLKL>;
 120                 };
 121
 122                 cpu_l2: cpu@2 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53", "arm,armv8";
 125                         reg = <0x0 0x2>;
 126                         enable-method = "psci";
 127                         clocks = <&cru ARMCLKL>;
 128                 };
 129
 130                 cpu_l3: cpu@3 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a53", "arm,armv8";
 133                         reg = <0x0 0x3>;
 134                         enable-method = "psci";
 135                         clocks = <&cru ARMCLKL>;
 136                 };
 137
 138                 cpu_b0: cpu@100 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a72", "arm,armv8";
 141                         reg = <0x0 0x100>;
 142                         enable-method = "psci";
 143                         #cooling-cells = <2>; /* min followed by max */
 144                         clocks = <&cru ARMCLKB>;
 145                 };
 146
 147                 cpu_b1: cpu@101 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72", "arm,armv8";
 150                         reg = <0x0 0x101>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKB>;
 153                 };
 154         };
 155
 156         psci {
 157                 compatible = "arm,psci-1.0";
 158                 method = "smc";
 159         };
 160
 161         timer {
 162                 compatible = "arm,armv8-timer";
 163                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 164                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 165                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 166                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 167         };
 168
 169         xin24m: xin24m {
 170                 compatible = "fixed-clock";
 171                 clock-frequency = <24000000>;
 172                 clock-output-names = "xin24m";
 173                 #clock-cells = <0>;
 174         };
 175
 176         amba {
 177                 compatible = "simple-bus";
 178                 #address-cells = <2>;
 179                 #size-cells = <2>;
 180                 ranges;
 181
 182                 dmac_bus: dma-controller@ff6d0000 {
 183                         compatible = "arm,pl330", "arm,primecell";
 184                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 185                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 187                         #dma-cells = <1>;
 188                         clocks = <&cru ACLK_DMAC0_PERILP>;
 189                         clock-names = "apb_pclk";
 190                 };
 191
 192                 dmac_peri: dma-controller@ff6e0000 {
 193                         compatible = "arm,pl330", "arm,primecell";
 194                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 195                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 197                         #dma-cells = <1>;
 198                         clocks = <&cru ACLK_DMAC1_PERILP>;
 199                         clock-names = "apb_pclk";
 200                 };
 201         };
 202
 203         sdio0: dwmmc@fe310000 {
 204                 compatible = "rockchip,rk3399-dw-mshc",
 205                              "rockchip,rk3288-dw-mshc";
 206                 reg = <0x0 0xfe310000 0x0 0x4000>;
 207                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 208                 clock-freq-min-max = <400000 150000000>;
 209                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 210                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 211                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 212                 fifo-depth = <0x100>;
 213                 status = "disabled";
 214         };
 215
 216         sdmmc: dwmmc@fe320000 {
 217                 compatible = "rockchip,rk3399-dw-mshc",
 218                              "rockchip,rk3288-dw-mshc";
 219                 reg = <0x0 0xfe320000 0x0 0x4000>;
 220                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 221                 clock-freq-min-max = <400000 150000000>;
 222                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 223                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 224                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 225                 fifo-depth = <0x100>;
 226                 status = "disabled";
 227         };
 228
 229         sdhci: sdhci@fe330000 {
 230                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 231                 reg = <0x0 0xfe330000 0x0 0x10000>;
 232                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 233                 arasan,soc-ctl-syscon = <&grf>;
 234                 assigned-clocks = <&cru SCLK_EMMC>;
 235                 assigned-clock-rates = <200000000>;
 236                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 237                 clock-names = "clk_xin", "clk_ahb";
 238                 clock-output-names = "emmc_cardclock";
 239                 #clock-cells = <0>;
 240                 phys = <&emmc_phy>;
 241                 phy-names = "phy_arasan";
 242                 status = "disabled";
 243         };
 244
 245         usb_host0_ehci: usb@fe380000 {
 246                 compatible = "generic-ehci";
 247                 reg = <0x0 0xfe380000 0x0 0x20000>;
 248                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 249                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 250                 clock-names = "hclk_host0", "hclk_host0_arb";
 251                 phys = <&u2phy0_host>;
 252                 phy-names = "usb";
 253                 status = "disabled";
 254         };
 255
 256         usb_host0_ohci: usb@fe3a0000 {
 257                 compatible = "generic-ohci";
 258                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 259                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 260                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 261                 clock-names = "hclk_host0", "hclk_host0_arb";
 262                 status = "disabled";
 263         };
 264
 265         usb_host1_ehci: usb@fe3c0000 {
 266                 compatible = "generic-ehci";
 267                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 268                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 270                 clock-names = "hclk_host1", "hclk_host1_arb";
 271                 phys = <&u2phy1_host>;
 272                 phy-names = "usb";
 273                 status = "disabled";
 274         };
 275
 276         usb_host1_ohci: usb@fe3e0000 {
 277                 compatible = "generic-ohci";
 278                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 279                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 280                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 281                 clock-names = "hclk_host1", "hclk_host1_arb";
 282                 status = "disabled";
 283         };
 284
 285         gic: interrupt-controller@fee00000 {
 286                 compatible = "arm,gic-v3";
 287                 #interrupt-cells = <3>;
 288                 #address-cells = <2>;
 289                 #size-cells = <2>;
 290                 ranges;
 291                 interrupt-controller;
 292
 293                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 294                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 295                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 296                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 297                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 298                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 299                 its: interrupt-controller@fee20000 {
 300                         compatible = "arm,gic-v3-its";
 301                         msi-controller;
 302                         reg = <0x0 0xfee20000 0x0 0x20000>;
 303                 };
 304         };
 305
 306         i2c1: i2c@ff110000 {
 307                 compatible = "rockchip,rk3399-i2c";
 308                 reg = <0x0 0xff110000 0x0 0x1000>;
 309                 assigned-clocks = <&cru SCLK_I2C1>;
 310                 assigned-clock-rates = <200000000>;
 311                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 312                 clock-names = "i2c", "pclk";
 313                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 314                 pinctrl-names = "default";
 315                 pinctrl-0 = <&i2c1_xfer>;
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 status = "disabled";
 319         };
 320
 321         i2c2: i2c@ff120000 {
 322                 compatible = "rockchip,rk3399-i2c";
 323                 reg = <0x0 0xff120000 0x0 0x1000>;
 324                 assigned-clocks = <&cru SCLK_I2C2>;
 325                 assigned-clock-rates = <200000000>;
 326                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 327                 clock-names = "i2c", "pclk";
 328                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&i2c2_xfer>;
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 status = "disabled";
 334         };
 335
 336         i2c3: i2c@ff130000 {
 337                 compatible = "rockchip,rk3399-i2c";
 338                 reg = <0x0 0xff130000 0x0 0x1000>;
 339                 assigned-clocks = <&cru SCLK_I2C3>;
 340                 assigned-clock-rates = <200000000>;
 341                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 342                 clock-names = "i2c", "pclk";
 343                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&i2c3_xfer>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 status = "disabled";
 349         };
 350
 351         i2c5: i2c@ff140000 {
 352                 compatible = "rockchip,rk3399-i2c";
 353                 reg = <0x0 0xff140000 0x0 0x1000>;
 354                 assigned-clocks = <&cru SCLK_I2C5>;
 355                 assigned-clock-rates = <200000000>;
 356                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 357                 clock-names = "i2c", "pclk";
 358                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 359                 pinctrl-names = "default";
 360                 pinctrl-0 = <&i2c5_xfer>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363                 status = "disabled";
 364         };
 365
 366         i2c6: i2c@ff150000 {
 367                 compatible = "rockchip,rk3399-i2c";
 368                 reg = <0x0 0xff150000 0x0 0x1000>;
 369                 assigned-clocks = <&cru SCLK_I2C6>;
 370                 assigned-clock-rates = <200000000>;
 371                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 372                 clock-names = "i2c", "pclk";
 373                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 374                 pinctrl-names = "default";
 375                 pinctrl-0 = <&i2c6_xfer>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 status = "disabled";
 379         };
 380
 381         i2c7: i2c@ff160000 {
 382                 compatible = "rockchip,rk3399-i2c";
 383                 reg = <0x0 0xff160000 0x0 0x1000>;
 384                 assigned-clocks = <&cru SCLK_I2C7>;
 385                 assigned-clock-rates = <200000000>;
 386                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 387                 clock-names = "i2c", "pclk";
 388                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 389                 pinctrl-names = "default";
 390                 pinctrl-0 = <&i2c7_xfer>;
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 status = "disabled";
 394         };
 395
 396         uart0: serial@ff180000 {
 397                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 398                 reg = <0x0 0xff180000 0x0 0x100>;
 399                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 400                 clock-names = "baudclk", "apb_pclk";
 401                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 402                 reg-shift = <2>;
 403                 reg-io-width = <4>;
 404                 pinctrl-names = "default";
 405                 pinctrl-0 = <&uart0_xfer>;
 406                 status = "disabled";
 407         };
 408
 409         uart1: serial@ff190000 {
 410                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 411                 reg = <0x0 0xff190000 0x0 0x100>;
 412                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 413                 clock-names = "baudclk", "apb_pclk";
 414                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 415                 reg-shift = <2>;
 416                 reg-io-width = <4>;
 417                 pinctrl-names = "default";
 418                 pinctrl-0 = <&uart1_xfer>;
 419                 status = "disabled";
 420         };
 421
 422         uart2: serial@ff1a0000 {
 423                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 424                 reg = <0x0 0xff1a0000 0x0 0x100>;
 425                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 426                 clock-names = "baudclk", "apb_pclk";
 427                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 428                 reg-shift = <2>;
 429                 reg-io-width = <4>;
 430                 pinctrl-names = "default";
 431                 pinctrl-0 = <&uart2c_xfer>;
 432                 status = "disabled";
 433         };
 434
 435         uart3: serial@ff1b0000 {
 436                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 437                 reg = <0x0 0xff1b0000 0x0 0x100>;
 438                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 439                 clock-names = "baudclk", "apb_pclk";
 440                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 441                 reg-shift = <2>;
 442                 reg-io-width = <4>;
 443                 pinctrl-names = "default";
 444                 pinctrl-0 = <&uart3_xfer>;
 445                 status = "disabled";
 446         };
 447
 448         spi0: spi@ff1c0000 {
 449                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 450                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 451                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 452                 clock-names = "spiclk", "apb_pclk";
 453                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 454                 pinctrl-names = "default";
 455                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 456                 #address-cells = <1>;
 457                 #size-cells = <0>;
 458                 status = "disabled";
 459         };
 460
 461         spi1: spi@ff1d0000 {
 462                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 463                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 464                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 465                 clock-names = "spiclk", "apb_pclk";
 466                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 467                 pinctrl-names = "default";
 468                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 469                 #address-cells = <1>;
 470                 #size-cells = <0>;
 471                 status = "disabled";
 472         };
 473
 474         spi2: spi@ff1e0000 {
 475                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 476                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 477                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 478                 clock-names = "spiclk", "apb_pclk";
 479                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 480                 pinctrl-names = "default";
 481                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 482                 #address-cells = <1>;
 483                 #size-cells = <0>;
 484                 status = "disabled";
 485         };
 486
 487         spi4: spi@ff1f0000 {
 488                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 489                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 490                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 491                 clock-names = "spiclk", "apb_pclk";
 492                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 493                 pinctrl-names = "default";
 494                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 status = "disabled";
 498         };
 499
 500         spi5: spi@ff200000 {
 501                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 502                 reg = <0x0 0xff200000 0x0 0x1000>;
 503                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 504                 clock-names = "spiclk", "apb_pclk";
 505                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 506                 pinctrl-names = "default";
 507                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 508                 #address-cells = <1>;
 509                 #size-cells = <0>;
 510                 status = "disabled";
 511         };
 512
 513         thermal-zones {
 514                 cpu_thermal: cpu {
 515                         polling-delay-passive = <100>;
 516                         polling-delay = <1000>;
 517
 518                         thermal-sensors = <&tsadc 0>;
 519
 520                         trips {
 521                                 cpu_alert0: cpu_alert0 {
 522                                         temperature = <70000>;
 523                                         hysteresis = <2000>;
 524                                         type = "passive";
 525                                 };
 526                                 cpu_alert1: cpu_alert1 {
 527                                         temperature = <75000>;
 528                                         hysteresis = <2000>;
 529                                         type = "passive";
 530                                 };
 531                                 cpu_crit: cpu_crit {
 532                                         temperature = <95000>;
 533                                         hysteresis = <2000>;
 534                                         type = "critical";
 535                                 };
 536                         };
 537
 538                         cooling-maps {
 539                                 map0 {
 540                                         trip = <&cpu_alert0>;
 541                                         cooling-device =
 542                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 543                                 };
 544                                 map1 {
 545                                         trip = <&cpu_alert1>;
 546                                         cooling-device =
 547                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 548                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 549                                 };
 550                         };
 551                 };
 552
 553                 gpu_thermal: gpu {
 554                         polling-delay-passive = <100>;
 555                         polling-delay = <1000>;
 556
 557                         thermal-sensors = <&tsadc 1>;
 558
 559                         trips {
 560                                 gpu_alert0: gpu_alert0 {
 561                                         temperature = <75000>;
 562                                         hysteresis = <2000>;
 563                                         type = "passive";
 564                                 };
 565                                 gpu_crit: gpu_crit {
 566                                         temperature = <95000>;
 567                                         hysteresis = <2000>;
 568                                         type = "critical";
 569                                 };
 570                         };
 571
 572                         cooling-maps {
 573                                 map0 {
 574                                         trip = <&gpu_alert0>;
 575                                         cooling-device =
 576                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 577                                 };
 578                         };
 579                 };
 580         };
 581
 582         tsadc: tsadc@ff260000 {
 583                 compatible = "rockchip,rk3399-tsadc";
 584                 reg = <0x0 0xff260000 0x0 0x100>;
 585                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 586                 assigned-clocks = <&cru SCLK_TSADC>;
 587                 assigned-clock-rates = <750000>;
 588                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 589                 clock-names = "tsadc", "apb_pclk";
 590                 resets = <&cru SRST_TSADC>;
 591                 reset-names = "tsadc-apb";
 592                 rockchip,grf = <&grf>;
 593                 rockchip,hw-tshut-temp = <95000>;
 594                 pinctrl-names = "init", "default", "sleep";
 595                 pinctrl-0 = <&otp_gpio>;
 596                 pinctrl-1 = <&otp_out>;
 597                 pinctrl-2 = <&otp_gpio>;
 598                 #thermal-sensor-cells = <1>;
 599                 status = "disabled";
 600         };
 601
 602         qos_hdcp: qos@ffa90000 {
 603                 compatible = "syscon";
 604                 reg = <0x0 0xffa90000 0x0 0x20>;
 605         };
 606
 607         qos_iep: qos@ffa98000 {
 608                 compatible = "syscon";
 609                 reg = <0x0 0xffa98000 0x0 0x20>;
 610         };
 611
 612         qos_isp0_m0: qos@ffaa0000 {
 613                 compatible = "syscon";
 614                 reg = <0x0 0xffaa0000 0x0 0x20>;
 615         };
 616
 617         qos_isp0_m1: qos@ffaa0080 {
 618                 compatible = "syscon";
 619                 reg = <0x0 0xffaa0080 0x0 0x20>;
 620         };
 621
 622         qos_isp1_m0: qos@ffaa8000 {
 623                 compatible = "syscon";
 624                 reg = <0x0 0xffaa8000 0x0 0x20>;
 625         };
 626
 627         qos_isp1_m1: qos@ffaa8080 {
 628                 compatible = "syscon";
 629                 reg = <0x0 0xffaa8080 0x0 0x20>;
 630         };
 631
 632         qos_rga_r: qos@ffab0000 {
 633                 compatible = "syscon";
 634                 reg = <0x0 0xffab0000 0x0 0x20>;
 635         };
 636
 637         qos_rga_w: qos@ffab0080 {
 638                 compatible = "syscon";
 639                 reg = <0x0 0xffab0080 0x0 0x20>;
 640         };
 641
 642         qos_video_m0: qos@ffab8000 {
 643                 compatible = "syscon";
 644                 reg = <0x0 0xffab8000 0x0 0x20>;
 645         };
 646
 647         qos_video_m1_r: qos@ffac0000 {
 648                 compatible = "syscon";
 649                 reg = <0x0 0xffac0000 0x0 0x20>;
 650         };
 651
 652         qos_video_m1_w: qos@ffac0080 {
 653                 compatible = "syscon";
 654                 reg = <0x0 0xffac0080 0x0 0x20>;
 655         };
 656
 657         qos_vop_big_r: qos@ffac8000 {
 658                 compatible = "syscon";
 659                 reg = <0x0 0xffac8000 0x0 0x20>;
 660         };
 661
 662         qos_vop_big_w: qos@ffac8080 {
 663                 compatible = "syscon";
 664                 reg = <0x0 0xffac8080 0x0 0x20>;
 665         };
 666
 667         qos_vop_little: qos@ffad0000 {
 668                 compatible = "syscon";
 669                 reg = <0x0 0xffad0000 0x0 0x20>;
 670         };
 671
 672         qos_gpu: qos@ffae0000 {
 673                 compatible = "syscon";
 674                 reg = <0x0 0xffae0000 0x0 0x20>;
 675         };
 676
 677         pmu: power-management@ff310000 {
 678                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 679                 reg = <0x0 0xff310000 0x0 0x1000>;
 680
 681                 /*
 682                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 683                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 684                  * Some of the power domains are grouped together for every
 685                  * voltage domain.
 686                  * The detail contents as below.
 687                  */
 688                 power: power-controller {
 689                         compatible = "rockchip,rk3399-power-controller";
 690                         #power-domain-cells = <1>;
 691                         #address-cells = <1>;
 692                         #size-cells = <0>;
 693
 694                         /* These power domains are grouped by VD_CENTER */
 695                         pd_iep@RK3399_PD_IEP {
 696                                 reg = <RK3399_PD_IEP>;
 697                                 clocks = <&cru ACLK_IEP>,
 698                                          <&cru HCLK_IEP>;
 699                                 pm_qos = <&qos_iep>;
 700                         };
 701                         pd_rga@RK3399_PD_RGA {
 702                                 reg = <RK3399_PD_RGA>;
 703                                 clocks = <&cru ACLK_RGA>,
 704                                          <&cru HCLK_RGA>;
 705                                 pm_qos = <&qos_rga_r>,
 706                                          <&qos_rga_w>;
 707                         };
 708                         pd_vcodec@RK3399_PD_VCODEC {
 709                                 reg = <RK3399_PD_VCODEC>;
 710                                 clocks = <&cru ACLK_VCODEC>,
 711                                          <&cru HCLK_VCODEC>;
 712                                 pm_qos = <&qos_video_m0>;
 713                         };
 714                         pd_vdu@RK3399_PD_VDU {
 715                                 reg = <RK3399_PD_VDU>;
 716                                 clocks = <&cru ACLK_VDU>,
 717                                          <&cru HCLK_VDU>;
 718                                 pm_qos = <&qos_video_m1_r>,
 719                                          <&qos_video_m1_w>;
 720                         };
 721
 722                         /* These power domains are grouped by VD_GPU */
 723                         pd_gpu@RK3399_PD_GPU {
 724                                 reg = <RK3399_PD_GPU>;
 725                                 clocks = <&cru ACLK_GPU>;
 726                                 pm_qos = <&qos_gpu>;
 727                         };
 728
 729                         /* These power domains are grouped by VD_LOGIC */
 730                         pd_vio@RK3399_PD_VIO {
 731                                 reg = <RK3399_PD_VIO>;
 732                                 #address-cells = <1>;
 733                                 #size-cells = <0>;
 734
 735                                 pd_hdcp@RK3399_PD_HDCP {
 736                                         reg = <RK3399_PD_HDCP>;
 737                                         clocks = <&cru ACLK_HDCP>,
 738                                                  <&cru HCLK_HDCP>,
 739                                                  <&cru PCLK_HDCP>;
 740                                         pm_qos = <&qos_hdcp>;
 741                                 };
 742                                 pd_isp0@RK3399_PD_ISP0 {
 743                                         reg = <RK3399_PD_ISP0>;
 744                                         clocks = <&cru ACLK_ISP0>,
 745                                                  <&cru HCLK_ISP0>;
 746                                         pm_qos = <&qos_isp0_m0>,
 747                                                  <&qos_isp0_m1>;
 748                                 };
 749                                 pd_isp1@RK3399_PD_ISP1 {
 750                                         reg = <RK3399_PD_ISP1>;
 751                                         clocks = <&cru ACLK_ISP1>,
 752                                                  <&cru HCLK_ISP1>;
 753                                         pm_qos = <&qos_isp1_m0>,
 754                                                  <&qos_isp1_m1>;
 755                                 };
 756                                 pd_vo@RK3399_PD_VO {
 757                                         reg = <RK3399_PD_VO>;
 758                                         #address-cells = <1>;
 759                                         #size-cells = <0>;
 760
 761                                         pd_vopb@RK3399_PD_VOPB {
 762                                                 reg = <RK3399_PD_VOPB>;
 763                                                 clocks = <&cru ACLK_VOP0>,
 764                                                          <&cru HCLK_VOP0>;
 765                                                 pm_qos = <&qos_vop_big_r>,
 766                                                          <&qos_vop_big_w>;
 767                                         };
 768                                         pd_vopl@RK3399_PD_VOPL {
 769                                                 reg = <RK3399_PD_VOPL>;
 770                                                 clocks = <&cru ACLK_VOP1>,
 771                                                          <&cru HCLK_VOP1>;
 772                                                 pm_qos = <&qos_vop_little>;
 773                                         };
 774                                 };
 775                         };
 776                 };
 777         };
 778
 779         pmugrf: syscon@ff320000 {
 780                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 781                 reg = <0x0 0xff320000 0x0 0x1000>;
 782                 #address-cells = <1>;
 783                 #size-cells = <1>;
 784
 785                 pmu_io_domains: io-domains {
 786                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 787                         status = "disabled";
 788                 };
 789         };
 790
 791         spi3: spi@ff350000 {
 792                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 793                 reg = <0x0 0xff350000 0x0 0x1000>;
 794                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 795                 clock-names = "spiclk", "apb_pclk";
 796                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 797                 pinctrl-names = "default";
 798                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 799                 #address-cells = <1>;
 800                 #size-cells = <0>;
 801                 status = "disabled";
 802         };
 803
 804         uart4: serial@ff370000 {
 805                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 806                 reg = <0x0 0xff370000 0x0 0x100>;
 807                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 808                 clock-names = "baudclk", "apb_pclk";
 809                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 810                 reg-shift = <2>;
 811                 reg-io-width = <4>;
 812                 pinctrl-names = "default";
 813                 pinctrl-0 = <&uart4_xfer>;
 814                 status = "disabled";
 815         };
 816
 817         i2c0: i2c@ff3c0000 {
 818                 compatible = "rockchip,rk3399-i2c";
 819                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 820                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
 821                 assigned-clock-rates = <200000000>;
 822                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 823                 clock-names = "i2c", "pclk";
 824                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 825                 pinctrl-names = "default";
 826                 pinctrl-0 = <&i2c0_xfer>;
 827                 #address-cells = <1>;
 828                 #size-cells = <0>;
 829                 status = "disabled";
 830         };
 831
 832         i2c4: i2c@ff3d0000 {
 833                 compatible = "rockchip,rk3399-i2c";
 834                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 835                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
 836                 assigned-clock-rates = <200000000>;
 837                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 838                 clock-names = "i2c", "pclk";
 839                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 840                 pinctrl-names = "default";
 841                 pinctrl-0 = <&i2c4_xfer>;
 842                 #address-cells = <1>;
 843                 #size-cells = <0>;
 844                 status = "disabled";
 845         };
 846
 847         i2c8: i2c@ff3e0000 {
 848                 compatible = "rockchip,rk3399-i2c";
 849                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 850                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
 851                 assigned-clock-rates = <200000000>;
 852                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 853                 clock-names = "i2c", "pclk";
 854                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 855                 pinctrl-names = "default";
 856                 pinctrl-0 = <&i2c8_xfer>;
 857                 #address-cells = <1>;
 858                 #size-cells = <0>;
 859                 status = "disabled";
 860         };
 861
 862         pwm0: pwm@ff420000 {
 863                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 864                 reg = <0x0 0xff420000 0x0 0x10>;
 865                 #pwm-cells = <3>;
 866                 pinctrl-names = "default";
 867                 pinctrl-0 = <&pwm0_pin>;
 868                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 869                 clock-names = "pwm";
 870                 status = "disabled";
 871         };
 872
 873         pwm1: pwm@ff420010 {
 874                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 875                 reg = <0x0 0xff420010 0x0 0x10>;
 876                 #pwm-cells = <3>;
 877                 pinctrl-names = "default";
 878                 pinctrl-0 = <&pwm1_pin>;
 879                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 880                 clock-names = "pwm";
 881                 status = "disabled";
 882         };
 883
 884         pwm2: pwm@ff420020 {
 885                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 886                 reg = <0x0 0xff420020 0x0 0x10>;
 887                 #pwm-cells = <3>;
 888                 pinctrl-names = "default";
 889                 pinctrl-0 = <&pwm2_pin>;
 890                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 891                 clock-names = "pwm";
 892                 status = "disabled";
 893         };
 894
 895         pwm3: pwm@ff420030 {
 896                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 897                 reg = <0x0 0xff420030 0x0 0x10>;
 898                 #pwm-cells = <3>;
 899                 pinctrl-names = "default";
 900                 pinctrl-0 = <&pwm3a_pin>;
 901                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 902                 clock-names = "pwm";
 903                 status = "disabled";
 904         };
 905
 906         pmucru: pmu-clock-controller@ff750000 {
 907                 compatible = "rockchip,rk3399-pmucru";
 908                 reg = <0x0 0xff750000 0x0 0x1000>;
 909                 #clock-cells = <1>;
 910                 #reset-cells = <1>;
 911                 assigned-clocks = <&pmucru PLL_PPLL>;
 912                 assigned-clock-rates = <676000000>;
 913         };
 914
 915         cru: clock-controller@ff760000 {
 916                 compatible = "rockchip,rk3399-cru";
 917                 reg = <0x0 0xff760000 0x0 0x1000>;
 918                 #clock-cells = <1>;
 919                 #reset-cells = <1>;
 920                 assigned-clocks =
 921                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 922                         <&cru PLL_NPLL>,
 923                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 924                         <&cru PCLK_PERIHP>,
 925                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 926                         <&cru PCLK_PERILP0>,
 927                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 928                 assigned-clock-rates =
 929                          <594000000>,  <800000000>,
 930                         <1000000000>,
 931                          <150000000>,   <75000000>,
 932                           <37500000>,
 933                          <100000000>,  <100000000>,
 934                           <50000000>,
 935                          <100000000>,   <50000000>;
 936         };
 937
 938         grf: syscon@ff770000 {
 939                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
 940                 reg = <0x0 0xff770000 0x0 0x10000>;
 941                 #address-cells = <1>;
 942                 #size-cells = <1>;
 943
 944                 io_domains: io-domains {
 945                         compatible = "rockchip,rk3399-io-voltage-domain";
 946                         status = "disabled";
 947                 };
 948
 949                 u2phy0: usb2-phy@e450 {
 950                         compatible = "rockchip,rk3399-usb2phy";
 951                         reg = <0xe450 0x10>;
 952                         clocks = <&cru SCLK_USB2PHY0_REF>;
 953                         clock-names = "phyclk";
 954                         #clock-cells = <0>;
 955                         clock-output-names = "clk_usbphy0_480m";
 956                         status = "disabled";
 957
 958                         u2phy0_host: host-port {
 959                                 #phy-cells = <0>;
 960                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 961                                 interrupt-names = "linestate";
 962                                 status = "disabled";
 963                         };
 964                 };
 965
 966                 u2phy1: usb2-phy@e460 {
 967                         compatible = "rockchip,rk3399-usb2phy";
 968                         reg = <0xe460 0x10>;
 969                         clocks = <&cru SCLK_USB2PHY1_REF>;
 970                         clock-names = "phyclk";
 971                         #clock-cells = <0>;
 972                         clock-output-names = "clk_usbphy1_480m";
 973                         status = "disabled";
 974
 975                         u2phy1_host: host-port {
 976                                 #phy-cells = <0>;
 977                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 978                                 interrupt-names = "linestate";
 979                                 status = "disabled";
 980                         };
 981                 };
 982
 983                 emmc_phy: phy@f780 {
 984                         compatible = "rockchip,rk3399-emmc-phy";
 985                         reg = <0xf780 0x24>;
 986                         clocks = <&sdhci>;
 987                         clock-names = "emmcclk";
 988                         #phy-cells = <0>;
 989                         status = "disabled";
 990                 };
 991         };
 992
 993         watchdog@ff840000 {
 994                 compatible = "snps,dw-wdt";
 995                 reg = <0x0 0xff840000 0x0 0x100>;
 996                 clocks = <&cru PCLK_WDT>;
 997                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 998         };
 999
1000         rktimer: rktimer@ff850000 {
1001                 compatible = "rockchip,rk3399-timer";
1002                 reg = <0x0 0xff850000 0x0 0x1000>;
1003                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1004                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1005                 clock-names = "pclk", "timer";
1006         };
1007
1008         spdif: spdif@ff870000 {
1009                 compatible = "rockchip,rk3399-spdif";
1010                 reg = <0x0 0xff870000 0x0 0x1000>;
1011                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1012                 dmas = <&dmac_bus 7>;
1013                 dma-names = "tx";
1014                 clock-names = "mclk", "hclk";
1015                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1016                 pinctrl-names = "default";
1017                 pinctrl-0 = <&spdif_bus>;
1018                 status = "disabled";
1019         };
1020
1021         i2s0: i2s@ff880000 {
1022                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1023                 reg = <0x0 0xff880000 0x0 0x1000>;
1024                 rockchip,grf = <&grf>;
1025                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1026                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1027                 dma-names = "tx", "rx";
1028                 clock-names = "i2s_clk", "i2s_hclk";
1029                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1030                 pinctrl-names = "default";
1031                 pinctrl-0 = <&i2s0_8ch_bus>;
1032                 status = "disabled";
1033         };
1034
1035         i2s1: i2s@ff890000 {
1036                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1037                 reg = <0x0 0xff890000 0x0 0x1000>;
1038                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1039                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1040                 dma-names = "tx", "rx";
1041                 clock-names = "i2s_clk", "i2s_hclk";
1042                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1043                 pinctrl-names = "default";
1044                 pinctrl-0 = <&i2s1_2ch_bus>;
1045                 status = "disabled";
1046         };
1047
1048         i2s2: i2s@ff8a0000 {
1049                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1050                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1051                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1052                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1053                 dma-names = "tx", "rx";
1054                 clock-names = "i2s_clk", "i2s_hclk";
1055                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1056                 status = "disabled";
1057         };
1058
1059         pinctrl: pinctrl {
1060                 compatible = "rockchip,rk3399-pinctrl";
1061                 rockchip,grf = <&grf>;
1062                 rockchip,pmu = <&pmugrf>;
1063                 #address-cells = <2>;
1064                 #size-cells = <2>;
1065                 ranges;
1066
1067                 gpio0: gpio0@ff720000 {
1068                         compatible = "rockchip,gpio-bank";
1069                         reg = <0x0 0xff720000 0x0 0x100>;
1070                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1071                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1072
1073                         gpio-controller;
1074                         #gpio-cells = <0x2>;
1075
1076                         interrupt-controller;
1077                         #interrupt-cells = <0x2>;
1078                 };
1079
1080                 gpio1: gpio1@ff730000 {
1081                         compatible = "rockchip,gpio-bank";
1082                         reg = <0x0 0xff730000 0x0 0x100>;
1083                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1084                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1085
1086                         gpio-controller;
1087                         #gpio-cells = <0x2>;
1088
1089                         interrupt-controller;
1090                         #interrupt-cells = <0x2>;
1091                 };
1092
1093                 gpio2: gpio2@ff780000 {
1094                         compatible = "rockchip,gpio-bank";
1095                         reg = <0x0 0xff780000 0x0 0x100>;
1096                         clocks = <&cru PCLK_GPIO2>;
1097                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1098
1099                         gpio-controller;
1100                         #gpio-cells = <0x2>;
1101
1102                         interrupt-controller;
1103                         #interrupt-cells = <0x2>;
1104                 };
1105
1106                 gpio3: gpio3@ff788000 {
1107                         compatible = "rockchip,gpio-bank";
1108                         reg = <0x0 0xff788000 0x0 0x100>;
1109                         clocks = <&cru PCLK_GPIO3>;
1110                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1111
1112                         gpio-controller;
1113                         #gpio-cells = <0x2>;
1114
1115                         interrupt-controller;
1116                         #interrupt-cells = <0x2>;
1117                 };
1118
1119                 gpio4: gpio4@ff790000 {
1120                         compatible = "rockchip,gpio-bank";
1121                         reg = <0x0 0xff790000 0x0 0x100>;
1122                         clocks = <&cru PCLK_GPIO4>;
1123                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1124
1125                         gpio-controller;
1126                         #gpio-cells = <0x2>;
1127
1128                         interrupt-controller;
1129                         #interrupt-cells = <0x2>;
1130                 };
1131
1132                 pcfg_pull_up: pcfg-pull-up {
1133                         bias-pull-up;
1134                 };
1135
1136                 pcfg_pull_down: pcfg-pull-down {
1137                         bias-pull-down;
1138                 };
1139
1140                 pcfg_pull_none: pcfg-pull-none {
1141                         bias-disable;
1142                 };
1143
1144                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1145                         bias-disable;
1146                         drive-strength = <12>;
1147                 };
1148
1149                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1150                         bias-pull-up;
1151                         drive-strength = <8>;
1152                 };
1153
1154                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1155                         bias-pull-down;
1156                         drive-strength = <4>;
1157                 };
1158
1159                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1160                         bias-pull-up;
1161                         drive-strength = <2>;
1162                 };
1163
1164                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1165                         bias-pull-down;
1166                         drive-strength = <12>;
1167                 };
1168
1169                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1170                         bias-disable;
1171                         drive-strength = <13>;
1172                 };
1173
1174                 i2c0 {
1175                         i2c0_xfer: i2c0-xfer {
1176                                 rockchip,pins =
1177                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1178                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1179                         };
1180                 };
1181
1182                 i2c1 {
1183                         i2c1_xfer: i2c1-xfer {
1184                                 rockchip,pins =
1185                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1186                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1187                         };
1188                 };
1189
1190                 i2c2 {
1191                         i2c2_xfer: i2c2-xfer {
1192                                 rockchip,pins =
1193                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1194                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1195                         };
1196                 };
1197
1198                 i2c3 {
1199                         i2c3_xfer: i2c3-xfer {
1200                                 rockchip,pins =
1201                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1202                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1203                         };
1204                 };
1205
1206                 i2c4 {
1207                         i2c4_xfer: i2c4-xfer {
1208                                 rockchip,pins =
1209                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1210                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1211                         };
1212                 };
1213
1214                 i2c5 {
1215                         i2c5_xfer: i2c5-xfer {
1216                                 rockchip,pins =
1217                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1218                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1219                         };
1220                 };
1221
1222                 i2c6 {
1223                         i2c6_xfer: i2c6-xfer {
1224                                 rockchip,pins =
1225                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1226                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1227                         };
1228                 };
1229
1230                 i2c7 {
1231                         i2c7_xfer: i2c7-xfer {
1232                                 rockchip,pins =
1233                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1234                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1235                         };
1236                 };
1237
1238                 i2c8 {
1239                         i2c8_xfer: i2c8-xfer {
1240                                 rockchip,pins =
1241                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1242                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1243                         };
1244                 };
1245
1246                 i2s0 {
1247                         i2s0_8ch_bus: i2s0-8ch-bus {
1248                                 rockchip,pins =
1249                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1250                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1251                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1252                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1253                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1254                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1255                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1256                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1257                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1258                         };
1259                 };
1260
1261                 i2s1 {
1262                         i2s1_2ch_bus: i2s1-2ch-bus {
1263                                 rockchip,pins =
1264                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1265                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1266                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1267                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1268                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1269                         };
1270                 };
1271
1272                 sleep {
1273                         ap_pwroff: ap-pwroff {
1274                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1275                         };
1276
1277                         ddrio_pwroff: ddrio-pwroff {
1278                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1279                         };
1280                 };
1281
1282                 spdif {
1283                         spdif_bus: spdif-bus {
1284                                 rockchip,pins =
1285                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1286                         };
1287                 };
1288
1289                 spi0 {
1290                         spi0_clk: spi0-clk {
1291                                 rockchip,pins =
1292                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1293                         };
1294                         spi0_cs0: spi0-cs0 {
1295                                 rockchip,pins =
1296                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1297                         };
1298                         spi0_cs1: spi0-cs1 {
1299                                 rockchip,pins =
1300                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1301                         };
1302                         spi0_tx: spi0-tx {
1303                                 rockchip,pins =
1304                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1305                         };
1306                         spi0_rx: spi0-rx {
1307                                 rockchip,pins =
1308                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1309                         };
1310                 };
1311
1312                 spi1 {
1313                         spi1_clk: spi1-clk {
1314                                 rockchip,pins =
1315                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1316                         };
1317                         spi1_cs0: spi1-cs0 {
1318                                 rockchip,pins =
1319                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1320                         };
1321                         spi1_rx: spi1-rx {
1322                                 rockchip,pins =
1323                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1324                         };
1325                         spi1_tx: spi1-tx {
1326                                 rockchip,pins =
1327                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1328                         };
1329                 };
1330
1331                 spi2 {
1332                         spi2_clk: spi2-clk {
1333                                 rockchip,pins =
1334                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1335                         };
1336                         spi2_cs0: spi2-cs0 {
1337                                 rockchip,pins =
1338                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1339                         };
1340                         spi2_rx: spi2-rx {
1341                                 rockchip,pins =
1342                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1343                         };
1344                         spi2_tx: spi2-tx {
1345                                 rockchip,pins =
1346                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1347                         };
1348                 };
1349
1350                 spi3 {
1351                         spi3_clk: spi3-clk {
1352                                 rockchip,pins =
1353                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1354                         };
1355                         spi3_cs0: spi3-cs0 {
1356                                 rockchip,pins =
1357                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1358                         };
1359                         spi3_rx: spi3-rx {
1360                                 rockchip,pins =
1361                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1362                         };
1363                         spi3_tx: spi3-tx {
1364                                 rockchip,pins =
1365                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1366                         };
1367                 };
1368
1369                 spi4 {
1370                         spi4_clk: spi4-clk {
1371                                 rockchip,pins =
1372                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1373                         };
1374                         spi4_cs0: spi4-cs0 {
1375                                 rockchip,pins =
1376                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1377                         };
1378                         spi4_rx: spi4-rx {
1379                                 rockchip,pins =
1380                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1381                         };
1382                         spi4_tx: spi4-tx {
1383                                 rockchip,pins =
1384                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1385                         };
1386                 };
1387
1388                 spi5 {
1389                         spi5_clk: spi5-clk {
1390                                 rockchip,pins =
1391                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1392                         };
1393                         spi5_cs0: spi5-cs0 {
1394                                 rockchip,pins =
1395                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1396                         };
1397                         spi5_rx: spi5-rx {
1398                                 rockchip,pins =
1399                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1400                         };
1401                         spi5_tx: spi5-tx {
1402                                 rockchip,pins =
1403                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1404                         };
1405                 };
1406
1407                 tsadc {
1408                         otp_gpio: otp-gpio {
1409                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1410                         };
1411
1412                         otp_out: otp-out {
1413                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1414                         };
1415                 };
1416
1417                 uart0 {
1418                         uart0_xfer: uart0-xfer {
1419                                 rockchip,pins =
1420                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1421                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1422                         };
1423
1424                         uart0_cts: uart0-cts {
1425                                 rockchip,pins =
1426                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1427                         };
1428
1429                         uart0_rts: uart0-rts {
1430                                 rockchip,pins =
1431                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1432                         };
1433                 };
1434
1435                 uart1 {
1436                         uart1_xfer: uart1-xfer {
1437                                 rockchip,pins =
1438                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1439                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1440                         };
1441                 };
1442
1443                 uart2a {
1444                         uart2a_xfer: uart2a-xfer {
1445                                 rockchip,pins =
1446                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1447                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1448                         };
1449                 };
1450
1451                 uart2b {
1452                         uart2b_xfer: uart2b-xfer {
1453                                 rockchip,pins =
1454                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1455                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1456                         };
1457                 };
1458
1459                 uart2c {
1460                         uart2c_xfer: uart2c-xfer {
1461                                 rockchip,pins =
1462                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1463                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1464                         };
1465                 };
1466
1467                 uart3 {
1468                         uart3_xfer: uart3-xfer {
1469                                 rockchip,pins =
1470                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1471                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1472                         };
1473
1474                         uart3_cts: uart3-cts {
1475                                 rockchip,pins =
1476                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1477                         };
1478
1479                         uart3_rts: uart3-rts {
1480                                 rockchip,pins =
1481                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1482                         };
1483                 };
1484
1485                 uart4 {
1486                         uart4_xfer: uart4-xfer {
1487                                 rockchip,pins =
1488                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1489                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1490                         };
1491                 };
1492
1493                 uarthdcp {
1494                         uarthdcp_xfer: uarthdcp-xfer {
1495                                 rockchip,pins =
1496                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1497                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1498                         };
1499                 };
1500
1501                 pwm0 {
1502                         pwm0_pin: pwm0-pin {
1503                                 rockchip,pins =
1504                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1505                         };
1506
1507                         vop0_pwm_pin: vop0-pwm-pin {
1508                                 rockchip,pins =
1509                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1510                         };
1511                 };
1512
1513                 pwm1 {
1514                         pwm1_pin: pwm1-pin {
1515                                 rockchip,pins =
1516                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1517                         };
1518
1519                         vop1_pwm_pin: vop1-pwm-pin {
1520                                 rockchip,pins =
1521                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1522                         };
1523                 };
1524
1525                 pwm2 {
1526                         pwm2_pin: pwm2-pin {
1527                                 rockchip,pins =
1528                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1529                         };
1530                 };
1531
1532                 pwm3a {
1533                         pwm3a_pin: pwm3a-pin {
1534                                 rockchip,pins =
1535                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1536                         };
1537                 };
1538
1539                 pwm3b {
1540                         pwm3b_pin: pwm3b-pin {
1541                                 rockchip,pins =
1542                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1543                         };
1544                 };
1545         };
1546 };