arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 i2c6 = &i2c6;
  66                 i2c7 = &i2c7;
  67                 i2c8 = &i2c8;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73         };
  74
  75         cpus {
  76                 #address-cells = <2>;
  77                 #size-cells = <0>;
  78
  79                 cpu-map {
  80                         cluster0 {
  81                                 core0 {
  82                                         cpu = <&cpu_l0>;
  83                                 };
  84                                 core1 {
  85                                         cpu = <&cpu_l1>;
  86                                 };
  87                                 core2 {
  88                                         cpu = <&cpu_l2>;
  89                                 };
  90                                 core3 {
  91                                         cpu = <&cpu_l3>;
  92                                 };
  93                         };
  94
  95                         cluster1 {
  96                                 core0 {
  97                                         cpu = <&cpu_b0>;
  98                                 };
  99                                 core1 {
 100                                         cpu = <&cpu_b1>;
 101                                 };
 102                         };
 103                 };
 104
 105                 cpu_l0: cpu@0 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53", "arm,armv8";
 108                         reg = <0x0 0x0>;
 109                         enable-method = "psci";
 110                         #cooling-cells = <2>; /* min followed by max */
 111                         clocks = <&cru ARMCLKL>;
 112                 };
 113
 114                 cpu_l1: cpu@1 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a53", "arm,armv8";
 117                         reg = <0x0 0x1>;
 118                         enable-method = "psci";
 119                         clocks = <&cru ARMCLKL>;
 120                 };
 121
 122                 cpu_l2: cpu@2 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53", "arm,armv8";
 125                         reg = <0x0 0x2>;
 126                         enable-method = "psci";
 127                         clocks = <&cru ARMCLKL>;
 128                 };
 129
 130                 cpu_l3: cpu@3 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a53", "arm,armv8";
 133                         reg = <0x0 0x3>;
 134                         enable-method = "psci";
 135                         clocks = <&cru ARMCLKL>;
 136                 };
 137
 138                 cpu_b0: cpu@100 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a72", "arm,armv8";
 141                         reg = <0x0 0x100>;
 142                         enable-method = "psci";
 143                         #cooling-cells = <2>; /* min followed by max */
 144                         clocks = <&cru ARMCLKB>;
 145                 };
 146
 147                 cpu_b1: cpu@101 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72", "arm,armv8";
 150                         reg = <0x0 0x101>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKB>;
 153                 };
 154         };
 155
 156         psci {
 157                 compatible = "arm,psci-1.0";
 158                 method = "smc";
 159         };
 160
 161         timer {
 162                 compatible = "arm,armv8-timer";
 163                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 164                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 165                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 166                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 167         };
 168
 169         xin24m: xin24m {
 170                 compatible = "fixed-clock";
 171                 clock-frequency = <24000000>;
 172                 clock-output-names = "xin24m";
 173                 #clock-cells = <0>;
 174         };
 175
 176         amba {
 177                 compatible = "simple-bus";
 178                 #address-cells = <2>;
 179                 #size-cells = <2>;
 180                 ranges;
 181
 182                 dmac_bus: dma-controller@ff6d0000 {
 183                         compatible = "arm,pl330", "arm,primecell";
 184                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 185                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 187                         #dma-cells = <1>;
 188                         clocks = <&cru ACLK_DMAC0_PERILP>;
 189                         clock-names = "apb_pclk";
 190                 };
 191
 192                 dmac_peri: dma-controller@ff6e0000 {
 193                         compatible = "arm,pl330", "arm,primecell";
 194                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 195                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 197                         #dma-cells = <1>;
 198                         clocks = <&cru ACLK_DMAC1_PERILP>;
 199                         clock-names = "apb_pclk";
 200                 };
 201         };
 202
 203         sdio0: dwmmc@fe310000 {
 204                 compatible = "rockchip,rk3399-dw-mshc",
 205                              "rockchip,rk3288-dw-mshc";
 206                 reg = <0x0 0xfe310000 0x0 0x4000>;
 207                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 208                 clock-freq-min-max = <400000 150000000>;
 209                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 210                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 211                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 212                 fifo-depth = <0x100>;
 213                 status = "disabled";
 214         };
 215
 216         sdmmc: dwmmc@fe320000 {
 217                 compatible = "rockchip,rk3399-dw-mshc",
 218                              "rockchip,rk3288-dw-mshc";
 219                 reg = <0x0 0xfe320000 0x0 0x4000>;
 220                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 221                 clock-freq-min-max = <400000 150000000>;
 222                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 223                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 224                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 225                 fifo-depth = <0x100>;
 226                 status = "disabled";
 227         };
 228
 229         sdhci: sdhci@fe330000 {
 230                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 231                 reg = <0x0 0xfe330000 0x0 0x10000>;
 232                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 233                 arasan,soc-ctl-syscon = <&grf>;
 234                 assigned-clocks = <&cru SCLK_EMMC>;
 235                 assigned-clock-rates = <200000000>;
 236                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 237                 clock-names = "clk_xin", "clk_ahb";
 238                 clock-output-names = "emmc_cardclock";
 239                 #clock-cells = <0>;
 240                 phys = <&emmc_phy>;
 241                 phy-names = "phy_arasan";
 242                 status = "disabled";
 243         };
 244
 245         usb_host0_ehci: usb@fe380000 {
 246                 compatible = "generic-ehci";
 247                 reg = <0x0 0xfe380000 0x0 0x20000>;
 248                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 249                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 250                 clock-names = "hclk_host0", "hclk_host0_arb";
 251                 phys = <&u2phy0_host>;
 252                 phy-names = "usb";
 253                 status = "disabled";
 254         };
 255
 256         usb_host0_ohci: usb@fe3a0000 {
 257                 compatible = "generic-ohci";
 258                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 259                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 260                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 261                 clock-names = "hclk_host0", "hclk_host0_arb";
 262                 status = "disabled";
 263         };
 264
 265         usb_host1_ehci: usb@fe3c0000 {
 266                 compatible = "generic-ehci";
 267                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 268                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 270                 clock-names = "hclk_host1", "hclk_host1_arb";
 271                 phys = <&u2phy1_host>;
 272                 phy-names = "usb";
 273                 status = "disabled";
 274         };
 275
 276         usb_host1_ohci: usb@fe3e0000 {
 277                 compatible = "generic-ohci";
 278                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 279                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 280                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 281                 clock-names = "hclk_host1", "hclk_host1_arb";
 282                 status = "disabled";
 283         };
 284
 285         gic: interrupt-controller@fee00000 {
 286                 compatible = "arm,gic-v3";
 287                 #interrupt-cells = <3>;
 288                 #address-cells = <2>;
 289                 #size-cells = <2>;
 290                 ranges;
 291                 interrupt-controller;
 292
 293                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 294                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 295                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 296                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 297                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 298                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 299                 its: interrupt-controller@fee20000 {
 300                         compatible = "arm,gic-v3-its";
 301                         msi-controller;
 302                         reg = <0x0 0xfee20000 0x0 0x20000>;
 303                 };
 304         };
 305
 306         saradc: saradc@ff100000 {
 307                 compatible = "rockchip,rk3399-saradc";
 308                 reg = <0x0 0xff100000 0x0 0x100>;
 309                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 310                 #io-channel-cells = <1>;
 311                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 312                 clock-names = "saradc", "apb_pclk";
 313                 resets = <&cru SRST_P_SARADC>;
 314                 reset-names = "saradc-apb";
 315                 status = "disabled";
 316         };
 317
 318         i2c1: i2c@ff110000 {
 319                 compatible = "rockchip,rk3399-i2c";
 320                 reg = <0x0 0xff110000 0x0 0x1000>;
 321                 assigned-clocks = <&cru SCLK_I2C1>;
 322                 assigned-clock-rates = <200000000>;
 323                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 324                 clock-names = "i2c", "pclk";
 325                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 326                 pinctrl-names = "default";
 327                 pinctrl-0 = <&i2c1_xfer>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330                 status = "disabled";
 331         };
 332
 333         i2c2: i2c@ff120000 {
 334                 compatible = "rockchip,rk3399-i2c";
 335                 reg = <0x0 0xff120000 0x0 0x1000>;
 336                 assigned-clocks = <&cru SCLK_I2C2>;
 337                 assigned-clock-rates = <200000000>;
 338                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 339                 clock-names = "i2c", "pclk";
 340                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 341                 pinctrl-names = "default";
 342                 pinctrl-0 = <&i2c2_xfer>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 status = "disabled";
 346         };
 347
 348         i2c3: i2c@ff130000 {
 349                 compatible = "rockchip,rk3399-i2c";
 350                 reg = <0x0 0xff130000 0x0 0x1000>;
 351                 assigned-clocks = <&cru SCLK_I2C3>;
 352                 assigned-clock-rates = <200000000>;
 353                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 354                 clock-names = "i2c", "pclk";
 355                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 356                 pinctrl-names = "default";
 357                 pinctrl-0 = <&i2c3_xfer>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 status = "disabled";
 361         };
 362
 363         i2c5: i2c@ff140000 {
 364                 compatible = "rockchip,rk3399-i2c";
 365                 reg = <0x0 0xff140000 0x0 0x1000>;
 366                 assigned-clocks = <&cru SCLK_I2C5>;
 367                 assigned-clock-rates = <200000000>;
 368                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 369                 clock-names = "i2c", "pclk";
 370                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 371                 pinctrl-names = "default";
 372                 pinctrl-0 = <&i2c5_xfer>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 status = "disabled";
 376         };
 377
 378         i2c6: i2c@ff150000 {
 379                 compatible = "rockchip,rk3399-i2c";
 380                 reg = <0x0 0xff150000 0x0 0x1000>;
 381                 assigned-clocks = <&cru SCLK_I2C6>;
 382                 assigned-clock-rates = <200000000>;
 383                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 384                 clock-names = "i2c", "pclk";
 385                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&i2c6_xfer>;
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 status = "disabled";
 391         };
 392
 393         i2c7: i2c@ff160000 {
 394                 compatible = "rockchip,rk3399-i2c";
 395                 reg = <0x0 0xff160000 0x0 0x1000>;
 396                 assigned-clocks = <&cru SCLK_I2C7>;
 397                 assigned-clock-rates = <200000000>;
 398                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 399                 clock-names = "i2c", "pclk";
 400                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&i2c7_xfer>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 status = "disabled";
 406         };
 407
 408         uart0: serial@ff180000 {
 409                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 410                 reg = <0x0 0xff180000 0x0 0x100>;
 411                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 412                 clock-names = "baudclk", "apb_pclk";
 413                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 414                 reg-shift = <2>;
 415                 reg-io-width = <4>;
 416                 pinctrl-names = "default";
 417                 pinctrl-0 = <&uart0_xfer>;
 418                 status = "disabled";
 419         };
 420
 421         uart1: serial@ff190000 {
 422                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 423                 reg = <0x0 0xff190000 0x0 0x100>;
 424                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 425                 clock-names = "baudclk", "apb_pclk";
 426                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 427                 reg-shift = <2>;
 428                 reg-io-width = <4>;
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&uart1_xfer>;
 431                 status = "disabled";
 432         };
 433
 434         uart2: serial@ff1a0000 {
 435                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 436                 reg = <0x0 0xff1a0000 0x0 0x100>;
 437                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 438                 clock-names = "baudclk", "apb_pclk";
 439                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 440                 reg-shift = <2>;
 441                 reg-io-width = <4>;
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&uart2c_xfer>;
 444                 status = "disabled";
 445         };
 446
 447         uart3: serial@ff1b0000 {
 448                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 449                 reg = <0x0 0xff1b0000 0x0 0x100>;
 450                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 451                 clock-names = "baudclk", "apb_pclk";
 452                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 453                 reg-shift = <2>;
 454                 reg-io-width = <4>;
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&uart3_xfer>;
 457                 status = "disabled";
 458         };
 459
 460         spi0: spi@ff1c0000 {
 461                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 462                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 463                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 464                 clock-names = "spiclk", "apb_pclk";
 465                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 466                 pinctrl-names = "default";
 467                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 468                 #address-cells = <1>;
 469                 #size-cells = <0>;
 470                 status = "disabled";
 471         };
 472
 473         spi1: spi@ff1d0000 {
 474                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 475                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 476                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 477                 clock-names = "spiclk", "apb_pclk";
 478                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 479                 pinctrl-names = "default";
 480                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 481                 #address-cells = <1>;
 482                 #size-cells = <0>;
 483                 status = "disabled";
 484         };
 485
 486         spi2: spi@ff1e0000 {
 487                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 488                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 489                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 490                 clock-names = "spiclk", "apb_pclk";
 491                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 494                 #address-cells = <1>;
 495                 #size-cells = <0>;
 496                 status = "disabled";
 497         };
 498
 499         spi4: spi@ff1f0000 {
 500                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 501                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 502                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 503                 clock-names = "spiclk", "apb_pclk";
 504                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 505                 pinctrl-names = "default";
 506                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 507                 #address-cells = <1>;
 508                 #size-cells = <0>;
 509                 status = "disabled";
 510         };
 511
 512         spi5: spi@ff200000 {
 513                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 514                 reg = <0x0 0xff200000 0x0 0x1000>;
 515                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 516                 clock-names = "spiclk", "apb_pclk";
 517                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 518                 pinctrl-names = "default";
 519                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 status = "disabled";
 523         };
 524
 525         thermal-zones {
 526                 cpu_thermal: cpu {
 527                         polling-delay-passive = <100>;
 528                         polling-delay = <1000>;
 529
 530                         thermal-sensors = <&tsadc 0>;
 531
 532                         trips {
 533                                 cpu_alert0: cpu_alert0 {
 534                                         temperature = <70000>;
 535                                         hysteresis = <2000>;
 536                                         type = "passive";
 537                                 };
 538                                 cpu_alert1: cpu_alert1 {
 539                                         temperature = <75000>;
 540                                         hysteresis = <2000>;
 541                                         type = "passive";
 542                                 };
 543                                 cpu_crit: cpu_crit {
 544                                         temperature = <95000>;
 545                                         hysteresis = <2000>;
 546                                         type = "critical";
 547                                 };
 548                         };
 549
 550                         cooling-maps {
 551                                 map0 {
 552                                         trip = <&cpu_alert0>;
 553                                         cooling-device =
 554                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 555                                 };
 556                                 map1 {
 557                                         trip = <&cpu_alert1>;
 558                                         cooling-device =
 559                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 560                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 561                                 };
 562                         };
 563                 };
 564
 565                 gpu_thermal: gpu {
 566                         polling-delay-passive = <100>;
 567                         polling-delay = <1000>;
 568
 569                         thermal-sensors = <&tsadc 1>;
 570
 571                         trips {
 572                                 gpu_alert0: gpu_alert0 {
 573                                         temperature = <75000>;
 574                                         hysteresis = <2000>;
 575                                         type = "passive";
 576                                 };
 577                                 gpu_crit: gpu_crit {
 578                                         temperature = <95000>;
 579                                         hysteresis = <2000>;
 580                                         type = "critical";
 581                                 };
 582                         };
 583
 584                         cooling-maps {
 585                                 map0 {
 586                                         trip = <&gpu_alert0>;
 587                                         cooling-device =
 588                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 589                                 };
 590                         };
 591                 };
 592         };
 593
 594         tsadc: tsadc@ff260000 {
 595                 compatible = "rockchip,rk3399-tsadc";
 596                 reg = <0x0 0xff260000 0x0 0x100>;
 597                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 598                 assigned-clocks = <&cru SCLK_TSADC>;
 599                 assigned-clock-rates = <750000>;
 600                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 601                 clock-names = "tsadc", "apb_pclk";
 602                 resets = <&cru SRST_TSADC>;
 603                 reset-names = "tsadc-apb";
 604                 rockchip,grf = <&grf>;
 605                 rockchip,hw-tshut-temp = <95000>;
 606                 pinctrl-names = "init", "default", "sleep";
 607                 pinctrl-0 = <&otp_gpio>;
 608                 pinctrl-1 = <&otp_out>;
 609                 pinctrl-2 = <&otp_gpio>;
 610                 #thermal-sensor-cells = <1>;
 611                 status = "disabled";
 612         };
 613
 614         qos_gmac: qos@ffa5c000 {
 615                 compatible = "syscon";
 616                 reg = <0x0 0xffa5c000 0x0 0x20>;
 617         };
 618
 619         qos_hdcp: qos@ffa90000 {
 620                 compatible = "syscon";
 621                 reg = <0x0 0xffa90000 0x0 0x20>;
 622         };
 623
 624         qos_iep: qos@ffa98000 {
 625                 compatible = "syscon";
 626                 reg = <0x0 0xffa98000 0x0 0x20>;
 627         };
 628
 629         qos_isp0_m0: qos@ffaa0000 {
 630                 compatible = "syscon";
 631                 reg = <0x0 0xffaa0000 0x0 0x20>;
 632         };
 633
 634         qos_isp0_m1: qos@ffaa0080 {
 635                 compatible = "syscon";
 636                 reg = <0x0 0xffaa0080 0x0 0x20>;
 637         };
 638
 639         qos_isp1_m0: qos@ffaa8000 {
 640                 compatible = "syscon";
 641                 reg = <0x0 0xffaa8000 0x0 0x20>;
 642         };
 643
 644         qos_isp1_m1: qos@ffaa8080 {
 645                 compatible = "syscon";
 646                 reg = <0x0 0xffaa8080 0x0 0x20>;
 647         };
 648
 649         qos_rga_r: qos@ffab0000 {
 650                 compatible = "syscon";
 651                 reg = <0x0 0xffab0000 0x0 0x20>;
 652         };
 653
 654         qos_rga_w: qos@ffab0080 {
 655                 compatible = "syscon";
 656                 reg = <0x0 0xffab0080 0x0 0x20>;
 657         };
 658
 659         qos_video_m0: qos@ffab8000 {
 660                 compatible = "syscon";
 661                 reg = <0x0 0xffab8000 0x0 0x20>;
 662         };
 663
 664         qos_video_m1_r: qos@ffac0000 {
 665                 compatible = "syscon";
 666                 reg = <0x0 0xffac0000 0x0 0x20>;
 667         };
 668
 669         qos_video_m1_w: qos@ffac0080 {
 670                 compatible = "syscon";
 671                 reg = <0x0 0xffac0080 0x0 0x20>;
 672         };
 673
 674         qos_vop_big_r: qos@ffac8000 {
 675                 compatible = "syscon";
 676                 reg = <0x0 0xffac8000 0x0 0x20>;
 677         };
 678
 679         qos_vop_big_w: qos@ffac8080 {
 680                 compatible = "syscon";
 681                 reg = <0x0 0xffac8080 0x0 0x20>;
 682         };
 683
 684         qos_vop_little: qos@ffad0000 {
 685                 compatible = "syscon";
 686                 reg = <0x0 0xffad0000 0x0 0x20>;
 687         };
 688
 689         qos_gpu: qos@ffae0000 {
 690                 compatible = "syscon";
 691                 reg = <0x0 0xffae0000 0x0 0x20>;
 692         };
 693
 694         pmu: power-management@ff310000 {
 695                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 696                 reg = <0x0 0xff310000 0x0 0x1000>;
 697
 698                 /*
 699                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 700                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 701                  * Some of the power domains are grouped together for every
 702                  * voltage domain.
 703                  * The detail contents as below.
 704                  */
 705                 power: power-controller {
 706                         compatible = "rockchip,rk3399-power-controller";
 707                         #power-domain-cells = <1>;
 708                         #address-cells = <1>;
 709                         #size-cells = <0>;
 710
 711                         /* These power domains are grouped by VD_CENTER */
 712                         pd_iep@RK3399_PD_IEP {
 713                                 reg = <RK3399_PD_IEP>;
 714                                 clocks = <&cru ACLK_IEP>,
 715                                          <&cru HCLK_IEP>;
 716                                 pm_qos = <&qos_iep>;
 717                         };
 718                         pd_rga@RK3399_PD_RGA {
 719                                 reg = <RK3399_PD_RGA>;
 720                                 clocks = <&cru ACLK_RGA>,
 721                                          <&cru HCLK_RGA>;
 722                                 pm_qos = <&qos_rga_r>,
 723                                          <&qos_rga_w>;
 724                         };
 725                         pd_vcodec@RK3399_PD_VCODEC {
 726                                 reg = <RK3399_PD_VCODEC>;
 727                                 clocks = <&cru ACLK_VCODEC>,
 728                                          <&cru HCLK_VCODEC>;
 729                                 pm_qos = <&qos_video_m0>;
 730                         };
 731                         pd_vdu@RK3399_PD_VDU {
 732                                 reg = <RK3399_PD_VDU>;
 733                                 clocks = <&cru ACLK_VDU>,
 734                                          <&cru HCLK_VDU>;
 735                                 pm_qos = <&qos_video_m1_r>,
 736                                          <&qos_video_m1_w>;
 737                         };
 738
 739                         /* These power domains are grouped by VD_GPU */
 740                         pd_gpu@RK3399_PD_GPU {
 741                                 reg = <RK3399_PD_GPU>;
 742                                 clocks = <&cru ACLK_GPU>;
 743                                 pm_qos = <&qos_gpu>;
 744                         };
 745
 746                         /* These power domains are grouped by VD_LOGIC */
 747                         pd_gmac@RK3399_PD_GMAC {
 748                                 reg = <RK3399_PD_GMAC>;
 749                                 clocks = <&cru ACLK_GMAC>;
 750                                 pm_qos = <&qos_gmac>;
 751                         };
 752                         pd_vio@RK3399_PD_VIO {
 753                                 reg = <RK3399_PD_VIO>;
 754                                 #address-cells = <1>;
 755                                 #size-cells = <0>;
 756
 757                                 pd_hdcp@RK3399_PD_HDCP {
 758                                         reg = <RK3399_PD_HDCP>;
 759                                         clocks = <&cru ACLK_HDCP>,
 760                                                  <&cru HCLK_HDCP>,
 761                                                  <&cru PCLK_HDCP>;
 762                                         pm_qos = <&qos_hdcp>;
 763                                 };
 764                                 pd_isp0@RK3399_PD_ISP0 {
 765                                         reg = <RK3399_PD_ISP0>;
 766                                         clocks = <&cru ACLK_ISP0>,
 767                                                  <&cru HCLK_ISP0>;
 768                                         pm_qos = <&qos_isp0_m0>,
 769                                                  <&qos_isp0_m1>;
 770                                 };
 771                                 pd_isp1@RK3399_PD_ISP1 {
 772                                         reg = <RK3399_PD_ISP1>;
 773                                         clocks = <&cru ACLK_ISP1>,
 774                                                  <&cru HCLK_ISP1>;
 775                                         pm_qos = <&qos_isp1_m0>,
 776                                                  <&qos_isp1_m1>;
 777                                 };
 778                                 pd_vo@RK3399_PD_VO {
 779                                         reg = <RK3399_PD_VO>;
 780                                         #address-cells = <1>;
 781                                         #size-cells = <0>;
 782
 783                                         pd_vopb@RK3399_PD_VOPB {
 784                                                 reg = <RK3399_PD_VOPB>;
 785                                                 clocks = <&cru ACLK_VOP0>,
 786                                                          <&cru HCLK_VOP0>;
 787                                                 pm_qos = <&qos_vop_big_r>,
 788                                                          <&qos_vop_big_w>;
 789                                         };
 790                                         pd_vopl@RK3399_PD_VOPL {
 791                                                 reg = <RK3399_PD_VOPL>;
 792                                                 clocks = <&cru ACLK_VOP1>,
 793                                                          <&cru HCLK_VOP1>;
 794                                                 pm_qos = <&qos_vop_little>;
 795                                         };
 796                                 };
 797                         };
 798                 };
 799         };
 800
 801         pmugrf: syscon@ff320000 {
 802                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 803                 reg = <0x0 0xff320000 0x0 0x1000>;
 804                 #address-cells = <1>;
 805                 #size-cells = <1>;
 806
 807                 pmu_io_domains: io-domains {
 808                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 809                         status = "disabled";
 810                 };
 811         };
 812
 813         spi3: spi@ff350000 {
 814                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 815                 reg = <0x0 0xff350000 0x0 0x1000>;
 816                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 817                 clock-names = "spiclk", "apb_pclk";
 818                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 819                 pinctrl-names = "default";
 820                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 821                 #address-cells = <1>;
 822                 #size-cells = <0>;
 823                 status = "disabled";
 824         };
 825
 826         uart4: serial@ff370000 {
 827                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 828                 reg = <0x0 0xff370000 0x0 0x100>;
 829                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 830                 clock-names = "baudclk", "apb_pclk";
 831                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 832                 reg-shift = <2>;
 833                 reg-io-width = <4>;
 834                 pinctrl-names = "default";
 835                 pinctrl-0 = <&uart4_xfer>;
 836                 status = "disabled";
 837         };
 838
 839         i2c0: i2c@ff3c0000 {
 840                 compatible = "rockchip,rk3399-i2c";
 841                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 842                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
 843                 assigned-clock-rates = <200000000>;
 844                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 845                 clock-names = "i2c", "pclk";
 846                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 847                 pinctrl-names = "default";
 848                 pinctrl-0 = <&i2c0_xfer>;
 849                 #address-cells = <1>;
 850                 #size-cells = <0>;
 851                 status = "disabled";
 852         };
 853
 854         i2c4: i2c@ff3d0000 {
 855                 compatible = "rockchip,rk3399-i2c";
 856                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 857                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
 858                 assigned-clock-rates = <200000000>;
 859                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 860                 clock-names = "i2c", "pclk";
 861                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 862                 pinctrl-names = "default";
 863                 pinctrl-0 = <&i2c4_xfer>;
 864                 #address-cells = <1>;
 865                 #size-cells = <0>;
 866                 status = "disabled";
 867         };
 868
 869         i2c8: i2c@ff3e0000 {
 870                 compatible = "rockchip,rk3399-i2c";
 871                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 872                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
 873                 assigned-clock-rates = <200000000>;
 874                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 875                 clock-names = "i2c", "pclk";
 876                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 877                 pinctrl-names = "default";
 878                 pinctrl-0 = <&i2c8_xfer>;
 879                 #address-cells = <1>;
 880                 #size-cells = <0>;
 881                 status = "disabled";
 882         };
 883
 884         pwm0: pwm@ff420000 {
 885                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 886                 reg = <0x0 0xff420000 0x0 0x10>;
 887                 #pwm-cells = <3>;
 888                 pinctrl-names = "default";
 889                 pinctrl-0 = <&pwm0_pin>;
 890                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 891                 clock-names = "pwm";
 892                 status = "disabled";
 893         };
 894
 895         pwm1: pwm@ff420010 {
 896                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 897                 reg = <0x0 0xff420010 0x0 0x10>;
 898                 #pwm-cells = <3>;
 899                 pinctrl-names = "default";
 900                 pinctrl-0 = <&pwm1_pin>;
 901                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 902                 clock-names = "pwm";
 903                 status = "disabled";
 904         };
 905
 906         pwm2: pwm@ff420020 {
 907                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 908                 reg = <0x0 0xff420020 0x0 0x10>;
 909                 #pwm-cells = <3>;
 910                 pinctrl-names = "default";
 911                 pinctrl-0 = <&pwm2_pin>;
 912                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 913                 clock-names = "pwm";
 914                 status = "disabled";
 915         };
 916
 917         pwm3: pwm@ff420030 {
 918                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 919                 reg = <0x0 0xff420030 0x0 0x10>;
 920                 #pwm-cells = <3>;
 921                 pinctrl-names = "default";
 922                 pinctrl-0 = <&pwm3a_pin>;
 923                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 924                 clock-names = "pwm";
 925                 status = "disabled";
 926         };
 927
 928         pmucru: pmu-clock-controller@ff750000 {
 929                 compatible = "rockchip,rk3399-pmucru";
 930                 reg = <0x0 0xff750000 0x0 0x1000>;
 931                 #clock-cells = <1>;
 932                 #reset-cells = <1>;
 933                 assigned-clocks = <&pmucru PLL_PPLL>;
 934                 assigned-clock-rates = <676000000>;
 935         };
 936
 937         cru: clock-controller@ff760000 {
 938                 compatible = "rockchip,rk3399-cru";
 939                 reg = <0x0 0xff760000 0x0 0x1000>;
 940                 #clock-cells = <1>;
 941                 #reset-cells = <1>;
 942                 assigned-clocks =
 943                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 944                         <&cru PLL_NPLL>,
 945                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 946                         <&cru PCLK_PERIHP>,
 947                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 948                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
 949                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 950                 assigned-clock-rates =
 951                          <594000000>,  <800000000>,
 952                         <1000000000>,
 953                          <150000000>,   <75000000>,
 954                           <37500000>,
 955                          <100000000>,  <100000000>,
 956                           <50000000>, <600000000>,
 957                          <100000000>,   <50000000>;
 958         };
 959
 960         grf: syscon@ff770000 {
 961                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
 962                 reg = <0x0 0xff770000 0x0 0x10000>;
 963                 #address-cells = <1>;
 964                 #size-cells = <1>;
 965
 966                 io_domains: io-domains {
 967                         compatible = "rockchip,rk3399-io-voltage-domain";
 968                         status = "disabled";
 969                 };
 970
 971                 u2phy0: usb2-phy@e450 {
 972                         compatible = "rockchip,rk3399-usb2phy";
 973                         reg = <0xe450 0x10>;
 974                         clocks = <&cru SCLK_USB2PHY0_REF>;
 975                         clock-names = "phyclk";
 976                         #clock-cells = <0>;
 977                         clock-output-names = "clk_usbphy0_480m";
 978                         status = "disabled";
 979
 980                         u2phy0_host: host-port {
 981                                 #phy-cells = <0>;
 982                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 983                                 interrupt-names = "linestate";
 984                                 status = "disabled";
 985                         };
 986                 };
 987
 988                 u2phy1: usb2-phy@e460 {
 989                         compatible = "rockchip,rk3399-usb2phy";
 990                         reg = <0xe460 0x10>;
 991                         clocks = <&cru SCLK_USB2PHY1_REF>;
 992                         clock-names = "phyclk";
 993                         #clock-cells = <0>;
 994                         clock-output-names = "clk_usbphy1_480m";
 995                         status = "disabled";
 996
 997                         u2phy1_host: host-port {
 998                                 #phy-cells = <0>;
 999                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1000                                 interrupt-names = "linestate";
1001                                 status = "disabled";
1002                         };
1003                 };
1004
1005                 emmc_phy: phy@f780 {
1006                         compatible = "rockchip,rk3399-emmc-phy";
1007                         reg = <0xf780 0x24>;
1008                         clocks = <&sdhci>;
1009                         clock-names = "emmcclk";
1010                         #phy-cells = <0>;
1011                         status = "disabled";
1012                 };
1013
1014                 pcie_phy: pcie-phy {
1015                         compatible = "rockchip,rk3399-pcie-phy";
1016                         clocks = <&cru SCLK_PCIEPHY_REF>;
1017                         clock-names = "refclk";
1018                         #phy-cells = <0>;
1019                         resets = <&cru SRST_PCIEPHY>;
1020                         reset-names = "phy";
1021                         status = "disabled";
1022                 };
1023         };
1024
1025         watchdog@ff848000 {
1026                 compatible = "snps,dw-wdt";
1027                 reg = <0x0 0xff848000 0x0 0x100>;
1028                 clocks = <&cru PCLK_WDT>;
1029                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1030         };
1031
1032         rktimer: rktimer@ff850000 {
1033                 compatible = "rockchip,rk3399-timer";
1034                 reg = <0x0 0xff850000 0x0 0x1000>;
1035                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1036                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1037                 clock-names = "pclk", "timer";
1038         };
1039
1040         spdif: spdif@ff870000 {
1041                 compatible = "rockchip,rk3399-spdif";
1042                 reg = <0x0 0xff870000 0x0 0x1000>;
1043                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1044                 dmas = <&dmac_bus 7>;
1045                 dma-names = "tx";
1046                 clock-names = "mclk", "hclk";
1047                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1048                 pinctrl-names = "default";
1049                 pinctrl-0 = <&spdif_bus>;
1050                 status = "disabled";
1051         };
1052
1053         i2s0: i2s@ff880000 {
1054                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1055                 reg = <0x0 0xff880000 0x0 0x1000>;
1056                 rockchip,grf = <&grf>;
1057                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1058                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1059                 dma-names = "tx", "rx";
1060                 clock-names = "i2s_clk", "i2s_hclk";
1061                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1062                 pinctrl-names = "default";
1063                 pinctrl-0 = <&i2s0_8ch_bus>;
1064                 status = "disabled";
1065         };
1066
1067         i2s1: i2s@ff890000 {
1068                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1069                 reg = <0x0 0xff890000 0x0 0x1000>;
1070                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1071                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1072                 dma-names = "tx", "rx";
1073                 clock-names = "i2s_clk", "i2s_hclk";
1074                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1075                 pinctrl-names = "default";
1076                 pinctrl-0 = <&i2s1_2ch_bus>;
1077                 status = "disabled";
1078         };
1079
1080         i2s2: i2s@ff8a0000 {
1081                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1082                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1083                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1084                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1085                 dma-names = "tx", "rx";
1086                 clock-names = "i2s_clk", "i2s_hclk";
1087                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1088                 status = "disabled";
1089         };
1090
1091         pinctrl: pinctrl {
1092                 compatible = "rockchip,rk3399-pinctrl";
1093                 rockchip,grf = <&grf>;
1094                 rockchip,pmu = <&pmugrf>;
1095                 #address-cells = <2>;
1096                 #size-cells = <2>;
1097                 ranges;
1098
1099                 gpio0: gpio0@ff720000 {
1100                         compatible = "rockchip,gpio-bank";
1101                         reg = <0x0 0xff720000 0x0 0x100>;
1102                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1103                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1104
1105                         gpio-controller;
1106                         #gpio-cells = <0x2>;
1107
1108                         interrupt-controller;
1109                         #interrupt-cells = <0x2>;
1110                 };
1111
1112                 gpio1: gpio1@ff730000 {
1113                         compatible = "rockchip,gpio-bank";
1114                         reg = <0x0 0xff730000 0x0 0x100>;
1115                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1116                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1117
1118                         gpio-controller;
1119                         #gpio-cells = <0x2>;
1120
1121                         interrupt-controller;
1122                         #interrupt-cells = <0x2>;
1123                 };
1124
1125                 gpio2: gpio2@ff780000 {
1126                         compatible = "rockchip,gpio-bank";
1127                         reg = <0x0 0xff780000 0x0 0x100>;
1128                         clocks = <&cru PCLK_GPIO2>;
1129                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1130
1131                         gpio-controller;
1132                         #gpio-cells = <0x2>;
1133
1134                         interrupt-controller;
1135                         #interrupt-cells = <0x2>;
1136                 };
1137
1138                 gpio3: gpio3@ff788000 {
1139                         compatible = "rockchip,gpio-bank";
1140                         reg = <0x0 0xff788000 0x0 0x100>;
1141                         clocks = <&cru PCLK_GPIO3>;
1142                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1143
1144                         gpio-controller;
1145                         #gpio-cells = <0x2>;
1146
1147                         interrupt-controller;
1148                         #interrupt-cells = <0x2>;
1149                 };
1150
1151                 gpio4: gpio4@ff790000 {
1152                         compatible = "rockchip,gpio-bank";
1153                         reg = <0x0 0xff790000 0x0 0x100>;
1154                         clocks = <&cru PCLK_GPIO4>;
1155                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1156
1157                         gpio-controller;
1158                         #gpio-cells = <0x2>;
1159
1160                         interrupt-controller;
1161                         #interrupt-cells = <0x2>;
1162                 };
1163
1164                 pcfg_pull_up: pcfg-pull-up {
1165                         bias-pull-up;
1166                 };
1167
1168                 pcfg_pull_down: pcfg-pull-down {
1169                         bias-pull-down;
1170                 };
1171
1172                 pcfg_pull_none: pcfg-pull-none {
1173                         bias-disable;
1174                 };
1175
1176                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1177                         bias-disable;
1178                         drive-strength = <12>;
1179                 };
1180
1181                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1182                         bias-pull-up;
1183                         drive-strength = <8>;
1184                 };
1185
1186                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1187                         bias-pull-down;
1188                         drive-strength = <4>;
1189                 };
1190
1191                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1192                         bias-pull-up;
1193                         drive-strength = <2>;
1194                 };
1195
1196                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1197                         bias-pull-down;
1198                         drive-strength = <12>;
1199                 };
1200
1201                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1202                         bias-disable;
1203                         drive-strength = <13>;
1204                 };
1205
1206                 clock {
1207                         clk_32k: clk-32k {
1208                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1209                         };
1210                 };
1211
1212                 i2c0 {
1213                         i2c0_xfer: i2c0-xfer {
1214                                 rockchip,pins =
1215                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1216                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1217                         };
1218                 };
1219
1220                 i2c1 {
1221                         i2c1_xfer: i2c1-xfer {
1222                                 rockchip,pins =
1223                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1224                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1225                         };
1226                 };
1227
1228                 i2c2 {
1229                         i2c2_xfer: i2c2-xfer {
1230                                 rockchip,pins =
1231                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1232                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1233                         };
1234                 };
1235
1236                 i2c3 {
1237                         i2c3_xfer: i2c3-xfer {
1238                                 rockchip,pins =
1239                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1240                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1241                         };
1242                 };
1243
1244                 i2c4 {
1245                         i2c4_xfer: i2c4-xfer {
1246                                 rockchip,pins =
1247                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1248                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1249                         };
1250                 };
1251
1252                 i2c5 {
1253                         i2c5_xfer: i2c5-xfer {
1254                                 rockchip,pins =
1255                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1256                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1257                         };
1258                 };
1259
1260                 i2c6 {
1261                         i2c6_xfer: i2c6-xfer {
1262                                 rockchip,pins =
1263                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1264                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1265                         };
1266                 };
1267
1268                 i2c7 {
1269                         i2c7_xfer: i2c7-xfer {
1270                                 rockchip,pins =
1271                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1272                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1273                         };
1274                 };
1275
1276                 i2c8 {
1277                         i2c8_xfer: i2c8-xfer {
1278                                 rockchip,pins =
1279                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1280                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1281                         };
1282                 };
1283
1284                 i2s0 {
1285                         i2s0_8ch_bus: i2s0-8ch-bus {
1286                                 rockchip,pins =
1287                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1288                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1289                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1290                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1291                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1292                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1293                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1294                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1295                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1296                         };
1297                 };
1298
1299                 i2s1 {
1300                         i2s1_2ch_bus: i2s1-2ch-bus {
1301                                 rockchip,pins =
1302                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1303                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1304                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1305                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1306                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1307                         };
1308                 };
1309
1310                 sleep {
1311                         ap_pwroff: ap-pwroff {
1312                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1313                         };
1314
1315                         ddrio_pwroff: ddrio-pwroff {
1316                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1317                         };
1318                 };
1319
1320                 spdif {
1321                         spdif_bus: spdif-bus {
1322                                 rockchip,pins =
1323                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1324                         };
1325                 };
1326
1327                 spi0 {
1328                         spi0_clk: spi0-clk {
1329                                 rockchip,pins =
1330                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1331                         };
1332                         spi0_cs0: spi0-cs0 {
1333                                 rockchip,pins =
1334                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1335                         };
1336                         spi0_cs1: spi0-cs1 {
1337                                 rockchip,pins =
1338                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1339                         };
1340                         spi0_tx: spi0-tx {
1341                                 rockchip,pins =
1342                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1343                         };
1344                         spi0_rx: spi0-rx {
1345                                 rockchip,pins =
1346                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1347                         };
1348                 };
1349
1350                 spi1 {
1351                         spi1_clk: spi1-clk {
1352                                 rockchip,pins =
1353                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1354                         };
1355                         spi1_cs0: spi1-cs0 {
1356                                 rockchip,pins =
1357                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1358                         };
1359                         spi1_rx: spi1-rx {
1360                                 rockchip,pins =
1361                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1362                         };
1363                         spi1_tx: spi1-tx {
1364                                 rockchip,pins =
1365                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1366                         };
1367                 };
1368
1369                 spi2 {
1370                         spi2_clk: spi2-clk {
1371                                 rockchip,pins =
1372                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1373                         };
1374                         spi2_cs0: spi2-cs0 {
1375                                 rockchip,pins =
1376                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1377                         };
1378                         spi2_rx: spi2-rx {
1379                                 rockchip,pins =
1380                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1381                         };
1382                         spi2_tx: spi2-tx {
1383                                 rockchip,pins =
1384                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1385                         };
1386                 };
1387
1388                 spi3 {
1389                         spi3_clk: spi3-clk {
1390                                 rockchip,pins =
1391                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1392                         };
1393                         spi3_cs0: spi3-cs0 {
1394                                 rockchip,pins =
1395                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1396                         };
1397                         spi3_rx: spi3-rx {
1398                                 rockchip,pins =
1399                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1400                         };
1401                         spi3_tx: spi3-tx {
1402                                 rockchip,pins =
1403                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1404                         };
1405                 };
1406
1407                 spi4 {
1408                         spi4_clk: spi4-clk {
1409                                 rockchip,pins =
1410                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1411                         };
1412                         spi4_cs0: spi4-cs0 {
1413                                 rockchip,pins =
1414                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1415                         };
1416                         spi4_rx: spi4-rx {
1417                                 rockchip,pins =
1418                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1419                         };
1420                         spi4_tx: spi4-tx {
1421                                 rockchip,pins =
1422                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1423                         };
1424                 };
1425
1426                 spi5 {
1427                         spi5_clk: spi5-clk {
1428                                 rockchip,pins =
1429                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1430                         };
1431                         spi5_cs0: spi5-cs0 {
1432                                 rockchip,pins =
1433                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1434                         };
1435                         spi5_rx: spi5-rx {
1436                                 rockchip,pins =
1437                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1438                         };
1439                         spi5_tx: spi5-tx {
1440                                 rockchip,pins =
1441                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1442                         };
1443                 };
1444
1445                 tsadc {
1446                         otp_gpio: otp-gpio {
1447                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1448                         };
1449
1450                         otp_out: otp-out {
1451                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1452                         };
1453                 };
1454
1455                 uart0 {
1456                         uart0_xfer: uart0-xfer {
1457                                 rockchip,pins =
1458                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1459                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1460                         };
1461
1462                         uart0_cts: uart0-cts {
1463                                 rockchip,pins =
1464                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1465                         };
1466
1467                         uart0_rts: uart0-rts {
1468                                 rockchip,pins =
1469                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1470                         };
1471                 };
1472
1473                 uart1 {
1474                         uart1_xfer: uart1-xfer {
1475                                 rockchip,pins =
1476                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1477                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1478                         };
1479                 };
1480
1481                 uart2a {
1482                         uart2a_xfer: uart2a-xfer {
1483                                 rockchip,pins =
1484                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1485                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1486                         };
1487                 };
1488
1489                 uart2b {
1490                         uart2b_xfer: uart2b-xfer {
1491                                 rockchip,pins =
1492                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1493                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1494                         };
1495                 };
1496
1497                 uart2c {
1498                         uart2c_xfer: uart2c-xfer {
1499                                 rockchip,pins =
1500                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1501                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1502                         };
1503                 };
1504
1505                 uart3 {
1506                         uart3_xfer: uart3-xfer {
1507                                 rockchip,pins =
1508                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1509                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1510                         };
1511
1512                         uart3_cts: uart3-cts {
1513                                 rockchip,pins =
1514                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1515                         };
1516
1517                         uart3_rts: uart3-rts {
1518                                 rockchip,pins =
1519                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1520                         };
1521                 };
1522
1523                 uart4 {
1524                         uart4_xfer: uart4-xfer {
1525                                 rockchip,pins =
1526                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1527                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1528                         };
1529                 };
1530
1531                 uarthdcp {
1532                         uarthdcp_xfer: uarthdcp-xfer {
1533                                 rockchip,pins =
1534                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1535                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1536                         };
1537                 };
1538
1539                 pwm0 {
1540                         pwm0_pin: pwm0-pin {
1541                                 rockchip,pins =
1542                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1543                         };
1544
1545                         vop0_pwm_pin: vop0-pwm-pin {
1546                                 rockchip,pins =
1547                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1548                         };
1549                 };
1550
1551                 pwm1 {
1552                         pwm1_pin: pwm1-pin {
1553                                 rockchip,pins =
1554                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1555                         };
1556
1557                         vop1_pwm_pin: vop1-pwm-pin {
1558                                 rockchip,pins =
1559                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1560                         };
1561                 };
1562
1563                 pwm2 {
1564                         pwm2_pin: pwm2-pin {
1565                                 rockchip,pins =
1566                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1567                         };
1568                 };
1569
1570                 pwm3a {
1571                         pwm3a_pin: pwm3a-pin {
1572                                 rockchip,pins =
1573                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1574                         };
1575                 };
1576
1577                 pwm3b {
1578                         pwm3b_pin: pwm3b-pin {
1579                                 rockchip,pins =
1580                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1581                         };
1582                 };
1583         };
1584 };