arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 i2c6 = &i2c6;
  66                 i2c7 = &i2c7;
  67                 i2c8 = &i2c8;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73         };
  74
  75         cpus {
  76                 #address-cells = <2>;
  77                 #size-cells = <0>;
  78
  79                 cpu-map {
  80                         cluster0 {
  81                                 core0 {
  82                                         cpu = <&cpu_l0>;
  83                                 };
  84                                 core1 {
  85                                         cpu = <&cpu_l1>;
  86                                 };
  87                                 core2 {
  88                                         cpu = <&cpu_l2>;
  89                                 };
  90                                 core3 {
  91                                         cpu = <&cpu_l3>;
  92                                 };
  93                         };
  94
  95                         cluster1 {
  96                                 core0 {
  97                                         cpu = <&cpu_b0>;
  98                                 };
  99                                 core1 {
 100                                         cpu = <&cpu_b1>;
 101                                 };
 102                         };
 103                 };
 104
 105                 cpu_l0: cpu@0 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53", "arm,armv8";
 108                         reg = <0x0 0x0>;
 109                         enable-method = "psci";
 110                         #cooling-cells = <2>; /* min followed by max */
 111                         clocks = <&cru ARMCLKL>;
 112                 };
 113
 114                 cpu_l1: cpu@1 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a53", "arm,armv8";
 117                         reg = <0x0 0x1>;
 118                         enable-method = "psci";
 119                         clocks = <&cru ARMCLKL>;
 120                 };
 121
 122                 cpu_l2: cpu@2 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53", "arm,armv8";
 125                         reg = <0x0 0x2>;
 126                         enable-method = "psci";
 127                         clocks = <&cru ARMCLKL>;
 128                 };
 129
 130                 cpu_l3: cpu@3 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a53", "arm,armv8";
 133                         reg = <0x0 0x3>;
 134                         enable-method = "psci";
 135                         clocks = <&cru ARMCLKL>;
 136                 };
 137
 138                 cpu_b0: cpu@100 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a72", "arm,armv8";
 141                         reg = <0x0 0x100>;
 142                         enable-method = "psci";
 143                         #cooling-cells = <2>; /* min followed by max */
 144                         clocks = <&cru ARMCLKB>;
 145                 };
 146
 147                 cpu_b1: cpu@101 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72", "arm,armv8";
 150                         reg = <0x0 0x101>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKB>;
 153                 };
 154         };
 155
 156         psci {
 157                 compatible = "arm,psci-1.0";
 158                 method = "smc";
 159         };
 160
 161         timer {
 162                 compatible = "arm,armv8-timer";
 163                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 164                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 165                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 166                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 167         };
 168
 169         xin24m: xin24m {
 170                 compatible = "fixed-clock";
 171                 clock-frequency = <24000000>;
 172                 clock-output-names = "xin24m";
 173                 #clock-cells = <0>;
 174         };
 175
 176         amba {
 177                 compatible = "simple-bus";
 178                 #address-cells = <2>;
 179                 #size-cells = <2>;
 180                 ranges;
 181
 182                 dmac_bus: dma-controller@ff6d0000 {
 183                         compatible = "arm,pl330", "arm,primecell";
 184                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 185                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 187                         #dma-cells = <1>;
 188                         clocks = <&cru ACLK_DMAC0_PERILP>;
 189                         clock-names = "apb_pclk";
 190                 };
 191
 192                 dmac_peri: dma-controller@ff6e0000 {
 193                         compatible = "arm,pl330", "arm,primecell";
 194                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 195                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 197                         #dma-cells = <1>;
 198                         clocks = <&cru ACLK_DMAC1_PERILP>;
 199                         clock-names = "apb_pclk";
 200                 };
 201         };
 202
 203         sdio0: dwmmc@fe310000 {
 204                 compatible = "rockchip,rk3399-dw-mshc",
 205                              "rockchip,rk3288-dw-mshc";
 206                 reg = <0x0 0xfe310000 0x0 0x4000>;
 207                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 208                 clock-freq-min-max = <400000 150000000>;
 209                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 210                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 211                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 212                 fifo-depth = <0x100>;
 213                 status = "disabled";
 214         };
 215
 216         sdmmc: dwmmc@fe320000 {
 217                 compatible = "rockchip,rk3399-dw-mshc",
 218                              "rockchip,rk3288-dw-mshc";
 219                 reg = <0x0 0xfe320000 0x0 0x4000>;
 220                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 221                 clock-freq-min-max = <400000 150000000>;
 222                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 223                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 224                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 225                 fifo-depth = <0x100>;
 226                 status = "disabled";
 227         };
 228
 229         sdhci: sdhci@fe330000 {
 230                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 231                 reg = <0x0 0xfe330000 0x0 0x10000>;
 232                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 233                 arasan,soc-ctl-syscon = <&grf>;
 234                 assigned-clocks = <&cru SCLK_EMMC>;
 235                 assigned-clock-rates = <200000000>;
 236                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 237                 clock-names = "clk_xin", "clk_ahb";
 238                 clock-output-names = "emmc_cardclock";
 239                 #clock-cells = <0>;
 240                 phys = <&emmc_phy>;
 241                 phy-names = "phy_arasan";
 242                 status = "disabled";
 243         };
 244
 245         pcie0: pcie@f8000000 {
 246                 compatible = "rockchip,rk3399-pcie";
 247                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 248                       <0x0 0xfd000000 0x0 0x1000000>;
 249                 reg-names = "axi-base", "apb-base";
 250                 #address-cells = <3>;
 251                 #size-cells = <2>;
 252                 #interrupt-cells = <1>;
 253                 bus-range = <0x0 0x1>;
 254                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 255                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 256                 clock-names = "aclk", "aclk-perf",
 257                               "hclk", "pm";
 258                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 259                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 260                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 261                 interrupt-names = "sys", "legacy", "client";
 262                 interrupt-map-mask = <0 0 0 7>;
 263                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 264                                 <0 0 0 2 &pcie0_intc 1>,
 265                                 <0 0 0 3 &pcie0_intc 2>,
 266                                 <0 0 0 4 &pcie0_intc 3>;
 267                 msi-map = <0x0 &its 0x0 0x1000>;
 268                 phys = <&pcie_phy>;
 269                 phy-names = "pcie-phy";
 270                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
 271                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
 272                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 273                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
 274                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
 275                 status = "disabled";
 276
 277                 pcie0_intc: interrupt-controller {
 278                         interrupt-controller;
 279                         #address-cells = <0>;
 280                         #interrupt-cells = <1>;
 281                 };
 282         };
 283
 284         usb_host0_ehci: usb@fe380000 {
 285                 compatible = "generic-ehci";
 286                 reg = <0x0 0xfe380000 0x0 0x20000>;
 287                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 289                 clock-names = "hclk_host0", "hclk_host0_arb";
 290                 phys = <&u2phy0_host>;
 291                 phy-names = "usb";
 292                 status = "disabled";
 293         };
 294
 295         usb_host0_ohci: usb@fe3a0000 {
 296                 compatible = "generic-ohci";
 297                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 298                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 299                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 300                 clock-names = "hclk_host0", "hclk_host0_arb";
 301                 status = "disabled";
 302         };
 303
 304         usb_host1_ehci: usb@fe3c0000 {
 305                 compatible = "generic-ehci";
 306                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 307                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 308                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 309                 clock-names = "hclk_host1", "hclk_host1_arb";
 310                 phys = <&u2phy1_host>;
 311                 phy-names = "usb";
 312                 status = "disabled";
 313         };
 314
 315         usb_host1_ohci: usb@fe3e0000 {
 316                 compatible = "generic-ohci";
 317                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 318                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 320                 clock-names = "hclk_host1", "hclk_host1_arb";
 321                 status = "disabled";
 322         };
 323
 324         gic: interrupt-controller@fee00000 {
 325                 compatible = "arm,gic-v3";
 326                 #interrupt-cells = <3>;
 327                 #address-cells = <2>;
 328                 #size-cells = <2>;
 329                 ranges;
 330                 interrupt-controller;
 331
 332                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 333                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 334                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 335                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 336                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 337                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 338                 its: interrupt-controller@fee20000 {
 339                         compatible = "arm,gic-v3-its";
 340                         msi-controller;
 341                         reg = <0x0 0xfee20000 0x0 0x20000>;
 342                 };
 343         };
 344
 345         saradc: saradc@ff100000 {
 346                 compatible = "rockchip,rk3399-saradc";
 347                 reg = <0x0 0xff100000 0x0 0x100>;
 348                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 349                 #io-channel-cells = <1>;
 350                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 351                 clock-names = "saradc", "apb_pclk";
 352                 resets = <&cru SRST_P_SARADC>;
 353                 reset-names = "saradc-apb";
 354                 status = "disabled";
 355         };
 356
 357         i2c1: i2c@ff110000 {
 358                 compatible = "rockchip,rk3399-i2c";
 359                 reg = <0x0 0xff110000 0x0 0x1000>;
 360                 assigned-clocks = <&cru SCLK_I2C1>;
 361                 assigned-clock-rates = <200000000>;
 362                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 363                 clock-names = "i2c", "pclk";
 364                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&i2c1_xfer>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 status = "disabled";
 370         };
 371
 372         i2c2: i2c@ff120000 {
 373                 compatible = "rockchip,rk3399-i2c";
 374                 reg = <0x0 0xff120000 0x0 0x1000>;
 375                 assigned-clocks = <&cru SCLK_I2C2>;
 376                 assigned-clock-rates = <200000000>;
 377                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 378                 clock-names = "i2c", "pclk";
 379                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 380                 pinctrl-names = "default";
 381                 pinctrl-0 = <&i2c2_xfer>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 status = "disabled";
 385         };
 386
 387         i2c3: i2c@ff130000 {
 388                 compatible = "rockchip,rk3399-i2c";
 389                 reg = <0x0 0xff130000 0x0 0x1000>;
 390                 assigned-clocks = <&cru SCLK_I2C3>;
 391                 assigned-clock-rates = <200000000>;
 392                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 393                 clock-names = "i2c", "pclk";
 394                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&i2c3_xfer>;
 397                 #address-cells = <1>;
 398                 #size-cells = <0>;
 399                 status = "disabled";
 400         };
 401
 402         i2c5: i2c@ff140000 {
 403                 compatible = "rockchip,rk3399-i2c";
 404                 reg = <0x0 0xff140000 0x0 0x1000>;
 405                 assigned-clocks = <&cru SCLK_I2C5>;
 406                 assigned-clock-rates = <200000000>;
 407                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 408                 clock-names = "i2c", "pclk";
 409                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&i2c5_xfer>;
 412                 #address-cells = <1>;
 413                 #size-cells = <0>;
 414                 status = "disabled";
 415         };
 416
 417         i2c6: i2c@ff150000 {
 418                 compatible = "rockchip,rk3399-i2c";
 419                 reg = <0x0 0xff150000 0x0 0x1000>;
 420                 assigned-clocks = <&cru SCLK_I2C6>;
 421                 assigned-clock-rates = <200000000>;
 422                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 423                 clock-names = "i2c", "pclk";
 424                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&i2c6_xfer>;
 427                 #address-cells = <1>;
 428                 #size-cells = <0>;
 429                 status = "disabled";
 430         };
 431
 432         i2c7: i2c@ff160000 {
 433                 compatible = "rockchip,rk3399-i2c";
 434                 reg = <0x0 0xff160000 0x0 0x1000>;
 435                 assigned-clocks = <&cru SCLK_I2C7>;
 436                 assigned-clock-rates = <200000000>;
 437                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 438                 clock-names = "i2c", "pclk";
 439                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&i2c7_xfer>;
 442                 #address-cells = <1>;
 443                 #size-cells = <0>;
 444                 status = "disabled";
 445         };
 446
 447         uart0: serial@ff180000 {
 448                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 449                 reg = <0x0 0xff180000 0x0 0x100>;
 450                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 451                 clock-names = "baudclk", "apb_pclk";
 452                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 453                 reg-shift = <2>;
 454                 reg-io-width = <4>;
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&uart0_xfer>;
 457                 status = "disabled";
 458         };
 459
 460         uart1: serial@ff190000 {
 461                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 462                 reg = <0x0 0xff190000 0x0 0x100>;
 463                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 464                 clock-names = "baudclk", "apb_pclk";
 465                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 466                 reg-shift = <2>;
 467                 reg-io-width = <4>;
 468                 pinctrl-names = "default";
 469                 pinctrl-0 = <&uart1_xfer>;
 470                 status = "disabled";
 471         };
 472
 473         uart2: serial@ff1a0000 {
 474                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 475                 reg = <0x0 0xff1a0000 0x0 0x100>;
 476                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 477                 clock-names = "baudclk", "apb_pclk";
 478                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 479                 reg-shift = <2>;
 480                 reg-io-width = <4>;
 481                 pinctrl-names = "default";
 482                 pinctrl-0 = <&uart2c_xfer>;
 483                 status = "disabled";
 484         };
 485
 486         uart3: serial@ff1b0000 {
 487                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 488                 reg = <0x0 0xff1b0000 0x0 0x100>;
 489                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 490                 clock-names = "baudclk", "apb_pclk";
 491                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 492                 reg-shift = <2>;
 493                 reg-io-width = <4>;
 494                 pinctrl-names = "default";
 495                 pinctrl-0 = <&uart3_xfer>;
 496                 status = "disabled";
 497         };
 498
 499         spi0: spi@ff1c0000 {
 500                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 501                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 502                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 503                 clock-names = "spiclk", "apb_pclk";
 504                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 505                 pinctrl-names = "default";
 506                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 507                 #address-cells = <1>;
 508                 #size-cells = <0>;
 509                 status = "disabled";
 510         };
 511
 512         spi1: spi@ff1d0000 {
 513                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 514                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 515                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 516                 clock-names = "spiclk", "apb_pclk";
 517                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 518                 pinctrl-names = "default";
 519                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 status = "disabled";
 523         };
 524
 525         spi2: spi@ff1e0000 {
 526                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 527                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 528                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 529                 clock-names = "spiclk", "apb_pclk";
 530                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 531                 pinctrl-names = "default";
 532                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 status = "disabled";
 536         };
 537
 538         spi4: spi@ff1f0000 {
 539                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 540                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 541                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 542                 clock-names = "spiclk", "apb_pclk";
 543                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 544                 pinctrl-names = "default";
 545                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 status = "disabled";
 549         };
 550
 551         spi5: spi@ff200000 {
 552                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 553                 reg = <0x0 0xff200000 0x0 0x1000>;
 554                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 555                 clock-names = "spiclk", "apb_pclk";
 556                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 559                 #address-cells = <1>;
 560                 #size-cells = <0>;
 561                 status = "disabled";
 562         };
 563
 564         thermal-zones {
 565                 cpu_thermal: cpu {
 566                         polling-delay-passive = <100>;
 567                         polling-delay = <1000>;
 568
 569                         thermal-sensors = <&tsadc 0>;
 570
 571                         trips {
 572                                 cpu_alert0: cpu_alert0 {
 573                                         temperature = <70000>;
 574                                         hysteresis = <2000>;
 575                                         type = "passive";
 576                                 };
 577                                 cpu_alert1: cpu_alert1 {
 578                                         temperature = <75000>;
 579                                         hysteresis = <2000>;
 580                                         type = "passive";
 581                                 };
 582                                 cpu_crit: cpu_crit {
 583                                         temperature = <95000>;
 584                                         hysteresis = <2000>;
 585                                         type = "critical";
 586                                 };
 587                         };
 588
 589                         cooling-maps {
 590                                 map0 {
 591                                         trip = <&cpu_alert0>;
 592                                         cooling-device =
 593                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 594                                 };
 595                                 map1 {
 596                                         trip = <&cpu_alert1>;
 597                                         cooling-device =
 598                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 599                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 600                                 };
 601                         };
 602                 };
 603
 604                 gpu_thermal: gpu {
 605                         polling-delay-passive = <100>;
 606                         polling-delay = <1000>;
 607
 608                         thermal-sensors = <&tsadc 1>;
 609
 610                         trips {
 611                                 gpu_alert0: gpu_alert0 {
 612                                         temperature = <75000>;
 613                                         hysteresis = <2000>;
 614                                         type = "passive";
 615                                 };
 616                                 gpu_crit: gpu_crit {
 617                                         temperature = <95000>;
 618                                         hysteresis = <2000>;
 619                                         type = "critical";
 620                                 };
 621                         };
 622
 623                         cooling-maps {
 624                                 map0 {
 625                                         trip = <&gpu_alert0>;
 626                                         cooling-device =
 627                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 628                                 };
 629                         };
 630                 };
 631         };
 632
 633         tsadc: tsadc@ff260000 {
 634                 compatible = "rockchip,rk3399-tsadc";
 635                 reg = <0x0 0xff260000 0x0 0x100>;
 636                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 637                 assigned-clocks = <&cru SCLK_TSADC>;
 638                 assigned-clock-rates = <750000>;
 639                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 640                 clock-names = "tsadc", "apb_pclk";
 641                 resets = <&cru SRST_TSADC>;
 642                 reset-names = "tsadc-apb";
 643                 rockchip,grf = <&grf>;
 644                 rockchip,hw-tshut-temp = <95000>;
 645                 pinctrl-names = "init", "default", "sleep";
 646                 pinctrl-0 = <&otp_gpio>;
 647                 pinctrl-1 = <&otp_out>;
 648                 pinctrl-2 = <&otp_gpio>;
 649                 #thermal-sensor-cells = <1>;
 650                 status = "disabled";
 651         };
 652
 653         qos_gmac: qos@ffa5c000 {
 654                 compatible = "syscon";
 655                 reg = <0x0 0xffa5c000 0x0 0x20>;
 656         };
 657
 658         qos_hdcp: qos@ffa90000 {
 659                 compatible = "syscon";
 660                 reg = <0x0 0xffa90000 0x0 0x20>;
 661         };
 662
 663         qos_iep: qos@ffa98000 {
 664                 compatible = "syscon";
 665                 reg = <0x0 0xffa98000 0x0 0x20>;
 666         };
 667
 668         qos_isp0_m0: qos@ffaa0000 {
 669                 compatible = "syscon";
 670                 reg = <0x0 0xffaa0000 0x0 0x20>;
 671         };
 672
 673         qos_isp0_m1: qos@ffaa0080 {
 674                 compatible = "syscon";
 675                 reg = <0x0 0xffaa0080 0x0 0x20>;
 676         };
 677
 678         qos_isp1_m0: qos@ffaa8000 {
 679                 compatible = "syscon";
 680                 reg = <0x0 0xffaa8000 0x0 0x20>;
 681         };
 682
 683         qos_isp1_m1: qos@ffaa8080 {
 684                 compatible = "syscon";
 685                 reg = <0x0 0xffaa8080 0x0 0x20>;
 686         };
 687
 688         qos_rga_r: qos@ffab0000 {
 689                 compatible = "syscon";
 690                 reg = <0x0 0xffab0000 0x0 0x20>;
 691         };
 692
 693         qos_rga_w: qos@ffab0080 {
 694                 compatible = "syscon";
 695                 reg = <0x0 0xffab0080 0x0 0x20>;
 696         };
 697
 698         qos_video_m0: qos@ffab8000 {
 699                 compatible = "syscon";
 700                 reg = <0x0 0xffab8000 0x0 0x20>;
 701         };
 702
 703         qos_video_m1_r: qos@ffac0000 {
 704                 compatible = "syscon";
 705                 reg = <0x0 0xffac0000 0x0 0x20>;
 706         };
 707
 708         qos_video_m1_w: qos@ffac0080 {
 709                 compatible = "syscon";
 710                 reg = <0x0 0xffac0080 0x0 0x20>;
 711         };
 712
 713         qos_vop_big_r: qos@ffac8000 {
 714                 compatible = "syscon";
 715                 reg = <0x0 0xffac8000 0x0 0x20>;
 716         };
 717
 718         qos_vop_big_w: qos@ffac8080 {
 719                 compatible = "syscon";
 720                 reg = <0x0 0xffac8080 0x0 0x20>;
 721         };
 722
 723         qos_vop_little: qos@ffad0000 {
 724                 compatible = "syscon";
 725                 reg = <0x0 0xffad0000 0x0 0x20>;
 726         };
 727
 728         qos_gpu: qos@ffae0000 {
 729                 compatible = "syscon";
 730                 reg = <0x0 0xffae0000 0x0 0x20>;
 731         };
 732
 733         pmu: power-management@ff310000 {
 734                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 735                 reg = <0x0 0xff310000 0x0 0x1000>;
 736
 737                 /*
 738                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 739                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 740                  * Some of the power domains are grouped together for every
 741                  * voltage domain.
 742                  * The detail contents as below.
 743                  */
 744                 power: power-controller {
 745                         compatible = "rockchip,rk3399-power-controller";
 746                         #power-domain-cells = <1>;
 747                         #address-cells = <1>;
 748                         #size-cells = <0>;
 749
 750                         /* These power domains are grouped by VD_CENTER */
 751                         pd_iep@RK3399_PD_IEP {
 752                                 reg = <RK3399_PD_IEP>;
 753                                 clocks = <&cru ACLK_IEP>,
 754                                          <&cru HCLK_IEP>;
 755                                 pm_qos = <&qos_iep>;
 756                         };
 757                         pd_rga@RK3399_PD_RGA {
 758                                 reg = <RK3399_PD_RGA>;
 759                                 clocks = <&cru ACLK_RGA>,
 760                                          <&cru HCLK_RGA>;
 761                                 pm_qos = <&qos_rga_r>,
 762                                          <&qos_rga_w>;
 763                         };
 764                         pd_vcodec@RK3399_PD_VCODEC {
 765                                 reg = <RK3399_PD_VCODEC>;
 766                                 clocks = <&cru ACLK_VCODEC>,
 767                                          <&cru HCLK_VCODEC>;
 768                                 pm_qos = <&qos_video_m0>;
 769                         };
 770                         pd_vdu@RK3399_PD_VDU {
 771                                 reg = <RK3399_PD_VDU>;
 772                                 clocks = <&cru ACLK_VDU>,
 773                                          <&cru HCLK_VDU>;
 774                                 pm_qos = <&qos_video_m1_r>,
 775                                          <&qos_video_m1_w>;
 776                         };
 777
 778                         /* These power domains are grouped by VD_GPU */
 779                         pd_gpu@RK3399_PD_GPU {
 780                                 reg = <RK3399_PD_GPU>;
 781                                 clocks = <&cru ACLK_GPU>;
 782                                 pm_qos = <&qos_gpu>;
 783                         };
 784
 785                         /* These power domains are grouped by VD_LOGIC */
 786                         pd_gmac@RK3399_PD_GMAC {
 787                                 reg = <RK3399_PD_GMAC>;
 788                                 clocks = <&cru ACLK_GMAC>;
 789                                 pm_qos = <&qos_gmac>;
 790                         };
 791                         pd_vio@RK3399_PD_VIO {
 792                                 reg = <RK3399_PD_VIO>;
 793                                 #address-cells = <1>;
 794                                 #size-cells = <0>;
 795
 796                                 pd_hdcp@RK3399_PD_HDCP {
 797                                         reg = <RK3399_PD_HDCP>;
 798                                         clocks = <&cru ACLK_HDCP>,
 799                                                  <&cru HCLK_HDCP>,
 800                                                  <&cru PCLK_HDCP>;
 801                                         pm_qos = <&qos_hdcp>;
 802                                 };
 803                                 pd_isp0@RK3399_PD_ISP0 {
 804                                         reg = <RK3399_PD_ISP0>;
 805                                         clocks = <&cru ACLK_ISP0>,
 806                                                  <&cru HCLK_ISP0>;
 807                                         pm_qos = <&qos_isp0_m0>,
 808                                                  <&qos_isp0_m1>;
 809                                 };
 810                                 pd_isp1@RK3399_PD_ISP1 {
 811                                         reg = <RK3399_PD_ISP1>;
 812                                         clocks = <&cru ACLK_ISP1>,
 813                                                  <&cru HCLK_ISP1>;
 814                                         pm_qos = <&qos_isp1_m0>,
 815                                                  <&qos_isp1_m1>;
 816                                 };
 817                                 pd_tcpc0@RK3399_PD_TCPC0 {
 818                                         reg = <RK3399_PD_TCPD0>;
 819                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
 820                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
 821                                 };
 822                                 pd_tcpc1@RK3399_PD_TCPC1 {
 823                                         reg = <RK3399_PD_TCPD1>;
 824                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
 825                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
 826                                 };
 827                                 pd_vo@RK3399_PD_VO {
 828                                         reg = <RK3399_PD_VO>;
 829                                         #address-cells = <1>;
 830                                         #size-cells = <0>;
 831
 832                                         pd_vopb@RK3399_PD_VOPB {
 833                                                 reg = <RK3399_PD_VOPB>;
 834                                                 clocks = <&cru ACLK_VOP0>,
 835                                                          <&cru HCLK_VOP0>;
 836                                                 pm_qos = <&qos_vop_big_r>,
 837                                                          <&qos_vop_big_w>;
 838                                         };
 839                                         pd_vopl@RK3399_PD_VOPL {
 840                                                 reg = <RK3399_PD_VOPL>;
 841                                                 clocks = <&cru ACLK_VOP1>,
 842                                                          <&cru HCLK_VOP1>;
 843                                                 pm_qos = <&qos_vop_little>;
 844                                         };
 845                                 };
 846                         };
 847                 };
 848         };
 849
 850         pmugrf: syscon@ff320000 {
 851                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 852                 reg = <0x0 0xff320000 0x0 0x1000>;
 853                 #address-cells = <1>;
 854                 #size-cells = <1>;
 855
 856                 pmu_io_domains: io-domains {
 857                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 858                         status = "disabled";
 859                 };
 860         };
 861
 862         spi3: spi@ff350000 {
 863                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 864                 reg = <0x0 0xff350000 0x0 0x1000>;
 865                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 866                 clock-names = "spiclk", "apb_pclk";
 867                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 868                 pinctrl-names = "default";
 869                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 870                 #address-cells = <1>;
 871                 #size-cells = <0>;
 872                 status = "disabled";
 873         };
 874
 875         uart4: serial@ff370000 {
 876                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 877                 reg = <0x0 0xff370000 0x0 0x100>;
 878                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 879                 clock-names = "baudclk", "apb_pclk";
 880                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 881                 reg-shift = <2>;
 882                 reg-io-width = <4>;
 883                 pinctrl-names = "default";
 884                 pinctrl-0 = <&uart4_xfer>;
 885                 status = "disabled";
 886         };
 887
 888         i2c0: i2c@ff3c0000 {
 889                 compatible = "rockchip,rk3399-i2c";
 890                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 891                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
 892                 assigned-clock-rates = <200000000>;
 893                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 894                 clock-names = "i2c", "pclk";
 895                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 896                 pinctrl-names = "default";
 897                 pinctrl-0 = <&i2c0_xfer>;
 898                 #address-cells = <1>;
 899                 #size-cells = <0>;
 900                 status = "disabled";
 901         };
 902
 903         i2c4: i2c@ff3d0000 {
 904                 compatible = "rockchip,rk3399-i2c";
 905                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 906                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
 907                 assigned-clock-rates = <200000000>;
 908                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 909                 clock-names = "i2c", "pclk";
 910                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 911                 pinctrl-names = "default";
 912                 pinctrl-0 = <&i2c4_xfer>;
 913                 #address-cells = <1>;
 914                 #size-cells = <0>;
 915                 status = "disabled";
 916         };
 917
 918         i2c8: i2c@ff3e0000 {
 919                 compatible = "rockchip,rk3399-i2c";
 920                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 921                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
 922                 assigned-clock-rates = <200000000>;
 923                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 924                 clock-names = "i2c", "pclk";
 925                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 926                 pinctrl-names = "default";
 927                 pinctrl-0 = <&i2c8_xfer>;
 928                 #address-cells = <1>;
 929                 #size-cells = <0>;
 930                 status = "disabled";
 931         };
 932
 933         pwm0: pwm@ff420000 {
 934                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 935                 reg = <0x0 0xff420000 0x0 0x10>;
 936                 #pwm-cells = <3>;
 937                 pinctrl-names = "default";
 938                 pinctrl-0 = <&pwm0_pin>;
 939                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 940                 clock-names = "pwm";
 941                 status = "disabled";
 942         };
 943
 944         pwm1: pwm@ff420010 {
 945                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 946                 reg = <0x0 0xff420010 0x0 0x10>;
 947                 #pwm-cells = <3>;
 948                 pinctrl-names = "default";
 949                 pinctrl-0 = <&pwm1_pin>;
 950                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 951                 clock-names = "pwm";
 952                 status = "disabled";
 953         };
 954
 955         pwm2: pwm@ff420020 {
 956                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 957                 reg = <0x0 0xff420020 0x0 0x10>;
 958                 #pwm-cells = <3>;
 959                 pinctrl-names = "default";
 960                 pinctrl-0 = <&pwm2_pin>;
 961                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 962                 clock-names = "pwm";
 963                 status = "disabled";
 964         };
 965
 966         pwm3: pwm@ff420030 {
 967                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 968                 reg = <0x0 0xff420030 0x0 0x10>;
 969                 #pwm-cells = <3>;
 970                 pinctrl-names = "default";
 971                 pinctrl-0 = <&pwm3a_pin>;
 972                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 973                 clock-names = "pwm";
 974                 status = "disabled";
 975         };
 976
 977         efuse0: efuse@ff690000 {
 978                 compatible = "rockchip,rk3399-efuse";
 979                 reg = <0x0 0xff690000 0x0 0x80>;
 980                 #address-cells = <1>;
 981                 #size-cells = <1>;
 982                 clocks = <&cru PCLK_EFUSE1024NS>;
 983                 clock-names = "pclk_efuse";
 984
 985                 /* Data cells */
 986                 cpub_leakage: cpu-leakage@17 {
 987                         reg = <0x17 0x1>;
 988                 };
 989                 gpu_leakage: gpu-leakage@18 {
 990                         reg = <0x18 0x1>;
 991                 };
 992                 center_leakage: center-leakage@19 {
 993                         reg = <0x19 0x1>;
 994                 };
 995                 cpul_leakage: cpu-leakage@1a {
 996                         reg = <0x1a 0x1>;
 997                 };
 998                 logic_leakage: logic-leakage@1b {
 999                         reg = <0x1b 0x1>;
1000                 };
1001                 wafer_info: wafer-info@1c {
1002                         reg = <0x1c 0x1>;
1003                 };
1004         };
1005
1006         pmucru: pmu-clock-controller@ff750000 {
1007                 compatible = "rockchip,rk3399-pmucru";
1008                 reg = <0x0 0xff750000 0x0 0x1000>;
1009                 #clock-cells = <1>;
1010                 #reset-cells = <1>;
1011                 assigned-clocks = <&pmucru PLL_PPLL>;
1012                 assigned-clock-rates = <676000000>;
1013         };
1014
1015         cru: clock-controller@ff760000 {
1016                 compatible = "rockchip,rk3399-cru";
1017                 reg = <0x0 0xff760000 0x0 0x1000>;
1018                 #clock-cells = <1>;
1019                 #reset-cells = <1>;
1020                 assigned-clocks =
1021                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1022                         <&cru PLL_NPLL>,
1023                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1024                         <&cru PCLK_PERIHP>,
1025                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1026                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1027                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1028                 assigned-clock-rates =
1029                          <594000000>,  <800000000>,
1030                         <1000000000>,
1031                          <150000000>,   <75000000>,
1032                           <37500000>,
1033                          <100000000>,  <100000000>,
1034                           <50000000>, <600000000>,
1035                          <100000000>,   <50000000>;
1036         };
1037
1038         grf: syscon@ff770000 {
1039                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1040                 reg = <0x0 0xff770000 0x0 0x10000>;
1041                 #address-cells = <1>;
1042                 #size-cells = <1>;
1043
1044                 io_domains: io-domains {
1045                         compatible = "rockchip,rk3399-io-voltage-domain";
1046                         status = "disabled";
1047                 };
1048
1049                 u2phy0: usb2-phy@e450 {
1050                         compatible = "rockchip,rk3399-usb2phy";
1051                         reg = <0xe450 0x10>;
1052                         clocks = <&cru SCLK_USB2PHY0_REF>;
1053                         clock-names = "phyclk";
1054                         #clock-cells = <0>;
1055                         clock-output-names = "clk_usbphy0_480m";
1056                         status = "disabled";
1057
1058                         u2phy0_host: host-port {
1059                                 #phy-cells = <0>;
1060                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1061                                 interrupt-names = "linestate";
1062                                 status = "disabled";
1063                         };
1064                 };
1065
1066                 u2phy1: usb2-phy@e460 {
1067                         compatible = "rockchip,rk3399-usb2phy";
1068                         reg = <0xe460 0x10>;
1069                         clocks = <&cru SCLK_USB2PHY1_REF>;
1070                         clock-names = "phyclk";
1071                         #clock-cells = <0>;
1072                         clock-output-names = "clk_usbphy1_480m";
1073                         status = "disabled";
1074
1075                         u2phy1_host: host-port {
1076                                 #phy-cells = <0>;
1077                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1078                                 interrupt-names = "linestate";
1079                                 status = "disabled";
1080                         };
1081                 };
1082
1083                 emmc_phy: phy@f780 {
1084                         compatible = "rockchip,rk3399-emmc-phy";
1085                         reg = <0xf780 0x24>;
1086                         clocks = <&sdhci>;
1087                         clock-names = "emmcclk";
1088                         #phy-cells = <0>;
1089                         status = "disabled";
1090                 };
1091
1092                 pcie_phy: pcie-phy {
1093                         compatible = "rockchip,rk3399-pcie-phy";
1094                         clocks = <&cru SCLK_PCIEPHY_REF>;
1095                         clock-names = "refclk";
1096                         #phy-cells = <0>;
1097                         resets = <&cru SRST_PCIEPHY>;
1098                         reset-names = "phy";
1099                         status = "disabled";
1100                 };
1101         };
1102
1103         watchdog@ff848000 {
1104                 compatible = "snps,dw-wdt";
1105                 reg = <0x0 0xff848000 0x0 0x100>;
1106                 clocks = <&cru PCLK_WDT>;
1107                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1108         };
1109
1110         rktimer: rktimer@ff850000 {
1111                 compatible = "rockchip,rk3399-timer";
1112                 reg = <0x0 0xff850000 0x0 0x1000>;
1113                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1114                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1115                 clock-names = "pclk", "timer";
1116         };
1117
1118         spdif: spdif@ff870000 {
1119                 compatible = "rockchip,rk3399-spdif";
1120                 reg = <0x0 0xff870000 0x0 0x1000>;
1121                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1122                 dmas = <&dmac_bus 7>;
1123                 dma-names = "tx";
1124                 clock-names = "mclk", "hclk";
1125                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1126                 pinctrl-names = "default";
1127                 pinctrl-0 = <&spdif_bus>;
1128                 status = "disabled";
1129         };
1130
1131         i2s0: i2s@ff880000 {
1132                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1133                 reg = <0x0 0xff880000 0x0 0x1000>;
1134                 rockchip,grf = <&grf>;
1135                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1136                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1137                 dma-names = "tx", "rx";
1138                 clock-names = "i2s_clk", "i2s_hclk";
1139                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1140                 pinctrl-names = "default";
1141                 pinctrl-0 = <&i2s0_8ch_bus>;
1142                 status = "disabled";
1143         };
1144
1145         i2s1: i2s@ff890000 {
1146                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1147                 reg = <0x0 0xff890000 0x0 0x1000>;
1148                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1149                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1150                 dma-names = "tx", "rx";
1151                 clock-names = "i2s_clk", "i2s_hclk";
1152                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1153                 pinctrl-names = "default";
1154                 pinctrl-0 = <&i2s1_2ch_bus>;
1155                 status = "disabled";
1156         };
1157
1158         i2s2: i2s@ff8a0000 {
1159                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1160                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1161                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1162                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1163                 dma-names = "tx", "rx";
1164                 clock-names = "i2s_clk", "i2s_hclk";
1165                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1166                 status = "disabled";
1167         };
1168
1169         pinctrl: pinctrl {
1170                 compatible = "rockchip,rk3399-pinctrl";
1171                 rockchip,grf = <&grf>;
1172                 rockchip,pmu = <&pmugrf>;
1173                 #address-cells = <2>;
1174                 #size-cells = <2>;
1175                 ranges;
1176
1177                 gpio0: gpio0@ff720000 {
1178                         compatible = "rockchip,gpio-bank";
1179                         reg = <0x0 0xff720000 0x0 0x100>;
1180                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1181                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1182
1183                         gpio-controller;
1184                         #gpio-cells = <0x2>;
1185
1186                         interrupt-controller;
1187                         #interrupt-cells = <0x2>;
1188                 };
1189
1190                 gpio1: gpio1@ff730000 {
1191                         compatible = "rockchip,gpio-bank";
1192                         reg = <0x0 0xff730000 0x0 0x100>;
1193                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1194                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1195
1196                         gpio-controller;
1197                         #gpio-cells = <0x2>;
1198
1199                         interrupt-controller;
1200                         #interrupt-cells = <0x2>;
1201                 };
1202
1203                 gpio2: gpio2@ff780000 {
1204                         compatible = "rockchip,gpio-bank";
1205                         reg = <0x0 0xff780000 0x0 0x100>;
1206                         clocks = <&cru PCLK_GPIO2>;
1207                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1208
1209                         gpio-controller;
1210                         #gpio-cells = <0x2>;
1211
1212                         interrupt-controller;
1213                         #interrupt-cells = <0x2>;
1214                 };
1215
1216                 gpio3: gpio3@ff788000 {
1217                         compatible = "rockchip,gpio-bank";
1218                         reg = <0x0 0xff788000 0x0 0x100>;
1219                         clocks = <&cru PCLK_GPIO3>;
1220                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1221
1222                         gpio-controller;
1223                         #gpio-cells = <0x2>;
1224
1225                         interrupt-controller;
1226                         #interrupt-cells = <0x2>;
1227                 };
1228
1229                 gpio4: gpio4@ff790000 {
1230                         compatible = "rockchip,gpio-bank";
1231                         reg = <0x0 0xff790000 0x0 0x100>;
1232                         clocks = <&cru PCLK_GPIO4>;
1233                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1234
1235                         gpio-controller;
1236                         #gpio-cells = <0x2>;
1237
1238                         interrupt-controller;
1239                         #interrupt-cells = <0x2>;
1240                 };
1241
1242                 pcfg_pull_up: pcfg-pull-up {
1243                         bias-pull-up;
1244                 };
1245
1246                 pcfg_pull_down: pcfg-pull-down {
1247                         bias-pull-down;
1248                 };
1249
1250                 pcfg_pull_none: pcfg-pull-none {
1251                         bias-disable;
1252                 };
1253
1254                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1255                         bias-disable;
1256                         drive-strength = <12>;
1257                 };
1258
1259                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1260                         bias-pull-up;
1261                         drive-strength = <8>;
1262                 };
1263
1264                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1265                         bias-pull-down;
1266                         drive-strength = <4>;
1267                 };
1268
1269                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1270                         bias-pull-up;
1271                         drive-strength = <2>;
1272                 };
1273
1274                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1275                         bias-pull-down;
1276                         drive-strength = <12>;
1277                 };
1278
1279                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1280                         bias-disable;
1281                         drive-strength = <13>;
1282                 };
1283
1284                 clock {
1285                         clk_32k: clk-32k {
1286                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1287                         };
1288                 };
1289
1290                 i2c0 {
1291                         i2c0_xfer: i2c0-xfer {
1292                                 rockchip,pins =
1293                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1294                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1295                         };
1296                 };
1297
1298                 i2c1 {
1299                         i2c1_xfer: i2c1-xfer {
1300                                 rockchip,pins =
1301                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1302                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1303                         };
1304                 };
1305
1306                 i2c2 {
1307                         i2c2_xfer: i2c2-xfer {
1308                                 rockchip,pins =
1309                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1310                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1311                         };
1312                 };
1313
1314                 i2c3 {
1315                         i2c3_xfer: i2c3-xfer {
1316                                 rockchip,pins =
1317                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1318                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1319                         };
1320                 };
1321
1322                 i2c4 {
1323                         i2c4_xfer: i2c4-xfer {
1324                                 rockchip,pins =
1325                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1326                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1327                         };
1328                 };
1329
1330                 i2c5 {
1331                         i2c5_xfer: i2c5-xfer {
1332                                 rockchip,pins =
1333                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1334                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1335                         };
1336                 };
1337
1338                 i2c6 {
1339                         i2c6_xfer: i2c6-xfer {
1340                                 rockchip,pins =
1341                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1342                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1343                         };
1344                 };
1345
1346                 i2c7 {
1347                         i2c7_xfer: i2c7-xfer {
1348                                 rockchip,pins =
1349                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1350                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1351                         };
1352                 };
1353
1354                 i2c8 {
1355                         i2c8_xfer: i2c8-xfer {
1356                                 rockchip,pins =
1357                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1358                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1359                         };
1360                 };
1361
1362                 i2s0 {
1363                         i2s0_8ch_bus: i2s0-8ch-bus {
1364                                 rockchip,pins =
1365                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1366                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1367                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1368                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1369                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1370                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1371                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1372                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1373                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1374                         };
1375                 };
1376
1377                 i2s1 {
1378                         i2s1_2ch_bus: i2s1-2ch-bus {
1379                                 rockchip,pins =
1380                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1381                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1382                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1383                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1384                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1385                         };
1386                 };
1387
1388                 sleep {
1389                         ap_pwroff: ap-pwroff {
1390                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1391                         };
1392
1393                         ddrio_pwroff: ddrio-pwroff {
1394                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1395                         };
1396                 };
1397
1398                 spdif {
1399                         spdif_bus: spdif-bus {
1400                                 rockchip,pins =
1401                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1402                         };
1403                 };
1404
1405                 spi0 {
1406                         spi0_clk: spi0-clk {
1407                                 rockchip,pins =
1408                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1409                         };
1410                         spi0_cs0: spi0-cs0 {
1411                                 rockchip,pins =
1412                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1413                         };
1414                         spi0_cs1: spi0-cs1 {
1415                                 rockchip,pins =
1416                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1417                         };
1418                         spi0_tx: spi0-tx {
1419                                 rockchip,pins =
1420                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1421                         };
1422                         spi0_rx: spi0-rx {
1423                                 rockchip,pins =
1424                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1425                         };
1426                 };
1427
1428                 spi1 {
1429                         spi1_clk: spi1-clk {
1430                                 rockchip,pins =
1431                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1432                         };
1433                         spi1_cs0: spi1-cs0 {
1434                                 rockchip,pins =
1435                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1436                         };
1437                         spi1_rx: spi1-rx {
1438                                 rockchip,pins =
1439                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1440                         };
1441                         spi1_tx: spi1-tx {
1442                                 rockchip,pins =
1443                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1444                         };
1445                 };
1446
1447                 spi2 {
1448                         spi2_clk: spi2-clk {
1449                                 rockchip,pins =
1450                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1451                         };
1452                         spi2_cs0: spi2-cs0 {
1453                                 rockchip,pins =
1454                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1455                         };
1456                         spi2_rx: spi2-rx {
1457                                 rockchip,pins =
1458                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1459                         };
1460                         spi2_tx: spi2-tx {
1461                                 rockchip,pins =
1462                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1463                         };
1464                 };
1465
1466                 spi3 {
1467                         spi3_clk: spi3-clk {
1468                                 rockchip,pins =
1469                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1470                         };
1471                         spi3_cs0: spi3-cs0 {
1472                                 rockchip,pins =
1473                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1474                         };
1475                         spi3_rx: spi3-rx {
1476                                 rockchip,pins =
1477                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1478                         };
1479                         spi3_tx: spi3-tx {
1480                                 rockchip,pins =
1481                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1482                         };
1483                 };
1484
1485                 spi4 {
1486                         spi4_clk: spi4-clk {
1487                                 rockchip,pins =
1488                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1489                         };
1490                         spi4_cs0: spi4-cs0 {
1491                                 rockchip,pins =
1492                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1493                         };
1494                         spi4_rx: spi4-rx {
1495                                 rockchip,pins =
1496                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1497                         };
1498                         spi4_tx: spi4-tx {
1499                                 rockchip,pins =
1500                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1501                         };
1502                 };
1503
1504                 spi5 {
1505                         spi5_clk: spi5-clk {
1506                                 rockchip,pins =
1507                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1508                         };
1509                         spi5_cs0: spi5-cs0 {
1510                                 rockchip,pins =
1511                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1512                         };
1513                         spi5_rx: spi5-rx {
1514                                 rockchip,pins =
1515                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1516                         };
1517                         spi5_tx: spi5-tx {
1518                                 rockchip,pins =
1519                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1520                         };
1521                 };
1522
1523                 tsadc {
1524                         otp_gpio: otp-gpio {
1525                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1526                         };
1527
1528                         otp_out: otp-out {
1529                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1530                         };
1531                 };
1532
1533                 uart0 {
1534                         uart0_xfer: uart0-xfer {
1535                                 rockchip,pins =
1536                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1537                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1538                         };
1539
1540                         uart0_cts: uart0-cts {
1541                                 rockchip,pins =
1542                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1543                         };
1544
1545                         uart0_rts: uart0-rts {
1546                                 rockchip,pins =
1547                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1548                         };
1549                 };
1550
1551                 uart1 {
1552                         uart1_xfer: uart1-xfer {
1553                                 rockchip,pins =
1554                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1555                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1556                         };
1557                 };
1558
1559                 uart2a {
1560                         uart2a_xfer: uart2a-xfer {
1561                                 rockchip,pins =
1562                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1563                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1564                         };
1565                 };
1566
1567                 uart2b {
1568                         uart2b_xfer: uart2b-xfer {
1569                                 rockchip,pins =
1570                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1571                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1572                         };
1573                 };
1574
1575                 uart2c {
1576                         uart2c_xfer: uart2c-xfer {
1577                                 rockchip,pins =
1578                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1579                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1580                         };
1581                 };
1582
1583                 uart3 {
1584                         uart3_xfer: uart3-xfer {
1585                                 rockchip,pins =
1586                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1587                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1588                         };
1589
1590                         uart3_cts: uart3-cts {
1591                                 rockchip,pins =
1592                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1593                         };
1594
1595                         uart3_rts: uart3-rts {
1596                                 rockchip,pins =
1597                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1598                         };
1599                 };
1600
1601                 uart4 {
1602                         uart4_xfer: uart4-xfer {
1603                                 rockchip,pins =
1604                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1605                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1606                         };
1607                 };
1608
1609                 uarthdcp {
1610                         uarthdcp_xfer: uarthdcp-xfer {
1611                                 rockchip,pins =
1612                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1613                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1614                         };
1615                 };
1616
1617                 pwm0 {
1618                         pwm0_pin: pwm0-pin {
1619                                 rockchip,pins =
1620                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1621                         };
1622
1623                         vop0_pwm_pin: vop0-pwm-pin {
1624                                 rockchip,pins =
1625                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1626                         };
1627                 };
1628
1629                 pwm1 {
1630                         pwm1_pin: pwm1-pin {
1631                                 rockchip,pins =
1632                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1633                         };
1634
1635                         vop1_pwm_pin: vop1-pwm-pin {
1636                                 rockchip,pins =
1637                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1638                         };
1639                 };
1640
1641                 pwm2 {
1642                         pwm2_pin: pwm2-pin {
1643                                 rockchip,pins =
1644                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1645                         };
1646                 };
1647
1648                 pwm3a {
1649                         pwm3a_pin: pwm3a-pin {
1650                                 rockchip,pins =
1651                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1652                         };
1653                 };
1654
1655                 pwm3b {
1656                         pwm3b_pin: pwm3b-pin {
1657                                 rockchip,pins =
1658                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1659                         };
1660                 };
1661
1662                 pcie {
1663                         pcie_clkreqn: pci-clkreqn {
1664                                 rockchip,pins =
1665                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
1666                         };
1667
1668                         pcie_clkreqnb: pci-clkreqnb {
1669                                 rockchip,pins =
1670                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1671                         };
1672                 };
1673
1674         };
1675 };