arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 / {
  51         compatible = "rockchip,rk3399";
  52
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72         };
  73
  74         cpus {
  75                 #address-cells = <2>;
  76                 #size-cells = <0>;
  77
  78                 cpu-map {
  79                         cluster0 {
  80                                 core0 {
  81                                         cpu = <&cpu_l0>;
  82                                 };
  83                                 core1 {
  84                                         cpu = <&cpu_l1>;
  85                                 };
  86                                 core2 {
  87                                         cpu = <&cpu_l2>;
  88                                 };
  89                                 core3 {
  90                                         cpu = <&cpu_l3>;
  91                                 };
  92                         };
  93
  94                         cluster1 {
  95                                 core0 {
  96                                         cpu = <&cpu_b0>;
  97                                 };
  98                                 core1 {
  99                                         cpu = <&cpu_b1>;
 100                                 };
 101                         };
 102                 };
 103
 104                 cpu_l0: cpu@0 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a53", "arm,armv8";
 107                         reg = <0x0 0x0>;
 108                         enable-method = "psci";
 109                         #cooling-cells = <2>; /* min followed by max */
 110                         clocks = <&cru ARMCLKL>;
 111                 };
 112
 113                 cpu_l1: cpu@1 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53", "arm,armv8";
 116                         reg = <0x0 0x1>;
 117                         enable-method = "psci";
 118                         clocks = <&cru ARMCLKL>;
 119                 };
 120
 121                 cpu_l2: cpu@2 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a53", "arm,armv8";
 124                         reg = <0x0 0x2>;
 125                         enable-method = "psci";
 126                         clocks = <&cru ARMCLKL>;
 127                 };
 128
 129                 cpu_l3: cpu@3 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a53", "arm,armv8";
 132                         reg = <0x0 0x3>;
 133                         enable-method = "psci";
 134                         clocks = <&cru ARMCLKL>;
 135                 };
 136
 137                 cpu_b0: cpu@100 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a72", "arm,armv8";
 140                         reg = <0x0 0x100>;
 141                         enable-method = "psci";
 142                         #cooling-cells = <2>; /* min followed by max */
 143                         clocks = <&cru ARMCLKB>;
 144                 };
 145
 146                 cpu_b1: cpu@101 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a72", "arm,armv8";
 149                         reg = <0x0 0x101>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKB>;
 152                 };
 153         };
 154
 155         psci {
 156                 compatible = "arm,psci-1.0";
 157                 method = "smc";
 158         };
 159
 160         timer {
 161                 compatible = "arm,armv8-timer";
 162                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 163                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 164                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 165                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 166         };
 167
 168         xin24m: xin24m {
 169                 compatible = "fixed-clock";
 170                 clock-frequency = <24000000>;
 171                 clock-output-names = "xin24m";
 172                 #clock-cells = <0>;
 173         };
 174
 175         amba {
 176                 compatible = "simple-bus";
 177                 #address-cells = <2>;
 178                 #size-cells = <2>;
 179                 ranges;
 180
 181                 dmac_bus: dma-controller@ff6d0000 {
 182                         compatible = "arm,pl330", "arm,primecell";
 183                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 184                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 185                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 186                         #dma-cells = <1>;
 187                         clocks = <&cru ACLK_DMAC0_PERILP>;
 188                         clock-names = "apb_pclk";
 189                 };
 190
 191                 dmac_peri: dma-controller@ff6e0000 {
 192                         compatible = "arm,pl330", "arm,primecell";
 193                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 194                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 195                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 196                         #dma-cells = <1>;
 197                         clocks = <&cru ACLK_DMAC1_PERILP>;
 198                         clock-names = "apb_pclk";
 199                 };
 200         };
 201
 202         sdio0: dwmmc@fe310000 {
 203                 compatible = "rockchip,rk3399-dw-mshc",
 204                              "rockchip,rk3288-dw-mshc";
 205                 reg = <0x0 0xfe310000 0x0 0x4000>;
 206                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 207                 clock-freq-min-max = <400000 150000000>;
 208                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 209                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 210                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 211                 fifo-depth = <0x100>;
 212                 status = "disabled";
 213         };
 214
 215         sdmmc: dwmmc@fe320000 {
 216                 compatible = "rockchip,rk3399-dw-mshc",
 217                              "rockchip,rk3288-dw-mshc";
 218                 reg = <0x0 0xfe320000 0x0 0x4000>;
 219                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 220                 clock-freq-min-max = <400000 150000000>;
 221                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 222                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 223                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 224                 fifo-depth = <0x100>;
 225                 status = "disabled";
 226         };
 227
 228         sdhci: sdhci@fe330000 {
 229                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 230                 reg = <0x0 0xfe330000 0x0 0x10000>;
 231                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 232                 arasan,soc-ctl-syscon = <&grf>;
 233                 assigned-clocks = <&cru SCLK_EMMC>;
 234                 assigned-clock-rates = <200000000>;
 235                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 236                 clock-names = "clk_xin", "clk_ahb";
 237                 clock-output-names = "emmc_cardclock";
 238                 #clock-cells = <0>;
 239                 phys = <&emmc_phy>;
 240                 phy-names = "phy_arasan";
 241                 status = "disabled";
 242         };
 243
 244         usb_host0_ehci: usb@fe380000 {
 245                 compatible = "generic-ehci";
 246                 reg = <0x0 0xfe380000 0x0 0x20000>;
 247                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 248                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 249                 clock-names = "hclk_host0", "hclk_host0_arb";
 250                 status = "disabled";
 251         };
 252
 253         usb_host0_ohci: usb@fe3a0000 {
 254                 compatible = "generic-ohci";
 255                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 256                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 257                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 258                 clock-names = "hclk_host0", "hclk_host0_arb";
 259                 status = "disabled";
 260         };
 261
 262         usb_host1_ehci: usb@fe3c0000 {
 263                 compatible = "generic-ehci";
 264                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 265                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 266                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 267                 clock-names = "hclk_host1", "hclk_host1_arb";
 268                 status = "disabled";
 269         };
 270
 271         usb_host1_ohci: usb@fe3e0000 {
 272                 compatible = "generic-ohci";
 273                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 274                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 275                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 276                 clock-names = "hclk_host1", "hclk_host1_arb";
 277                 status = "disabled";
 278         };
 279
 280         gic: interrupt-controller@fee00000 {
 281                 compatible = "arm,gic-v3";
 282                 #interrupt-cells = <3>;
 283                 #address-cells = <2>;
 284                 #size-cells = <2>;
 285                 ranges;
 286                 interrupt-controller;
 287
 288                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 289                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 290                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 291                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 292                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 293                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 294                 its: interrupt-controller@fee20000 {
 295                         compatible = "arm,gic-v3-its";
 296                         msi-controller;
 297                         reg = <0x0 0xfee20000 0x0 0x20000>;
 298                 };
 299         };
 300
 301         i2c1: i2c@ff110000 {
 302                 compatible = "rockchip,rk3399-i2c";
 303                 reg = <0x0 0xff110000 0x0 0x1000>;
 304                 assigned-clocks = <&cru SCLK_I2C1>;
 305                 assigned-clock-rates = <200000000>;
 306                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 307                 clock-names = "i2c", "pclk";
 308                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 309                 pinctrl-names = "default";
 310                 pinctrl-0 = <&i2c1_xfer>;
 311                 #address-cells = <1>;
 312                 #size-cells = <0>;
 313                 status = "disabled";
 314         };
 315
 316         i2c2: i2c@ff120000 {
 317                 compatible = "rockchip,rk3399-i2c";
 318                 reg = <0x0 0xff120000 0x0 0x1000>;
 319                 assigned-clocks = <&cru SCLK_I2C2>;
 320                 assigned-clock-rates = <200000000>;
 321                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 322                 clock-names = "i2c", "pclk";
 323                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&i2c2_xfer>;
 326                 #address-cells = <1>;
 327                 #size-cells = <0>;
 328                 status = "disabled";
 329         };
 330
 331         i2c3: i2c@ff130000 {
 332                 compatible = "rockchip,rk3399-i2c";
 333                 reg = <0x0 0xff130000 0x0 0x1000>;
 334                 assigned-clocks = <&cru SCLK_I2C3>;
 335                 assigned-clock-rates = <200000000>;
 336                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 337                 clock-names = "i2c", "pclk";
 338                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 339                 pinctrl-names = "default";
 340                 pinctrl-0 = <&i2c3_xfer>;
 341                 #address-cells = <1>;
 342                 #size-cells = <0>;
 343                 status = "disabled";
 344         };
 345
 346         i2c5: i2c@ff140000 {
 347                 compatible = "rockchip,rk3399-i2c";
 348                 reg = <0x0 0xff140000 0x0 0x1000>;
 349                 assigned-clocks = <&cru SCLK_I2C5>;
 350                 assigned-clock-rates = <200000000>;
 351                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 352                 clock-names = "i2c", "pclk";
 353                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&i2c5_xfer>;
 356                 #address-cells = <1>;
 357                 #size-cells = <0>;
 358                 status = "disabled";
 359         };
 360
 361         i2c6: i2c@ff150000 {
 362                 compatible = "rockchip,rk3399-i2c";
 363                 reg = <0x0 0xff150000 0x0 0x1000>;
 364                 assigned-clocks = <&cru SCLK_I2C6>;
 365                 assigned-clock-rates = <200000000>;
 366                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 367                 clock-names = "i2c", "pclk";
 368                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 369                 pinctrl-names = "default";
 370                 pinctrl-0 = <&i2c6_xfer>;
 371                 #address-cells = <1>;
 372                 #size-cells = <0>;
 373                 status = "disabled";
 374         };
 375
 376         i2c7: i2c@ff160000 {
 377                 compatible = "rockchip,rk3399-i2c";
 378                 reg = <0x0 0xff160000 0x0 0x1000>;
 379                 assigned-clocks = <&cru SCLK_I2C7>;
 380                 assigned-clock-rates = <200000000>;
 381                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 382                 clock-names = "i2c", "pclk";
 383                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&i2c7_xfer>;
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 status = "disabled";
 389         };
 390
 391         uart0: serial@ff180000 {
 392                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 393                 reg = <0x0 0xff180000 0x0 0x100>;
 394                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 395                 clock-names = "baudclk", "apb_pclk";
 396                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 397                 reg-shift = <2>;
 398                 reg-io-width = <4>;
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&uart0_xfer>;
 401                 status = "disabled";
 402         };
 403
 404         uart1: serial@ff190000 {
 405                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 406                 reg = <0x0 0xff190000 0x0 0x100>;
 407                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 408                 clock-names = "baudclk", "apb_pclk";
 409                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 410                 reg-shift = <2>;
 411                 reg-io-width = <4>;
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&uart1_xfer>;
 414                 status = "disabled";
 415         };
 416
 417         uart2: serial@ff1a0000 {
 418                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 419                 reg = <0x0 0xff1a0000 0x0 0x100>;
 420                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 421                 clock-names = "baudclk", "apb_pclk";
 422                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 423                 reg-shift = <2>;
 424                 reg-io-width = <4>;
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&uart2c_xfer>;
 427                 status = "disabled";
 428         };
 429
 430         uart3: serial@ff1b0000 {
 431                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 432                 reg = <0x0 0xff1b0000 0x0 0x100>;
 433                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 434                 clock-names = "baudclk", "apb_pclk";
 435                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 436                 reg-shift = <2>;
 437                 reg-io-width = <4>;
 438                 pinctrl-names = "default";
 439                 pinctrl-0 = <&uart3_xfer>;
 440                 status = "disabled";
 441         };
 442
 443         spi0: spi@ff1c0000 {
 444                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 445                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 446                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 447                 clock-names = "spiclk", "apb_pclk";
 448                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 451                 #address-cells = <1>;
 452                 #size-cells = <0>;
 453                 status = "disabled";
 454         };
 455
 456         spi1: spi@ff1d0000 {
 457                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 458                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 459                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 460                 clock-names = "spiclk", "apb_pclk";
 461                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 462                 pinctrl-names = "default";
 463                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 464                 #address-cells = <1>;
 465                 #size-cells = <0>;
 466                 status = "disabled";
 467         };
 468
 469         spi2: spi@ff1e0000 {
 470                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 471                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 472                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 473                 clock-names = "spiclk", "apb_pclk";
 474                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 477                 #address-cells = <1>;
 478                 #size-cells = <0>;
 479                 status = "disabled";
 480         };
 481
 482         spi4: spi@ff1f0000 {
 483                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 484                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 485                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 486                 clock-names = "spiclk", "apb_pclk";
 487                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 status = "disabled";
 493         };
 494
 495         spi5: spi@ff200000 {
 496                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 497                 reg = <0x0 0xff200000 0x0 0x1000>;
 498                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 499                 clock-names = "spiclk", "apb_pclk";
 500                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 503                 #address-cells = <1>;
 504                 #size-cells = <0>;
 505                 status = "disabled";
 506         };
 507
 508         thermal-zones {
 509                 cpu_thermal: cpu {
 510                         polling-delay-passive = <100>;
 511                         polling-delay = <1000>;
 512
 513                         thermal-sensors = <&tsadc 0>;
 514
 515                         trips {
 516                                 cpu_alert0: cpu_alert0 {
 517                                         temperature = <70000>;
 518                                         hysteresis = <2000>;
 519                                         type = "passive";
 520                                 };
 521                                 cpu_alert1: cpu_alert1 {
 522                                         temperature = <75000>;
 523                                         hysteresis = <2000>;
 524                                         type = "passive";
 525                                 };
 526                                 cpu_crit: cpu_crit {
 527                                         temperature = <95000>;
 528                                         hysteresis = <2000>;
 529                                         type = "critical";
 530                                 };
 531                         };
 532
 533                         cooling-maps {
 534                                 map0 {
 535                                         trip = <&cpu_alert0>;
 536                                         cooling-device =
 537                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 538                                 };
 539                                 map1 {
 540                                         trip = <&cpu_alert1>;
 541                                         cooling-device =
 542                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 543                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 544                                 };
 545                         };
 546                 };
 547
 548                 gpu_thermal: gpu {
 549                         polling-delay-passive = <100>;
 550                         polling-delay = <1000>;
 551
 552                         thermal-sensors = <&tsadc 1>;
 553
 554                         trips {
 555                                 gpu_alert0: gpu_alert0 {
 556                                         temperature = <75000>;
 557                                         hysteresis = <2000>;
 558                                         type = "passive";
 559                                 };
 560                                 gpu_crit: gpu_crit {
 561                                         temperature = <95000>;
 562                                         hysteresis = <2000>;
 563                                         type = "critical";
 564                                 };
 565                         };
 566
 567                         cooling-maps {
 568                                 map0 {
 569                                         trip = <&gpu_alert0>;
 570                                         cooling-device =
 571                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 572                                 };
 573                         };
 574                 };
 575         };
 576
 577         tsadc: tsadc@ff260000 {
 578                 compatible = "rockchip,rk3399-tsadc";
 579                 reg = <0x0 0xff260000 0x0 0x100>;
 580                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 581                 assigned-clocks = <&cru SCLK_TSADC>;
 582                 assigned-clock-rates = <750000>;
 583                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 584                 clock-names = "tsadc", "apb_pclk";
 585                 resets = <&cru SRST_TSADC>;
 586                 reset-names = "tsadc-apb";
 587                 rockchip,grf = <&grf>;
 588                 rockchip,hw-tshut-temp = <95000>;
 589                 pinctrl-names = "init", "default", "sleep";
 590                 pinctrl-0 = <&otp_gpio>;
 591                 pinctrl-1 = <&otp_out>;
 592                 pinctrl-2 = <&otp_gpio>;
 593                 #thermal-sensor-cells = <1>;
 594                 status = "disabled";
 595         };
 596
 597         pmugrf: syscon@ff320000 {
 598                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 599                 reg = <0x0 0xff320000 0x0 0x1000>;
 600                 #address-cells = <1>;
 601                 #size-cells = <1>;
 602
 603                 pmu_io_domains: io-domains {
 604                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 605                         status = "disabled";
 606                 };
 607         };
 608
 609         spi3: spi@ff350000 {
 610                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 611                 reg = <0x0 0xff350000 0x0 0x1000>;
 612                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 613                 clock-names = "spiclk", "apb_pclk";
 614                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 617                 #address-cells = <1>;
 618                 #size-cells = <0>;
 619                 status = "disabled";
 620         };
 621
 622         uart4: serial@ff370000 {
 623                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 624                 reg = <0x0 0xff370000 0x0 0x100>;
 625                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 626                 clock-names = "baudclk", "apb_pclk";
 627                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 628                 reg-shift = <2>;
 629                 reg-io-width = <4>;
 630                 pinctrl-names = "default";
 631                 pinctrl-0 = <&uart4_xfer>;
 632                 status = "disabled";
 633         };
 634
 635         i2c0: i2c@ff3c0000 {
 636                 compatible = "rockchip,rk3399-i2c";
 637                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 638                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
 639                 assigned-clock-rates = <200000000>;
 640                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 641                 clock-names = "i2c", "pclk";
 642                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 643                 pinctrl-names = "default";
 644                 pinctrl-0 = <&i2c0_xfer>;
 645                 #address-cells = <1>;
 646                 #size-cells = <0>;
 647                 status = "disabled";
 648         };
 649
 650         i2c4: i2c@ff3d0000 {
 651                 compatible = "rockchip,rk3399-i2c";
 652                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 653                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
 654                 assigned-clock-rates = <200000000>;
 655                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 656                 clock-names = "i2c", "pclk";
 657                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 658                 pinctrl-names = "default";
 659                 pinctrl-0 = <&i2c4_xfer>;
 660                 #address-cells = <1>;
 661                 #size-cells = <0>;
 662                 status = "disabled";
 663         };
 664
 665         i2c8: i2c@ff3e0000 {
 666                 compatible = "rockchip,rk3399-i2c";
 667                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 668                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
 669                 assigned-clock-rates = <200000000>;
 670                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 671                 clock-names = "i2c", "pclk";
 672                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 673                 pinctrl-names = "default";
 674                 pinctrl-0 = <&i2c8_xfer>;
 675                 #address-cells = <1>;
 676                 #size-cells = <0>;
 677                 status = "disabled";
 678         };
 679
 680         pwm0: pwm@ff420000 {
 681                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 682                 reg = <0x0 0xff420000 0x0 0x10>;
 683                 #pwm-cells = <3>;
 684                 pinctrl-names = "default";
 685                 pinctrl-0 = <&pwm0_pin>;
 686                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 687                 clock-names = "pwm";
 688                 status = "disabled";
 689         };
 690
 691         pwm1: pwm@ff420010 {
 692                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 693                 reg = <0x0 0xff420010 0x0 0x10>;
 694                 #pwm-cells = <3>;
 695                 pinctrl-names = "default";
 696                 pinctrl-0 = <&pwm1_pin>;
 697                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 698                 clock-names = "pwm";
 699                 status = "disabled";
 700         };
 701
 702         pwm2: pwm@ff420020 {
 703                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 704                 reg = <0x0 0xff420020 0x0 0x10>;
 705                 #pwm-cells = <3>;
 706                 pinctrl-names = "default";
 707                 pinctrl-0 = <&pwm2_pin>;
 708                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 709                 clock-names = "pwm";
 710                 status = "disabled";
 711         };
 712
 713         pwm3: pwm@ff420030 {
 714                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 715                 reg = <0x0 0xff420030 0x0 0x10>;
 716                 #pwm-cells = <3>;
 717                 pinctrl-names = "default";
 718                 pinctrl-0 = <&pwm3a_pin>;
 719                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 720                 clock-names = "pwm";
 721                 status = "disabled";
 722         };
 723
 724         pmucru: pmu-clock-controller@ff750000 {
 725                 compatible = "rockchip,rk3399-pmucru";
 726                 reg = <0x0 0xff750000 0x0 0x1000>;
 727                 #clock-cells = <1>;
 728                 #reset-cells = <1>;
 729                 assigned-clocks = <&pmucru PLL_PPLL>;
 730                 assigned-clock-rates = <676000000>;
 731         };
 732
 733         cru: clock-controller@ff760000 {
 734                 compatible = "rockchip,rk3399-cru";
 735                 reg = <0x0 0xff760000 0x0 0x1000>;
 736                 #clock-cells = <1>;
 737                 #reset-cells = <1>;
 738                 assigned-clocks =
 739                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 740                         <&cru PLL_NPLL>,
 741                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 742                         <&cru PCLK_PERIHP>,
 743                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 744                         <&cru PCLK_PERILP0>,
 745                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 746                 assigned-clock-rates =
 747                          <594000000>,  <800000000>,
 748                         <1000000000>,
 749                          <150000000>,   <75000000>,
 750                           <37500000>,
 751                          <100000000>,  <100000000>,
 752                           <50000000>,
 753                          <100000000>,   <50000000>;
 754         };
 755
 756         grf: syscon@ff770000 {
 757                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
 758                 reg = <0x0 0xff770000 0x0 0x10000>;
 759                 #address-cells = <1>;
 760                 #size-cells = <1>;
 761
 762                 io_domains: io-domains {
 763                         compatible = "rockchip,rk3399-io-voltage-domain";
 764                         status = "disabled";
 765                 };
 766
 767                 emmc_phy: phy@f780 {
 768                         compatible = "rockchip,rk3399-emmc-phy";
 769                         reg = <0xf780 0x24>;
 770                         clocks = <&sdhci>;
 771                         clock-names = "emmcclk";
 772                         #phy-cells = <0>;
 773                         status = "disabled";
 774                 };
 775         };
 776
 777         watchdog@ff840000 {
 778                 compatible = "snps,dw-wdt";
 779                 reg = <0x0 0xff840000 0x0 0x100>;
 780                 clocks = <&cru PCLK_WDT>;
 781                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 782         };
 783
 784         rktimer: rktimer@ff850000 {
 785                 compatible = "rockchip,rk3399-timer";
 786                 reg = <0x0 0xff850000 0x0 0x1000>;
 787                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 788                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
 789                 clock-names = "pclk", "timer";
 790         };
 791
 792         spdif: spdif@ff870000 {
 793                 compatible = "rockchip,rk3399-spdif";
 794                 reg = <0x0 0xff870000 0x0 0x1000>;
 795                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 796                 dmas = <&dmac_bus 7>;
 797                 dma-names = "tx";
 798                 clock-names = "mclk", "hclk";
 799                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 800                 pinctrl-names = "default";
 801                 pinctrl-0 = <&spdif_bus>;
 802                 status = "disabled";
 803         };
 804
 805         i2s0: i2s@ff880000 {
 806                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 807                 reg = <0x0 0xff880000 0x0 0x1000>;
 808                 rockchip,grf = <&grf>;
 809                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 810                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 811                 dma-names = "tx", "rx";
 812                 clock-names = "i2s_clk", "i2s_hclk";
 813                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
 814                 pinctrl-names = "default";
 815                 pinctrl-0 = <&i2s0_8ch_bus>;
 816                 status = "disabled";
 817         };
 818
 819         i2s1: i2s@ff890000 {
 820                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 821                 reg = <0x0 0xff890000 0x0 0x1000>;
 822                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 823                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 824                 dma-names = "tx", "rx";
 825                 clock-names = "i2s_clk", "i2s_hclk";
 826                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
 827                 pinctrl-names = "default";
 828                 pinctrl-0 = <&i2s1_2ch_bus>;
 829                 status = "disabled";
 830         };
 831
 832         i2s2: i2s@ff8a0000 {
 833                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 834                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 835                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 836                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 837                 dma-names = "tx", "rx";
 838                 clock-names = "i2s_clk", "i2s_hclk";
 839                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
 840                 status = "disabled";
 841         };
 842
 843         pinctrl: pinctrl {
 844                 compatible = "rockchip,rk3399-pinctrl";
 845                 rockchip,grf = <&grf>;
 846                 rockchip,pmu = <&pmugrf>;
 847                 #address-cells = <2>;
 848                 #size-cells = <2>;
 849                 ranges;
 850
 851                 gpio0: gpio0@ff720000 {
 852                         compatible = "rockchip,gpio-bank";
 853                         reg = <0x0 0xff720000 0x0 0x100>;
 854                         clocks = <&pmucru PCLK_GPIO0_PMU>;
 855                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 856
 857                         gpio-controller;
 858                         #gpio-cells = <0x2>;
 859
 860                         interrupt-controller;
 861                         #interrupt-cells = <0x2>;
 862                 };
 863
 864                 gpio1: gpio1@ff730000 {
 865                         compatible = "rockchip,gpio-bank";
 866                         reg = <0x0 0xff730000 0x0 0x100>;
 867                         clocks = <&pmucru PCLK_GPIO1_PMU>;
 868                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 869
 870                         gpio-controller;
 871                         #gpio-cells = <0x2>;
 872
 873                         interrupt-controller;
 874                         #interrupt-cells = <0x2>;
 875                 };
 876
 877                 gpio2: gpio2@ff780000 {
 878                         compatible = "rockchip,gpio-bank";
 879                         reg = <0x0 0xff780000 0x0 0x100>;
 880                         clocks = <&cru PCLK_GPIO2>;
 881                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 882
 883                         gpio-controller;
 884                         #gpio-cells = <0x2>;
 885
 886                         interrupt-controller;
 887                         #interrupt-cells = <0x2>;
 888                 };
 889
 890                 gpio3: gpio3@ff788000 {
 891                         compatible = "rockchip,gpio-bank";
 892                         reg = <0x0 0xff788000 0x0 0x100>;
 893                         clocks = <&cru PCLK_GPIO3>;
 894                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 895
 896                         gpio-controller;
 897                         #gpio-cells = <0x2>;
 898
 899                         interrupt-controller;
 900                         #interrupt-cells = <0x2>;
 901                 };
 902
 903                 gpio4: gpio4@ff790000 {
 904                         compatible = "rockchip,gpio-bank";
 905                         reg = <0x0 0xff790000 0x0 0x100>;
 906                         clocks = <&cru PCLK_GPIO4>;
 907                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 908
 909                         gpio-controller;
 910                         #gpio-cells = <0x2>;
 911
 912                         interrupt-controller;
 913                         #interrupt-cells = <0x2>;
 914                 };
 915
 916                 pcfg_pull_up: pcfg-pull-up {
 917                         bias-pull-up;
 918                 };
 919
 920                 pcfg_pull_down: pcfg-pull-down {
 921                         bias-pull-down;
 922                 };
 923
 924                 pcfg_pull_none: pcfg-pull-none {
 925                         bias-disable;
 926                 };
 927
 928                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 929                         bias-disable;
 930                         drive-strength = <12>;
 931                 };
 932
 933                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 934                         bias-pull-up;
 935                         drive-strength = <8>;
 936                 };
 937
 938                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 939                         bias-pull-down;
 940                         drive-strength = <4>;
 941                 };
 942
 943                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 944                         bias-pull-up;
 945                         drive-strength = <2>;
 946                 };
 947
 948                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 949                         bias-pull-down;
 950                         drive-strength = <12>;
 951                 };
 952
 953                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
 954                         bias-disable;
 955                         drive-strength = <13>;
 956                 };
 957
 958                 i2c0 {
 959                         i2c0_xfer: i2c0-xfer {
 960                                 rockchip,pins =
 961                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 962                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 963                         };
 964                 };
 965
 966                 i2c1 {
 967                         i2c1_xfer: i2c1-xfer {
 968                                 rockchip,pins =
 969                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 970                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 971                         };
 972                 };
 973
 974                 i2c2 {
 975                         i2c2_xfer: i2c2-xfer {
 976                                 rockchip,pins =
 977                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 978                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 979                         };
 980                 };
 981
 982                 i2c3 {
 983                         i2c3_xfer: i2c3-xfer {
 984                                 rockchip,pins =
 985                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 986                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
 987                         };
 988                 };
 989
 990                 i2c4 {
 991                         i2c4_xfer: i2c4-xfer {
 992                                 rockchip,pins =
 993                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
 994                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 995                         };
 996                 };
 997
 998                 i2c5 {
 999                         i2c5_xfer: i2c5-xfer {
1000                                 rockchip,pins =
1001                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1002                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1003                         };
1004                 };
1005
1006                 i2c6 {
1007                         i2c6_xfer: i2c6-xfer {
1008                                 rockchip,pins =
1009                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1010                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1011                         };
1012                 };
1013
1014                 i2c7 {
1015                         i2c7_xfer: i2c7-xfer {
1016                                 rockchip,pins =
1017                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1018                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1019                         };
1020                 };
1021
1022                 i2c8 {
1023                         i2c8_xfer: i2c8-xfer {
1024                                 rockchip,pins =
1025                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1026                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1027                         };
1028                 };
1029
1030                 i2s0 {
1031                         i2s0_8ch_bus: i2s0-8ch-bus {
1032                                 rockchip,pins =
1033                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1034                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1035                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1036                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1037                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1038                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1039                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1040                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1041                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1042                         };
1043                 };
1044
1045                 i2s1 {
1046                         i2s1_2ch_bus: i2s1-2ch-bus {
1047                                 rockchip,pins =
1048                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1049                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1050                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1051                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1052                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1053                         };
1054                 };
1055
1056                 sleep {
1057                         ap_pwroff: ap-pwroff {
1058                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1059                         };
1060
1061                         ddrio_pwroff: ddrio-pwroff {
1062                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1063                         };
1064                 };
1065
1066                 spdif {
1067                         spdif_bus: spdif-bus {
1068                                 rockchip,pins =
1069                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1070                         };
1071                 };
1072
1073                 spi0 {
1074                         spi0_clk: spi0-clk {
1075                                 rockchip,pins =
1076                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1077                         };
1078                         spi0_cs0: spi0-cs0 {
1079                                 rockchip,pins =
1080                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1081                         };
1082                         spi0_cs1: spi0-cs1 {
1083                                 rockchip,pins =
1084                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1085                         };
1086                         spi0_tx: spi0-tx {
1087                                 rockchip,pins =
1088                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1089                         };
1090                         spi0_rx: spi0-rx {
1091                                 rockchip,pins =
1092                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1093                         };
1094                 };
1095
1096                 spi1 {
1097                         spi1_clk: spi1-clk {
1098                                 rockchip,pins =
1099                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1100                         };
1101                         spi1_cs0: spi1-cs0 {
1102                                 rockchip,pins =
1103                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1104                         };
1105                         spi1_rx: spi1-rx {
1106                                 rockchip,pins =
1107                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1108                         };
1109                         spi1_tx: spi1-tx {
1110                                 rockchip,pins =
1111                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1112                         };
1113                 };
1114
1115                 spi2 {
1116                         spi2_clk: spi2-clk {
1117                                 rockchip,pins =
1118                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1119                         };
1120                         spi2_cs0: spi2-cs0 {
1121                                 rockchip,pins =
1122                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1123                         };
1124                         spi2_rx: spi2-rx {
1125                                 rockchip,pins =
1126                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1127                         };
1128                         spi2_tx: spi2-tx {
1129                                 rockchip,pins =
1130                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1131                         };
1132                 };
1133
1134                 spi3 {
1135                         spi3_clk: spi3-clk {
1136                                 rockchip,pins =
1137                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1138                         };
1139                         spi3_cs0: spi3-cs0 {
1140                                 rockchip,pins =
1141                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1142                         };
1143                         spi3_rx: spi3-rx {
1144                                 rockchip,pins =
1145                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1146                         };
1147                         spi3_tx: spi3-tx {
1148                                 rockchip,pins =
1149                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1150                         };
1151                 };
1152
1153                 spi4 {
1154                         spi4_clk: spi4-clk {
1155                                 rockchip,pins =
1156                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1157                         };
1158                         spi4_cs0: spi4-cs0 {
1159                                 rockchip,pins =
1160                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1161                         };
1162                         spi4_rx: spi4-rx {
1163                                 rockchip,pins =
1164                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1165                         };
1166                         spi4_tx: spi4-tx {
1167                                 rockchip,pins =
1168                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1169                         };
1170                 };
1171
1172                 spi5 {
1173                         spi5_clk: spi5-clk {
1174                                 rockchip,pins =
1175                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1176                         };
1177                         spi5_cs0: spi5-cs0 {
1178                                 rockchip,pins =
1179                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1180                         };
1181                         spi5_rx: spi5-rx {
1182                                 rockchip,pins =
1183                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1184                         };
1185                         spi5_tx: spi5-tx {
1186                                 rockchip,pins =
1187                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1188                         };
1189                 };
1190
1191                 tsadc {
1192                         otp_gpio: otp-gpio {
1193                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1194                         };
1195
1196                         otp_out: otp-out {
1197                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1198                         };
1199                 };
1200
1201                 uart0 {
1202                         uart0_xfer: uart0-xfer {
1203                                 rockchip,pins =
1204                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1205                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1206                         };
1207
1208                         uart0_cts: uart0-cts {
1209                                 rockchip,pins =
1210                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1211                         };
1212
1213                         uart0_rts: uart0-rts {
1214                                 rockchip,pins =
1215                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1216                         };
1217                 };
1218
1219                 uart1 {
1220                         uart1_xfer: uart1-xfer {
1221                                 rockchip,pins =
1222                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1223                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1224                         };
1225                 };
1226
1227                 uart2a {
1228                         uart2a_xfer: uart2a-xfer {
1229                                 rockchip,pins =
1230                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1231                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1232                         };
1233                 };
1234
1235                 uart2b {
1236                         uart2b_xfer: uart2b-xfer {
1237                                 rockchip,pins =
1238                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1239                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1240                         };
1241                 };
1242
1243                 uart2c {
1244                         uart2c_xfer: uart2c-xfer {
1245                                 rockchip,pins =
1246                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1247                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1248                         };
1249                 };
1250
1251                 uart3 {
1252                         uart3_xfer: uart3-xfer {
1253                                 rockchip,pins =
1254                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1255                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1256                         };
1257
1258                         uart3_cts: uart3-cts {
1259                                 rockchip,pins =
1260                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1261                         };
1262
1263                         uart3_rts: uart3-rts {
1264                                 rockchip,pins =
1265                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1266                         };
1267                 };
1268
1269                 uart4 {
1270                         uart4_xfer: uart4-xfer {
1271                                 rockchip,pins =
1272                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1273                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1274                         };
1275                 };
1276
1277                 uarthdcp {
1278                         uarthdcp_xfer: uarthdcp-xfer {
1279                                 rockchip,pins =
1280                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1281                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1282                         };
1283                 };
1284
1285                 pwm0 {
1286                         pwm0_pin: pwm0-pin {
1287                                 rockchip,pins =
1288                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1289                         };
1290
1291                         vop0_pwm_pin: vop0-pwm-pin {
1292                                 rockchip,pins =
1293                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1294                         };
1295                 };
1296
1297                 pwm1 {
1298                         pwm1_pin: pwm1-pin {
1299                                 rockchip,pins =
1300                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1301                         };
1302
1303                         vop1_pwm_pin: vop1-pwm-pin {
1304                                 rockchip,pins =
1305                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1306                         };
1307                 };
1308
1309                 pwm2 {
1310                         pwm2_pin: pwm2-pin {
1311                                 rockchip,pins =
1312                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1313                         };
1314                 };
1315
1316                 pwm3a {
1317                         pwm3a_pin: pwm3a-pin {
1318                                 rockchip,pins =
1319                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1320                         };
1321                 };
1322
1323                 pwm3b {
1324                         pwm3b_pin: pwm3b-pin {
1325                                 rockchip,pins =
1326                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1327                         };
1328                 };
1329         };
1330 };