arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 i2c6 = &i2c6;
  66                 i2c7 = &i2c7;
  67                 i2c8 = &i2c8;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73         };
  74
  75         cpus {
  76                 #address-cells = <2>;
  77                 #size-cells = <0>;
  78
  79                 cpu-map {
  80                         cluster0 {
  81                                 core0 {
  82                                         cpu = <&cpu_l0>;
  83                                 };
  84                                 core1 {
  85                                         cpu = <&cpu_l1>;
  86                                 };
  87                                 core2 {
  88                                         cpu = <&cpu_l2>;
  89                                 };
  90                                 core3 {
  91                                         cpu = <&cpu_l3>;
  92                                 };
  93                         };
  94
  95                         cluster1 {
  96                                 core0 {
  97                                         cpu = <&cpu_b0>;
  98                                 };
  99                                 core1 {
 100                                         cpu = <&cpu_b1>;
 101                                 };
 102                         };
 103                 };
 104
 105                 cpu_l0: cpu@0 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53", "arm,armv8";
 108                         reg = <0x0 0x0>;
 109                         enable-method = "psci";
 110                         #cooling-cells = <2>; /* min followed by max */
 111                         clocks = <&cru ARMCLKL>;
 112                 };
 113
 114                 cpu_l1: cpu@1 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a53", "arm,armv8";
 117                         reg = <0x0 0x1>;
 118                         enable-method = "psci";
 119                         clocks = <&cru ARMCLKL>;
 120                 };
 121
 122                 cpu_l2: cpu@2 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53", "arm,armv8";
 125                         reg = <0x0 0x2>;
 126                         enable-method = "psci";
 127                         clocks = <&cru ARMCLKL>;
 128                 };
 129
 130                 cpu_l3: cpu@3 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a53", "arm,armv8";
 133                         reg = <0x0 0x3>;
 134                         enable-method = "psci";
 135                         clocks = <&cru ARMCLKL>;
 136                 };
 137
 138                 cpu_b0: cpu@100 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a72", "arm,armv8";
 141                         reg = <0x0 0x100>;
 142                         enable-method = "psci";
 143                         #cooling-cells = <2>; /* min followed by max */
 144                         clocks = <&cru ARMCLKB>;
 145                 };
 146
 147                 cpu_b1: cpu@101 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72", "arm,armv8";
 150                         reg = <0x0 0x101>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKB>;
 153                 };
 154         };
 155
 156         pmu_a53 {
 157                 compatible = "arm,cortex-a53-pmu";
 158                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 159         };
 160
 161         pmu_a72 {
 162                 compatible = "arm,cortex-a72-pmu";
 163                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 164         };
 165
 166         psci {
 167                 compatible = "arm,psci-1.0";
 168                 method = "smc";
 169         };
 170
 171         timer {
 172                 compatible = "arm,armv8-timer";
 173                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 174                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 175                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 176                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 177         };
 178
 179         xin24m: xin24m {
 180                 compatible = "fixed-clock";
 181                 clock-frequency = <24000000>;
 182                 clock-output-names = "xin24m";
 183                 #clock-cells = <0>;
 184         };
 185
 186         amba {
 187                 compatible = "simple-bus";
 188                 #address-cells = <2>;
 189                 #size-cells = <2>;
 190                 ranges;
 191
 192                 dmac_bus: dma-controller@ff6d0000 {
 193                         compatible = "arm,pl330", "arm,primecell";
 194                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 195                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 196                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 197                         #dma-cells = <1>;
 198                         clocks = <&cru ACLK_DMAC0_PERILP>;
 199                         clock-names = "apb_pclk";
 200                 };
 201
 202                 dmac_peri: dma-controller@ff6e0000 {
 203                         compatible = "arm,pl330", "arm,primecell";
 204                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 205                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 206                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 207                         #dma-cells = <1>;
 208                         clocks = <&cru ACLK_DMAC1_PERILP>;
 209                         clock-names = "apb_pclk";
 210                 };
 211         };
 212
 213         sdio0: dwmmc@fe310000 {
 214                 compatible = "rockchip,rk3399-dw-mshc",
 215                              "rockchip,rk3288-dw-mshc";
 216                 reg = <0x0 0xfe310000 0x0 0x4000>;
 217                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 218                 clock-freq-min-max = <400000 150000000>;
 219                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 220                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 221                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 222                 fifo-depth = <0x100>;
 223                 status = "disabled";
 224         };
 225
 226         sdmmc: dwmmc@fe320000 {
 227                 compatible = "rockchip,rk3399-dw-mshc",
 228                              "rockchip,rk3288-dw-mshc";
 229                 reg = <0x0 0xfe320000 0x0 0x4000>;
 230                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 231                 clock-freq-min-max = <400000 150000000>;
 232                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 233                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 234                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 235                 fifo-depth = <0x100>;
 236                 status = "disabled";
 237         };
 238
 239         sdhci: sdhci@fe330000 {
 240                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 241                 reg = <0x0 0xfe330000 0x0 0x10000>;
 242                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 243                 arasan,soc-ctl-syscon = <&grf>;
 244                 assigned-clocks = <&cru SCLK_EMMC>;
 245                 assigned-clock-rates = <200000000>;
 246                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 247                 clock-names = "clk_xin", "clk_ahb";
 248                 clock-output-names = "emmc_cardclock";
 249                 #clock-cells = <0>;
 250                 phys = <&emmc_phy>;
 251                 phy-names = "phy_arasan";
 252                 status = "disabled";
 253         };
 254
 255         pcie0: pcie@f8000000 {
 256                 compatible = "rockchip,rk3399-pcie";
 257                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 258                       <0x0 0xfd000000 0x0 0x1000000>;
 259                 reg-names = "axi-base", "apb-base";
 260                 #address-cells = <3>;
 261                 #size-cells = <2>;
 262                 #interrupt-cells = <1>;
 263                 bus-range = <0x0 0x1>;
 264                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 265                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 266                 clock-names = "aclk", "aclk-perf",
 267                               "hclk", "pm";
 268                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 269                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 270                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 271                 interrupt-names = "sys", "legacy", "client";
 272                 interrupt-map-mask = <0 0 0 7>;
 273                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 274                                 <0 0 0 2 &pcie0_intc 1>,
 275                                 <0 0 0 3 &pcie0_intc 2>,
 276                                 <0 0 0 4 &pcie0_intc 3>;
 277                 msi-map = <0x0 &its 0x0 0x1000>;
 278                 phys = <&pcie_phy>;
 279                 phy-names = "pcie-phy";
 280                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
 281                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
 282                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 283                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
 284                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
 285                 status = "disabled";
 286
 287                 pcie0_intc: interrupt-controller {
 288                         interrupt-controller;
 289                         #address-cells = <0>;
 290                         #interrupt-cells = <1>;
 291                 };
 292         };
 293
 294         usb_host0_ehci: usb@fe380000 {
 295                 compatible = "generic-ehci";
 296                 reg = <0x0 0xfe380000 0x0 0x20000>;
 297                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 298                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 299                 clock-names = "hclk_host0", "hclk_host0_arb";
 300                 phys = <&u2phy0_host>;
 301                 phy-names = "usb";
 302                 status = "disabled";
 303         };
 304
 305         usb_host0_ohci: usb@fe3a0000 {
 306                 compatible = "generic-ohci";
 307                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 308                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 309                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 310                 clock-names = "hclk_host0", "hclk_host0_arb";
 311                 status = "disabled";
 312         };
 313
 314         usb_host1_ehci: usb@fe3c0000 {
 315                 compatible = "generic-ehci";
 316                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 317                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 318                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 319                 clock-names = "hclk_host1", "hclk_host1_arb";
 320                 phys = <&u2phy1_host>;
 321                 phy-names = "usb";
 322                 status = "disabled";
 323         };
 324
 325         usb_host1_ohci: usb@fe3e0000 {
 326                 compatible = "generic-ohci";
 327                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 328                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 329                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 330                 clock-names = "hclk_host1", "hclk_host1_arb";
 331                 status = "disabled";
 332         };
 333
 334         gic: interrupt-controller@fee00000 {
 335                 compatible = "arm,gic-v3";
 336                 #interrupt-cells = <4>;
 337                 #address-cells = <2>;
 338                 #size-cells = <2>;
 339                 ranges;
 340                 interrupt-controller;
 341
 342                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 343                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 344                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 345                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 346                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 347                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 348                 its: interrupt-controller@fee20000 {
 349                         compatible = "arm,gic-v3-its";
 350                         msi-controller;
 351                         reg = <0x0 0xfee20000 0x0 0x20000>;
 352                 };
 353
 354                 ppi-partitions {
 355                         ppi_cluster0: interrupt-partition-0 {
 356                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 357                         };
 358
 359                         ppi_cluster1: interrupt-partition-1 {
 360                                 affinity = <&cpu_b0 &cpu_b1>;
 361                         };
 362                 };
 363         };
 364
 365         saradc: saradc@ff100000 {
 366                 compatible = "rockchip,rk3399-saradc";
 367                 reg = <0x0 0xff100000 0x0 0x100>;
 368                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 369                 #io-channel-cells = <1>;
 370                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 371                 clock-names = "saradc", "apb_pclk";
 372                 resets = <&cru SRST_P_SARADC>;
 373                 reset-names = "saradc-apb";
 374                 status = "disabled";
 375         };
 376
 377         i2c1: i2c@ff110000 {
 378                 compatible = "rockchip,rk3399-i2c";
 379                 reg = <0x0 0xff110000 0x0 0x1000>;
 380                 assigned-clocks = <&cru SCLK_I2C1>;
 381                 assigned-clock-rates = <200000000>;
 382                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 383                 clock-names = "i2c", "pclk";
 384                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&i2c1_xfer>;
 387                 #address-cells = <1>;
 388                 #size-cells = <0>;
 389                 status = "disabled";
 390         };
 391
 392         i2c2: i2c@ff120000 {
 393                 compatible = "rockchip,rk3399-i2c";
 394                 reg = <0x0 0xff120000 0x0 0x1000>;
 395                 assigned-clocks = <&cru SCLK_I2C2>;
 396                 assigned-clock-rates = <200000000>;
 397                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 398                 clock-names = "i2c", "pclk";
 399                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 400                 pinctrl-names = "default";
 401                 pinctrl-0 = <&i2c2_xfer>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 status = "disabled";
 405         };
 406
 407         i2c3: i2c@ff130000 {
 408                 compatible = "rockchip,rk3399-i2c";
 409                 reg = <0x0 0xff130000 0x0 0x1000>;
 410                 assigned-clocks = <&cru SCLK_I2C3>;
 411                 assigned-clock-rates = <200000000>;
 412                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 413                 clock-names = "i2c", "pclk";
 414                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 415                 pinctrl-names = "default";
 416                 pinctrl-0 = <&i2c3_xfer>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 status = "disabled";
 420         };
 421
 422         i2c5: i2c@ff140000 {
 423                 compatible = "rockchip,rk3399-i2c";
 424                 reg = <0x0 0xff140000 0x0 0x1000>;
 425                 assigned-clocks = <&cru SCLK_I2C5>;
 426                 assigned-clock-rates = <200000000>;
 427                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 428                 clock-names = "i2c", "pclk";
 429                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 430                 pinctrl-names = "default";
 431                 pinctrl-0 = <&i2c5_xfer>;
 432                 #address-cells = <1>;
 433                 #size-cells = <0>;
 434                 status = "disabled";
 435         };
 436
 437         i2c6: i2c@ff150000 {
 438                 compatible = "rockchip,rk3399-i2c";
 439                 reg = <0x0 0xff150000 0x0 0x1000>;
 440                 assigned-clocks = <&cru SCLK_I2C6>;
 441                 assigned-clock-rates = <200000000>;
 442                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 443                 clock-names = "i2c", "pclk";
 444                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&i2c6_xfer>;
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 status = "disabled";
 450         };
 451
 452         i2c7: i2c@ff160000 {
 453                 compatible = "rockchip,rk3399-i2c";
 454                 reg = <0x0 0xff160000 0x0 0x1000>;
 455                 assigned-clocks = <&cru SCLK_I2C7>;
 456                 assigned-clock-rates = <200000000>;
 457                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 458                 clock-names = "i2c", "pclk";
 459                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&i2c7_xfer>;
 462                 #address-cells = <1>;
 463                 #size-cells = <0>;
 464                 status = "disabled";
 465         };
 466
 467         uart0: serial@ff180000 {
 468                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 469                 reg = <0x0 0xff180000 0x0 0x100>;
 470                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 471                 clock-names = "baudclk", "apb_pclk";
 472                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 473                 reg-shift = <2>;
 474                 reg-io-width = <4>;
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&uart0_xfer>;
 477                 status = "disabled";
 478         };
 479
 480         uart1: serial@ff190000 {
 481                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 482                 reg = <0x0 0xff190000 0x0 0x100>;
 483                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 484                 clock-names = "baudclk", "apb_pclk";
 485                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 486                 reg-shift = <2>;
 487                 reg-io-width = <4>;
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&uart1_xfer>;
 490                 status = "disabled";
 491         };
 492
 493         uart2: serial@ff1a0000 {
 494                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 495                 reg = <0x0 0xff1a0000 0x0 0x100>;
 496                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 497                 clock-names = "baudclk", "apb_pclk";
 498                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 499                 reg-shift = <2>;
 500                 reg-io-width = <4>;
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&uart2c_xfer>;
 503                 status = "disabled";
 504         };
 505
 506         uart3: serial@ff1b0000 {
 507                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 508                 reg = <0x0 0xff1b0000 0x0 0x100>;
 509                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 510                 clock-names = "baudclk", "apb_pclk";
 511                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 512                 reg-shift = <2>;
 513                 reg-io-width = <4>;
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&uart3_xfer>;
 516                 status = "disabled";
 517         };
 518
 519         spi0: spi@ff1c0000 {
 520                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 521                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 522                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 523                 clock-names = "spiclk", "apb_pclk";
 524                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 525                 pinctrl-names = "default";
 526                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 status = "disabled";
 530         };
 531
 532         spi1: spi@ff1d0000 {
 533                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 534                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 535                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 536                 clock-names = "spiclk", "apb_pclk";
 537                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 status = "disabled";
 543         };
 544
 545         spi2: spi@ff1e0000 {
 546                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 547                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 548                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 549                 clock-names = "spiclk", "apb_pclk";
 550                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 status = "disabled";
 556         };
 557
 558         spi4: spi@ff1f0000 {
 559                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 560                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 561                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 562                 clock-names = "spiclk", "apb_pclk";
 563                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 566                 #address-cells = <1>;
 567                 #size-cells = <0>;
 568                 status = "disabled";
 569         };
 570
 571         spi5: spi@ff200000 {
 572                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 573                 reg = <0x0 0xff200000 0x0 0x1000>;
 574                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 575                 clock-names = "spiclk", "apb_pclk";
 576                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 577                 pinctrl-names = "default";
 578                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 579                 #address-cells = <1>;
 580                 #size-cells = <0>;
 581                 status = "disabled";
 582         };
 583
 584         thermal-zones {
 585                 cpu_thermal: cpu {
 586                         polling-delay-passive = <100>;
 587                         polling-delay = <1000>;
 588
 589                         thermal-sensors = <&tsadc 0>;
 590
 591                         trips {
 592                                 cpu_alert0: cpu_alert0 {
 593                                         temperature = <70000>;
 594                                         hysteresis = <2000>;
 595                                         type = "passive";
 596                                 };
 597                                 cpu_alert1: cpu_alert1 {
 598                                         temperature = <75000>;
 599                                         hysteresis = <2000>;
 600                                         type = "passive";
 601                                 };
 602                                 cpu_crit: cpu_crit {
 603                                         temperature = <95000>;
 604                                         hysteresis = <2000>;
 605                                         type = "critical";
 606                                 };
 607                         };
 608
 609                         cooling-maps {
 610                                 map0 {
 611                                         trip = <&cpu_alert0>;
 612                                         cooling-device =
 613                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 614                                 };
 615                                 map1 {
 616                                         trip = <&cpu_alert1>;
 617                                         cooling-device =
 618                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 619                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 620                                 };
 621                         };
 622                 };
 623
 624                 gpu_thermal: gpu {
 625                         polling-delay-passive = <100>;
 626                         polling-delay = <1000>;
 627
 628                         thermal-sensors = <&tsadc 1>;
 629
 630                         trips {
 631                                 gpu_alert0: gpu_alert0 {
 632                                         temperature = <75000>;
 633                                         hysteresis = <2000>;
 634                                         type = "passive";
 635                                 };
 636                                 gpu_crit: gpu_crit {
 637                                         temperature = <95000>;
 638                                         hysteresis = <2000>;
 639                                         type = "critical";
 640                                 };
 641                         };
 642
 643                         cooling-maps {
 644                                 map0 {
 645                                         trip = <&gpu_alert0>;
 646                                         cooling-device =
 647                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 648                                 };
 649                         };
 650                 };
 651         };
 652
 653         tsadc: tsadc@ff260000 {
 654                 compatible = "rockchip,rk3399-tsadc";
 655                 reg = <0x0 0xff260000 0x0 0x100>;
 656                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 657                 assigned-clocks = <&cru SCLK_TSADC>;
 658                 assigned-clock-rates = <750000>;
 659                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 660                 clock-names = "tsadc", "apb_pclk";
 661                 resets = <&cru SRST_TSADC>;
 662                 reset-names = "tsadc-apb";
 663                 rockchip,grf = <&grf>;
 664                 rockchip,hw-tshut-temp = <95000>;
 665                 pinctrl-names = "init", "default", "sleep";
 666                 pinctrl-0 = <&otp_gpio>;
 667                 pinctrl-1 = <&otp_out>;
 668                 pinctrl-2 = <&otp_gpio>;
 669                 #thermal-sensor-cells = <1>;
 670                 status = "disabled";
 671         };
 672
 673         qos_gmac: qos@ffa5c000 {
 674                 compatible = "syscon";
 675                 reg = <0x0 0xffa5c000 0x0 0x20>;
 676         };
 677
 678         qos_hdcp: qos@ffa90000 {
 679                 compatible = "syscon";
 680                 reg = <0x0 0xffa90000 0x0 0x20>;
 681         };
 682
 683         qos_iep: qos@ffa98000 {
 684                 compatible = "syscon";
 685                 reg = <0x0 0xffa98000 0x0 0x20>;
 686         };
 687
 688         qos_isp0_m0: qos@ffaa0000 {
 689                 compatible = "syscon";
 690                 reg = <0x0 0xffaa0000 0x0 0x20>;
 691         };
 692
 693         qos_isp0_m1: qos@ffaa0080 {
 694                 compatible = "syscon";
 695                 reg = <0x0 0xffaa0080 0x0 0x20>;
 696         };
 697
 698         qos_isp1_m0: qos@ffaa8000 {
 699                 compatible = "syscon";
 700                 reg = <0x0 0xffaa8000 0x0 0x20>;
 701         };
 702
 703         qos_isp1_m1: qos@ffaa8080 {
 704                 compatible = "syscon";
 705                 reg = <0x0 0xffaa8080 0x0 0x20>;
 706         };
 707
 708         qos_rga_r: qos@ffab0000 {
 709                 compatible = "syscon";
 710                 reg = <0x0 0xffab0000 0x0 0x20>;
 711         };
 712
 713         qos_rga_w: qos@ffab0080 {
 714                 compatible = "syscon";
 715                 reg = <0x0 0xffab0080 0x0 0x20>;
 716         };
 717
 718         qos_video_m0: qos@ffab8000 {
 719                 compatible = "syscon";
 720                 reg = <0x0 0xffab8000 0x0 0x20>;
 721         };
 722
 723         qos_video_m1_r: qos@ffac0000 {
 724                 compatible = "syscon";
 725                 reg = <0x0 0xffac0000 0x0 0x20>;
 726         };
 727
 728         qos_video_m1_w: qos@ffac0080 {
 729                 compatible = "syscon";
 730                 reg = <0x0 0xffac0080 0x0 0x20>;
 731         };
 732
 733         qos_vop_big_r: qos@ffac8000 {
 734                 compatible = "syscon";
 735                 reg = <0x0 0xffac8000 0x0 0x20>;
 736         };
 737
 738         qos_vop_big_w: qos@ffac8080 {
 739                 compatible = "syscon";
 740                 reg = <0x0 0xffac8080 0x0 0x20>;
 741         };
 742
 743         qos_vop_little: qos@ffad0000 {
 744                 compatible = "syscon";
 745                 reg = <0x0 0xffad0000 0x0 0x20>;
 746         };
 747
 748         qos_gpu: qos@ffae0000 {
 749                 compatible = "syscon";
 750                 reg = <0x0 0xffae0000 0x0 0x20>;
 751         };
 752
 753         pmu: power-management@ff310000 {
 754                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 755                 reg = <0x0 0xff310000 0x0 0x1000>;
 756
 757                 /*
 758                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 759                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 760                  * Some of the power domains are grouped together for every
 761                  * voltage domain.
 762                  * The detail contents as below.
 763                  */
 764                 power: power-controller {
 765                         compatible = "rockchip,rk3399-power-controller";
 766                         #power-domain-cells = <1>;
 767                         #address-cells = <1>;
 768                         #size-cells = <0>;
 769
 770                         /* These power domains are grouped by VD_CENTER */
 771                         pd_iep@RK3399_PD_IEP {
 772                                 reg = <RK3399_PD_IEP>;
 773                                 clocks = <&cru ACLK_IEP>,
 774                                          <&cru HCLK_IEP>;
 775                                 pm_qos = <&qos_iep>;
 776                         };
 777                         pd_rga@RK3399_PD_RGA {
 778                                 reg = <RK3399_PD_RGA>;
 779                                 clocks = <&cru ACLK_RGA>,
 780                                          <&cru HCLK_RGA>;
 781                                 pm_qos = <&qos_rga_r>,
 782                                          <&qos_rga_w>;
 783                         };
 784                         pd_vcodec@RK3399_PD_VCODEC {
 785                                 reg = <RK3399_PD_VCODEC>;
 786                                 clocks = <&cru ACLK_VCODEC>,
 787                                          <&cru HCLK_VCODEC>;
 788                                 pm_qos = <&qos_video_m0>;
 789                         };
 790                         pd_vdu@RK3399_PD_VDU {
 791                                 reg = <RK3399_PD_VDU>;
 792                                 clocks = <&cru ACLK_VDU>,
 793                                          <&cru HCLK_VDU>;
 794                                 pm_qos = <&qos_video_m1_r>,
 795                                          <&qos_video_m1_w>;
 796                         };
 797
 798                         /* These power domains are grouped by VD_GPU */
 799                         pd_gpu@RK3399_PD_GPU {
 800                                 reg = <RK3399_PD_GPU>;
 801                                 clocks = <&cru ACLK_GPU>;
 802                                 pm_qos = <&qos_gpu>;
 803                         };
 804
 805                         /* These power domains are grouped by VD_LOGIC */
 806                         pd_gmac@RK3399_PD_GMAC {
 807                                 reg = <RK3399_PD_GMAC>;
 808                                 clocks = <&cru ACLK_GMAC>;
 809                                 pm_qos = <&qos_gmac>;
 810                         };
 811                         pd_vio@RK3399_PD_VIO {
 812                                 reg = <RK3399_PD_VIO>;
 813                                 #address-cells = <1>;
 814                                 #size-cells = <0>;
 815
 816                                 pd_hdcp@RK3399_PD_HDCP {
 817                                         reg = <RK3399_PD_HDCP>;
 818                                         clocks = <&cru ACLK_HDCP>,
 819                                                  <&cru HCLK_HDCP>,
 820                                                  <&cru PCLK_HDCP>;
 821                                         pm_qos = <&qos_hdcp>;
 822                                 };
 823                                 pd_isp0@RK3399_PD_ISP0 {
 824                                         reg = <RK3399_PD_ISP0>;
 825                                         clocks = <&cru ACLK_ISP0>,
 826                                                  <&cru HCLK_ISP0>;
 827                                         pm_qos = <&qos_isp0_m0>,
 828                                                  <&qos_isp0_m1>;
 829                                 };
 830                                 pd_isp1@RK3399_PD_ISP1 {
 831                                         reg = <RK3399_PD_ISP1>;
 832                                         clocks = <&cru ACLK_ISP1>,
 833                                                  <&cru HCLK_ISP1>;
 834                                         pm_qos = <&qos_isp1_m0>,
 835                                                  <&qos_isp1_m1>;
 836                                 };
 837                                 pd_tcpc0@RK3399_PD_TCPC0 {
 838                                         reg = <RK3399_PD_TCPD0>;
 839                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
 840                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
 841                                 };
 842                                 pd_tcpc1@RK3399_PD_TCPC1 {
 843                                         reg = <RK3399_PD_TCPD1>;
 844                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
 845                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
 846                                 };
 847                                 pd_vo@RK3399_PD_VO {
 848                                         reg = <RK3399_PD_VO>;
 849                                         #address-cells = <1>;
 850                                         #size-cells = <0>;
 851
 852                                         pd_vopb@RK3399_PD_VOPB {
 853                                                 reg = <RK3399_PD_VOPB>;
 854                                                 clocks = <&cru ACLK_VOP0>,
 855                                                          <&cru HCLK_VOP0>;
 856                                                 pm_qos = <&qos_vop_big_r>,
 857                                                          <&qos_vop_big_w>;
 858                                         };
 859                                         pd_vopl@RK3399_PD_VOPL {
 860                                                 reg = <RK3399_PD_VOPL>;
 861                                                 clocks = <&cru ACLK_VOP1>,
 862                                                          <&cru HCLK_VOP1>;
 863                                                 pm_qos = <&qos_vop_little>;
 864                                         };
 865                                 };
 866                         };
 867                 };
 868         };
 869
 870         pmugrf: syscon@ff320000 {
 871                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 872                 reg = <0x0 0xff320000 0x0 0x1000>;
 873                 #address-cells = <1>;
 874                 #size-cells = <1>;
 875
 876                 pmu_io_domains: io-domains {
 877                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 878                         status = "disabled";
 879                 };
 880         };
 881
 882         spi3: spi@ff350000 {
 883                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 884                 reg = <0x0 0xff350000 0x0 0x1000>;
 885                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 886                 clock-names = "spiclk", "apb_pclk";
 887                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
 888                 pinctrl-names = "default";
 889                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 890                 #address-cells = <1>;
 891                 #size-cells = <0>;
 892                 status = "disabled";
 893         };
 894
 895         uart4: serial@ff370000 {
 896                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 897                 reg = <0x0 0xff370000 0x0 0x100>;
 898                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 899                 clock-names = "baudclk", "apb_pclk";
 900                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
 901                 reg-shift = <2>;
 902                 reg-io-width = <4>;
 903                 pinctrl-names = "default";
 904                 pinctrl-0 = <&uart4_xfer>;
 905                 status = "disabled";
 906         };
 907
 908         i2c0: i2c@ff3c0000 {
 909                 compatible = "rockchip,rk3399-i2c";
 910                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 911                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
 912                 assigned-clock-rates = <200000000>;
 913                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 914                 clock-names = "i2c", "pclk";
 915                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 916                 pinctrl-names = "default";
 917                 pinctrl-0 = <&i2c0_xfer>;
 918                 #address-cells = <1>;
 919                 #size-cells = <0>;
 920                 status = "disabled";
 921         };
 922
 923         i2c4: i2c@ff3d0000 {
 924                 compatible = "rockchip,rk3399-i2c";
 925                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 926                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
 927                 assigned-clock-rates = <200000000>;
 928                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 929                 clock-names = "i2c", "pclk";
 930                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
 931                 pinctrl-names = "default";
 932                 pinctrl-0 = <&i2c4_xfer>;
 933                 #address-cells = <1>;
 934                 #size-cells = <0>;
 935                 status = "disabled";
 936         };
 937
 938         i2c8: i2c@ff3e0000 {
 939                 compatible = "rockchip,rk3399-i2c";
 940                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 941                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
 942                 assigned-clock-rates = <200000000>;
 943                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 944                 clock-names = "i2c", "pclk";
 945                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
 946                 pinctrl-names = "default";
 947                 pinctrl-0 = <&i2c8_xfer>;
 948                 #address-cells = <1>;
 949                 #size-cells = <0>;
 950                 status = "disabled";
 951         };
 952
 953         pwm0: pwm@ff420000 {
 954                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 955                 reg = <0x0 0xff420000 0x0 0x10>;
 956                 #pwm-cells = <3>;
 957                 pinctrl-names = "default";
 958                 pinctrl-0 = <&pwm0_pin>;
 959                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 960                 clock-names = "pwm";
 961                 status = "disabled";
 962         };
 963
 964         pwm1: pwm@ff420010 {
 965                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 966                 reg = <0x0 0xff420010 0x0 0x10>;
 967                 #pwm-cells = <3>;
 968                 pinctrl-names = "default";
 969                 pinctrl-0 = <&pwm1_pin>;
 970                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 971                 clock-names = "pwm";
 972                 status = "disabled";
 973         };
 974
 975         pwm2: pwm@ff420020 {
 976                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 977                 reg = <0x0 0xff420020 0x0 0x10>;
 978                 #pwm-cells = <3>;
 979                 pinctrl-names = "default";
 980                 pinctrl-0 = <&pwm2_pin>;
 981                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 982                 clock-names = "pwm";
 983                 status = "disabled";
 984         };
 985
 986         pwm3: pwm@ff420030 {
 987                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 988                 reg = <0x0 0xff420030 0x0 0x10>;
 989                 #pwm-cells = <3>;
 990                 pinctrl-names = "default";
 991                 pinctrl-0 = <&pwm3a_pin>;
 992                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 993                 clock-names = "pwm";
 994                 status = "disabled";
 995         };
 996
 997         efuse0: efuse@ff690000 {
 998                 compatible = "rockchip,rk3399-efuse";
 999                 reg = <0x0 0xff690000 0x0 0x80>;
1000                 #address-cells = <1>;
1001                 #size-cells = <1>;
1002                 clocks = <&cru PCLK_EFUSE1024NS>;
1003                 clock-names = "pclk_efuse";
1004
1005                 /* Data cells */
1006                 cpub_leakage: cpu-leakage@17 {
1007                         reg = <0x17 0x1>;
1008                 };
1009                 gpu_leakage: gpu-leakage@18 {
1010                         reg = <0x18 0x1>;
1011                 };
1012                 center_leakage: center-leakage@19 {
1013                         reg = <0x19 0x1>;
1014                 };
1015                 cpul_leakage: cpu-leakage@1a {
1016                         reg = <0x1a 0x1>;
1017                 };
1018                 logic_leakage: logic-leakage@1b {
1019                         reg = <0x1b 0x1>;
1020                 };
1021                 wafer_info: wafer-info@1c {
1022                         reg = <0x1c 0x1>;
1023                 };
1024         };
1025
1026         pmucru: pmu-clock-controller@ff750000 {
1027                 compatible = "rockchip,rk3399-pmucru";
1028                 reg = <0x0 0xff750000 0x0 0x1000>;
1029                 #clock-cells = <1>;
1030                 #reset-cells = <1>;
1031                 assigned-clocks = <&pmucru PLL_PPLL>;
1032                 assigned-clock-rates = <676000000>;
1033         };
1034
1035         cru: clock-controller@ff760000 {
1036                 compatible = "rockchip,rk3399-cru";
1037                 reg = <0x0 0xff760000 0x0 0x1000>;
1038                 #clock-cells = <1>;
1039                 #reset-cells = <1>;
1040                 assigned-clocks =
1041                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1042                         <&cru PLL_NPLL>,
1043                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1044                         <&cru PCLK_PERIHP>,
1045                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1046                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1047                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1048                 assigned-clock-rates =
1049                          <594000000>,  <800000000>,
1050                         <1000000000>,
1051                          <150000000>,   <75000000>,
1052                           <37500000>,
1053                          <100000000>,  <100000000>,
1054                           <50000000>, <600000000>,
1055                          <100000000>,   <50000000>;
1056         };
1057
1058         grf: syscon@ff770000 {
1059                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1060                 reg = <0x0 0xff770000 0x0 0x10000>;
1061                 #address-cells = <1>;
1062                 #size-cells = <1>;
1063
1064                 io_domains: io-domains {
1065                         compatible = "rockchip,rk3399-io-voltage-domain";
1066                         status = "disabled";
1067                 };
1068
1069                 u2phy0: usb2-phy@e450 {
1070                         compatible = "rockchip,rk3399-usb2phy";
1071                         reg = <0xe450 0x10>;
1072                         clocks = <&cru SCLK_USB2PHY0_REF>;
1073                         clock-names = "phyclk";
1074                         #clock-cells = <0>;
1075                         clock-output-names = "clk_usbphy0_480m";
1076                         status = "disabled";
1077
1078                         u2phy0_host: host-port {
1079                                 #phy-cells = <0>;
1080                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1081                                 interrupt-names = "linestate";
1082                                 status = "disabled";
1083                         };
1084                 };
1085
1086                 u2phy1: usb2-phy@e460 {
1087                         compatible = "rockchip,rk3399-usb2phy";
1088                         reg = <0xe460 0x10>;
1089                         clocks = <&cru SCLK_USB2PHY1_REF>;
1090                         clock-names = "phyclk";
1091                         #clock-cells = <0>;
1092                         clock-output-names = "clk_usbphy1_480m";
1093                         status = "disabled";
1094
1095                         u2phy1_host: host-port {
1096                                 #phy-cells = <0>;
1097                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1098                                 interrupt-names = "linestate";
1099                                 status = "disabled";
1100                         };
1101                 };
1102
1103                 emmc_phy: phy@f780 {
1104                         compatible = "rockchip,rk3399-emmc-phy";
1105                         reg = <0xf780 0x24>;
1106                         clocks = <&sdhci>;
1107                         clock-names = "emmcclk";
1108                         #phy-cells = <0>;
1109                         status = "disabled";
1110                 };
1111
1112                 pcie_phy: pcie-phy {
1113                         compatible = "rockchip,rk3399-pcie-phy";
1114                         clocks = <&cru SCLK_PCIEPHY_REF>;
1115                         clock-names = "refclk";
1116                         #phy-cells = <0>;
1117                         resets = <&cru SRST_PCIEPHY>;
1118                         reset-names = "phy";
1119                         status = "disabled";
1120                 };
1121         };
1122
1123         watchdog@ff848000 {
1124                 compatible = "snps,dw-wdt";
1125                 reg = <0x0 0xff848000 0x0 0x100>;
1126                 clocks = <&cru PCLK_WDT>;
1127                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1128         };
1129
1130         rktimer: rktimer@ff850000 {
1131                 compatible = "rockchip,rk3399-timer";
1132                 reg = <0x0 0xff850000 0x0 0x1000>;
1133                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1134                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1135                 clock-names = "pclk", "timer";
1136         };
1137
1138         spdif: spdif@ff870000 {
1139                 compatible = "rockchip,rk3399-spdif";
1140                 reg = <0x0 0xff870000 0x0 0x1000>;
1141                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1142                 dmas = <&dmac_bus 7>;
1143                 dma-names = "tx";
1144                 clock-names = "mclk", "hclk";
1145                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1146                 pinctrl-names = "default";
1147                 pinctrl-0 = <&spdif_bus>;
1148                 status = "disabled";
1149         };
1150
1151         i2s0: i2s@ff880000 {
1152                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1153                 reg = <0x0 0xff880000 0x0 0x1000>;
1154                 rockchip,grf = <&grf>;
1155                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1156                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1157                 dma-names = "tx", "rx";
1158                 clock-names = "i2s_clk", "i2s_hclk";
1159                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1160                 pinctrl-names = "default";
1161                 pinctrl-0 = <&i2s0_8ch_bus>;
1162                 status = "disabled";
1163         };
1164
1165         i2s1: i2s@ff890000 {
1166                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1167                 reg = <0x0 0xff890000 0x0 0x1000>;
1168                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1169                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1170                 dma-names = "tx", "rx";
1171                 clock-names = "i2s_clk", "i2s_hclk";
1172                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1173                 pinctrl-names = "default";
1174                 pinctrl-0 = <&i2s1_2ch_bus>;
1175                 status = "disabled";
1176         };
1177
1178         i2s2: i2s@ff8a0000 {
1179                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1180                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1181                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1182                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1183                 dma-names = "tx", "rx";
1184                 clock-names = "i2s_clk", "i2s_hclk";
1185                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1186                 status = "disabled";
1187         };
1188
1189         pinctrl: pinctrl {
1190                 compatible = "rockchip,rk3399-pinctrl";
1191                 rockchip,grf = <&grf>;
1192                 rockchip,pmu = <&pmugrf>;
1193                 #address-cells = <2>;
1194                 #size-cells = <2>;
1195                 ranges;
1196
1197                 gpio0: gpio0@ff720000 {
1198                         compatible = "rockchip,gpio-bank";
1199                         reg = <0x0 0xff720000 0x0 0x100>;
1200                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1201                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1202
1203                         gpio-controller;
1204                         #gpio-cells = <0x2>;
1205
1206                         interrupt-controller;
1207                         #interrupt-cells = <0x2>;
1208                 };
1209
1210                 gpio1: gpio1@ff730000 {
1211                         compatible = "rockchip,gpio-bank";
1212                         reg = <0x0 0xff730000 0x0 0x100>;
1213                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1214                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1215
1216                         gpio-controller;
1217                         #gpio-cells = <0x2>;
1218
1219                         interrupt-controller;
1220                         #interrupt-cells = <0x2>;
1221                 };
1222
1223                 gpio2: gpio2@ff780000 {
1224                         compatible = "rockchip,gpio-bank";
1225                         reg = <0x0 0xff780000 0x0 0x100>;
1226                         clocks = <&cru PCLK_GPIO2>;
1227                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1228
1229                         gpio-controller;
1230                         #gpio-cells = <0x2>;
1231
1232                         interrupt-controller;
1233                         #interrupt-cells = <0x2>;
1234                 };
1235
1236                 gpio3: gpio3@ff788000 {
1237                         compatible = "rockchip,gpio-bank";
1238                         reg = <0x0 0xff788000 0x0 0x100>;
1239                         clocks = <&cru PCLK_GPIO3>;
1240                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1241
1242                         gpio-controller;
1243                         #gpio-cells = <0x2>;
1244
1245                         interrupt-controller;
1246                         #interrupt-cells = <0x2>;
1247                 };
1248
1249                 gpio4: gpio4@ff790000 {
1250                         compatible = "rockchip,gpio-bank";
1251                         reg = <0x0 0xff790000 0x0 0x100>;
1252                         clocks = <&cru PCLK_GPIO4>;
1253                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1254
1255                         gpio-controller;
1256                         #gpio-cells = <0x2>;
1257
1258                         interrupt-controller;
1259                         #interrupt-cells = <0x2>;
1260                 };
1261
1262                 pcfg_pull_up: pcfg-pull-up {
1263                         bias-pull-up;
1264                 };
1265
1266                 pcfg_pull_down: pcfg-pull-down {
1267                         bias-pull-down;
1268                 };
1269
1270                 pcfg_pull_none: pcfg-pull-none {
1271                         bias-disable;
1272                 };
1273
1274                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1275                         bias-disable;
1276                         drive-strength = <12>;
1277                 };
1278
1279                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1280                         bias-pull-up;
1281                         drive-strength = <8>;
1282                 };
1283
1284                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1285                         bias-pull-down;
1286                         drive-strength = <4>;
1287                 };
1288
1289                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1290                         bias-pull-up;
1291                         drive-strength = <2>;
1292                 };
1293
1294                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1295                         bias-pull-down;
1296                         drive-strength = <12>;
1297                 };
1298
1299                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1300                         bias-disable;
1301                         drive-strength = <13>;
1302                 };
1303
1304                 clock {
1305                         clk_32k: clk-32k {
1306                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1307                         };
1308                 };
1309
1310                 i2c0 {
1311                         i2c0_xfer: i2c0-xfer {
1312                                 rockchip,pins =
1313                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1314                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1315                         };
1316                 };
1317
1318                 i2c1 {
1319                         i2c1_xfer: i2c1-xfer {
1320                                 rockchip,pins =
1321                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1322                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1323                         };
1324                 };
1325
1326                 i2c2 {
1327                         i2c2_xfer: i2c2-xfer {
1328                                 rockchip,pins =
1329                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1330                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1331                         };
1332                 };
1333
1334                 i2c3 {
1335                         i2c3_xfer: i2c3-xfer {
1336                                 rockchip,pins =
1337                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1338                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1339                         };
1340                 };
1341
1342                 i2c4 {
1343                         i2c4_xfer: i2c4-xfer {
1344                                 rockchip,pins =
1345                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1346                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1347                         };
1348                 };
1349
1350                 i2c5 {
1351                         i2c5_xfer: i2c5-xfer {
1352                                 rockchip,pins =
1353                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1354                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1355                         };
1356                 };
1357
1358                 i2c6 {
1359                         i2c6_xfer: i2c6-xfer {
1360                                 rockchip,pins =
1361                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1362                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1363                         };
1364                 };
1365
1366                 i2c7 {
1367                         i2c7_xfer: i2c7-xfer {
1368                                 rockchip,pins =
1369                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1370                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1371                         };
1372                 };
1373
1374                 i2c8 {
1375                         i2c8_xfer: i2c8-xfer {
1376                                 rockchip,pins =
1377                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1378                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1379                         };
1380                 };
1381
1382                 i2s0 {
1383                         i2s0_8ch_bus: i2s0-8ch-bus {
1384                                 rockchip,pins =
1385                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1386                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1387                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1388                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1389                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1390                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1391                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1392                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1393                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1394                         };
1395                 };
1396
1397                 i2s1 {
1398                         i2s1_2ch_bus: i2s1-2ch-bus {
1399                                 rockchip,pins =
1400                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1401                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1402                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1403                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1404                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1405                         };
1406                 };
1407
1408                 sleep {
1409                         ap_pwroff: ap-pwroff {
1410                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1411                         };
1412
1413                         ddrio_pwroff: ddrio-pwroff {
1414                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1415                         };
1416                 };
1417
1418                 spdif {
1419                         spdif_bus: spdif-bus {
1420                                 rockchip,pins =
1421                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1422                         };
1423                 };
1424
1425                 spi0 {
1426                         spi0_clk: spi0-clk {
1427                                 rockchip,pins =
1428                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1429                         };
1430                         spi0_cs0: spi0-cs0 {
1431                                 rockchip,pins =
1432                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1433                         };
1434                         spi0_cs1: spi0-cs1 {
1435                                 rockchip,pins =
1436                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1437                         };
1438                         spi0_tx: spi0-tx {
1439                                 rockchip,pins =
1440                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1441                         };
1442                         spi0_rx: spi0-rx {
1443                                 rockchip,pins =
1444                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1445                         };
1446                 };
1447
1448                 spi1 {
1449                         spi1_clk: spi1-clk {
1450                                 rockchip,pins =
1451                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1452                         };
1453                         spi1_cs0: spi1-cs0 {
1454                                 rockchip,pins =
1455                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1456                         };
1457                         spi1_rx: spi1-rx {
1458                                 rockchip,pins =
1459                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1460                         };
1461                         spi1_tx: spi1-tx {
1462                                 rockchip,pins =
1463                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1464                         };
1465                 };
1466
1467                 spi2 {
1468                         spi2_clk: spi2-clk {
1469                                 rockchip,pins =
1470                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1471                         };
1472                         spi2_cs0: spi2-cs0 {
1473                                 rockchip,pins =
1474                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1475                         };
1476                         spi2_rx: spi2-rx {
1477                                 rockchip,pins =
1478                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1479                         };
1480                         spi2_tx: spi2-tx {
1481                                 rockchip,pins =
1482                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1483                         };
1484                 };
1485
1486                 spi3 {
1487                         spi3_clk: spi3-clk {
1488                                 rockchip,pins =
1489                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1490                         };
1491                         spi3_cs0: spi3-cs0 {
1492                                 rockchip,pins =
1493                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1494                         };
1495                         spi3_rx: spi3-rx {
1496                                 rockchip,pins =
1497                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1498                         };
1499                         spi3_tx: spi3-tx {
1500                                 rockchip,pins =
1501                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1502                         };
1503                 };
1504
1505                 spi4 {
1506                         spi4_clk: spi4-clk {
1507                                 rockchip,pins =
1508                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1509                         };
1510                         spi4_cs0: spi4-cs0 {
1511                                 rockchip,pins =
1512                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1513                         };
1514                         spi4_rx: spi4-rx {
1515                                 rockchip,pins =
1516                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1517                         };
1518                         spi4_tx: spi4-tx {
1519                                 rockchip,pins =
1520                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1521                         };
1522                 };
1523
1524                 spi5 {
1525                         spi5_clk: spi5-clk {
1526                                 rockchip,pins =
1527                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1528                         };
1529                         spi5_cs0: spi5-cs0 {
1530                                 rockchip,pins =
1531                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1532                         };
1533                         spi5_rx: spi5-rx {
1534                                 rockchip,pins =
1535                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1536                         };
1537                         spi5_tx: spi5-tx {
1538                                 rockchip,pins =
1539                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1540                         };
1541                 };
1542
1543                 tsadc {
1544                         otp_gpio: otp-gpio {
1545                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1546                         };
1547
1548                         otp_out: otp-out {
1549                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1550                         };
1551                 };
1552
1553                 uart0 {
1554                         uart0_xfer: uart0-xfer {
1555                                 rockchip,pins =
1556                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1557                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1558                         };
1559
1560                         uart0_cts: uart0-cts {
1561                                 rockchip,pins =
1562                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1563                         };
1564
1565                         uart0_rts: uart0-rts {
1566                                 rockchip,pins =
1567                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1568                         };
1569                 };
1570
1571                 uart1 {
1572                         uart1_xfer: uart1-xfer {
1573                                 rockchip,pins =
1574                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1575                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1576                         };
1577                 };
1578
1579                 uart2a {
1580                         uart2a_xfer: uart2a-xfer {
1581                                 rockchip,pins =
1582                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1583                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1584                         };
1585                 };
1586
1587                 uart2b {
1588                         uart2b_xfer: uart2b-xfer {
1589                                 rockchip,pins =
1590                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1591                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1592                         };
1593                 };
1594
1595                 uart2c {
1596                         uart2c_xfer: uart2c-xfer {
1597                                 rockchip,pins =
1598                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1599                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1600                         };
1601                 };
1602
1603                 uart3 {
1604                         uart3_xfer: uart3-xfer {
1605                                 rockchip,pins =
1606                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1607                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1608                         };
1609
1610                         uart3_cts: uart3-cts {
1611                                 rockchip,pins =
1612                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1613                         };
1614
1615                         uart3_rts: uart3-rts {
1616                                 rockchip,pins =
1617                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1618                         };
1619                 };
1620
1621                 uart4 {
1622                         uart4_xfer: uart4-xfer {
1623                                 rockchip,pins =
1624                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1625                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1626                         };
1627                 };
1628
1629                 uarthdcp {
1630                         uarthdcp_xfer: uarthdcp-xfer {
1631                                 rockchip,pins =
1632                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1633                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1634                         };
1635                 };
1636
1637                 pwm0 {
1638                         pwm0_pin: pwm0-pin {
1639                                 rockchip,pins =
1640                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1641                         };
1642
1643                         vop0_pwm_pin: vop0-pwm-pin {
1644                                 rockchip,pins =
1645                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1646                         };
1647                 };
1648
1649                 pwm1 {
1650                         pwm1_pin: pwm1-pin {
1651                                 rockchip,pins =
1652                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1653                         };
1654
1655                         vop1_pwm_pin: vop1-pwm-pin {
1656                                 rockchip,pins =
1657                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1658                         };
1659                 };
1660
1661                 pwm2 {
1662                         pwm2_pin: pwm2-pin {
1663                                 rockchip,pins =
1664                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1665                         };
1666                 };
1667
1668                 pwm3a {
1669                         pwm3a_pin: pwm3a-pin {
1670                                 rockchip,pins =
1671                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1672                         };
1673                 };
1674
1675                 pwm3b {
1676                         pwm3b_pin: pwm3b-pin {
1677                                 rockchip,pins =
1678                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1679                         };
1680                 };
1681
1682                 pcie {
1683                         pcie_clkreqn: pci-clkreqn {
1684                                 rockchip,pins =
1685                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
1686                         };
1687
1688                         pcie_clkreqnb: pci-clkreqnb {
1689                                 rockchip,pins =
1690                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1691                         };
1692                 };
1693
1694         };
1695 };