arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 i2c6 = &i2c6;
  66                 i2c7 = &i2c7;
  67                 i2c8 = &i2c8;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73         };
  74
  75         cpus {
  76                 #address-cells = <2>;
  77                 #size-cells = <0>;
  78
  79                 cpu-map {
  80                         cluster0 {
  81                                 core0 {
  82                                         cpu = <&cpu_l0>;
  83                                 };
  84                                 core1 {
  85                                         cpu = <&cpu_l1>;
  86                                 };
  87                                 core2 {
  88                                         cpu = <&cpu_l2>;
  89                                 };
  90                                 core3 {
  91                                         cpu = <&cpu_l3>;
  92                                 };
  93                         };
  94
  95                         cluster1 {
  96                                 core0 {
  97                                         cpu = <&cpu_b0>;
  98                                 };
  99                                 core1 {
 100                                         cpu = <&cpu_b1>;
 101                                 };
 102                         };
 103                 };
 104
 105                 cpu_l0: cpu@0 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53", "arm,armv8";
 108                         reg = <0x0 0x0>;
 109                         enable-method = "psci";
 110                         #cooling-cells = <2>; /* min followed by max */
 111                         clocks = <&cru ARMCLKL>;
 112                 };
 113
 114                 cpu_l1: cpu@1 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a53", "arm,armv8";
 117                         reg = <0x0 0x1>;
 118                         enable-method = "psci";
 119                         clocks = <&cru ARMCLKL>;
 120                 };
 121
 122                 cpu_l2: cpu@2 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53", "arm,armv8";
 125                         reg = <0x0 0x2>;
 126                         enable-method = "psci";
 127                         clocks = <&cru ARMCLKL>;
 128                 };
 129
 130                 cpu_l3: cpu@3 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a53", "arm,armv8";
 133                         reg = <0x0 0x3>;
 134                         enable-method = "psci";
 135                         clocks = <&cru ARMCLKL>;
 136                 };
 137
 138                 cpu_b0: cpu@100 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a72", "arm,armv8";
 141                         reg = <0x0 0x100>;
 142                         enable-method = "psci";
 143                         #cooling-cells = <2>; /* min followed by max */
 144                         clocks = <&cru ARMCLKB>;
 145                 };
 146
 147                 cpu_b1: cpu@101 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72", "arm,armv8";
 150                         reg = <0x0 0x101>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKB>;
 153                 };
 154         };
 155
 156         psci {
 157                 compatible = "arm,psci-1.0";
 158                 method = "smc";
 159         };
 160
 161         timer {
 162                 compatible = "arm,armv8-timer";
 163                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 164                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 165                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 166                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 167         };
 168
 169         xin24m: xin24m {
 170                 compatible = "fixed-clock";
 171                 clock-frequency = <24000000>;
 172                 clock-output-names = "xin24m";
 173                 #clock-cells = <0>;
 174         };
 175
 176         amba {
 177                 compatible = "simple-bus";
 178                 #address-cells = <2>;
 179                 #size-cells = <2>;
 180                 ranges;
 181
 182                 dmac_bus: dma-controller@ff6d0000 {
 183                         compatible = "arm,pl330", "arm,primecell";
 184                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 185                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 187                         #dma-cells = <1>;
 188                         clocks = <&cru ACLK_DMAC0_PERILP>;
 189                         clock-names = "apb_pclk";
 190                 };
 191
 192                 dmac_peri: dma-controller@ff6e0000 {
 193                         compatible = "arm,pl330", "arm,primecell";
 194                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 195                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 197                         #dma-cells = <1>;
 198                         clocks = <&cru ACLK_DMAC1_PERILP>;
 199                         clock-names = "apb_pclk";
 200                 };
 201         };
 202
 203         sdio0: dwmmc@fe310000 {
 204                 compatible = "rockchip,rk3399-dw-mshc",
 205                              "rockchip,rk3288-dw-mshc";
 206                 reg = <0x0 0xfe310000 0x0 0x4000>;
 207                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 208                 clock-freq-min-max = <400000 150000000>;
 209                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 210                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 211                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 212                 fifo-depth = <0x100>;
 213                 status = "disabled";
 214         };
 215
 216         sdmmc: dwmmc@fe320000 {
 217                 compatible = "rockchip,rk3399-dw-mshc",
 218                              "rockchip,rk3288-dw-mshc";
 219                 reg = <0x0 0xfe320000 0x0 0x4000>;
 220                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 221                 clock-freq-min-max = <400000 150000000>;
 222                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 223                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 224                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 225                 fifo-depth = <0x100>;
 226                 status = "disabled";
 227         };
 228
 229         sdhci: sdhci@fe330000 {
 230                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 231                 reg = <0x0 0xfe330000 0x0 0x10000>;
 232                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 233                 arasan,soc-ctl-syscon = <&grf>;
 234                 assigned-clocks = <&cru SCLK_EMMC>;
 235                 assigned-clock-rates = <200000000>;
 236                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 237                 clock-names = "clk_xin", "clk_ahb";
 238                 clock-output-names = "emmc_cardclock";
 239                 #clock-cells = <0>;
 240                 phys = <&emmc_phy>;
 241                 phy-names = "phy_arasan";
 242                 status = "disabled";
 243         };
 244
 245         usb_host0_ehci: usb@fe380000 {
 246                 compatible = "generic-ehci";
 247                 reg = <0x0 0xfe380000 0x0 0x20000>;
 248                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 249                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 250                 clock-names = "hclk_host0", "hclk_host0_arb";
 251                 phys = <&u2phy0_host>;
 252                 phy-names = "usb";
 253                 status = "disabled";
 254         };
 255
 256         usb_host0_ohci: usb@fe3a0000 {
 257                 compatible = "generic-ohci";
 258                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 259                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 260                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 261                 clock-names = "hclk_host0", "hclk_host0_arb";
 262                 status = "disabled";
 263         };
 264
 265         usb_host1_ehci: usb@fe3c0000 {
 266                 compatible = "generic-ehci";
 267                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 268                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 270                 clock-names = "hclk_host1", "hclk_host1_arb";
 271                 phys = <&u2phy1_host>;
 272                 phy-names = "usb";
 273                 status = "disabled";
 274         };
 275
 276         usb_host1_ohci: usb@fe3e0000 {
 277                 compatible = "generic-ohci";
 278                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 279                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 280                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 281                 clock-names = "hclk_host1", "hclk_host1_arb";
 282                 status = "disabled";
 283         };
 284
 285         gic: interrupt-controller@fee00000 {
 286                 compatible = "arm,gic-v3";
 287                 #interrupt-cells = <3>;
 288                 #address-cells = <2>;
 289                 #size-cells = <2>;
 290                 ranges;
 291                 interrupt-controller;
 292
 293                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 294                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 295                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 296                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 297                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 298                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 299                 its: interrupt-controller@fee20000 {
 300                         compatible = "arm,gic-v3-its";
 301                         msi-controller;
 302                         reg = <0x0 0xfee20000 0x0 0x20000>;
 303                 };
 304         };
 305
 306         saradc: saradc@ff100000 {
 307                 compatible = "rockchip,rk3399-saradc";
 308                 reg = <0x0 0xff100000 0x0 0x100>;
 309                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 310                 #io-channel-cells = <1>;
 311                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 312                 clock-names = "saradc", "apb_pclk";
 313                 resets = <&cru SRST_P_SARADC>;
 314                 reset-names = "saradc-apb";
 315                 status = "disabled";
 316         };
 317
 318         i2c1: i2c@ff110000 {
 319                 compatible = "rockchip,rk3399-i2c";
 320                 reg = <0x0 0xff110000 0x0 0x1000>;
 321                 assigned-clocks = <&cru SCLK_I2C1>;
 322                 assigned-clock-rates = <200000000>;
 323                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 324                 clock-names = "i2c", "pclk";
 325                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 326                 pinctrl-names = "default";
 327                 pinctrl-0 = <&i2c1_xfer>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330                 status = "disabled";
 331         };
 332
 333         i2c2: i2c@ff120000 {
 334                 compatible = "rockchip,rk3399-i2c";
 335                 reg = <0x0 0xff120000 0x0 0x1000>;
 336                 assigned-clocks = <&cru SCLK_I2C2>;
 337                 assigned-clock-rates = <200000000>;
 338                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 339                 clock-names = "i2c", "pclk";
 340                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 341                 pinctrl-names = "default";
 342                 pinctrl-0 = <&i2c2_xfer>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 status = "disabled";
 346         };
 347
 348         i2c3: i2c@ff130000 {
 349                 compatible = "rockchip,rk3399-i2c";
 350                 reg = <0x0 0xff130000 0x0 0x1000>;
 351                 assigned-clocks = <&cru SCLK_I2C3>;
 352                 assigned-clock-rates = <200000000>;
 353                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 354                 clock-names = "i2c", "pclk";
 355                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 356                 pinctrl-names = "default";
 357                 pinctrl-0 = <&i2c3_xfer>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 status = "disabled";
 361         };
 362
 363         i2c5: i2c@ff140000 {
 364                 compatible = "rockchip,rk3399-i2c";
 365                 reg = <0x0 0xff140000 0x0 0x1000>;
 366                 assigned-clocks = <&cru SCLK_I2C5>;
 367                 assigned-clock-rates = <200000000>;
 368                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 369                 clock-names = "i2c", "pclk";
 370                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 371                 pinctrl-names = "default";
 372                 pinctrl-0 = <&i2c5_xfer>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 status = "disabled";
 376         };
 377
 378         i2c6: i2c@ff150000 {
 379                 compatible = "rockchip,rk3399-i2c";
 380                 reg = <0x0 0xff150000 0x0 0x1000>;
 381                 assigned-clocks = <&cru SCLK_I2C6>;
 382                 assigned-clock-rates = <200000000>;
 383                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 384                 clock-names = "i2c", "pclk";
 385                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&i2c6_xfer>;
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 status = "disabled";
 391         };
 392
 393         i2c7: i2c@ff160000 {
 394                 compatible = "rockchip,rk3399-i2c";
 395                 reg = <0x0 0xff160000 0x0 0x1000>;
 396                 assigned-clocks = <&cru SCLK_I2C7>;
 397                 assigned-clock-rates = <200000000>;
 398                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 399                 clock-names = "i2c", "pclk";
 400                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&i2c7_xfer>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 status = "disabled";
 406         };
 407
 408         uart0: serial@ff180000 {
 409                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 410                 reg = <0x0 0xff180000 0x0 0x100>;
 411                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 412                 clock-names = "baudclk", "apb_pclk";
 413                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 414                 reg-shift = <2>;
 415                 reg-io-width = <4>;
 416                 pinctrl-names = "default";
 417                 pinctrl-0 = <&uart0_xfer>;
 418                 status = "disabled";
 419         };
 420
 421         uart1: serial@ff190000 {
 422                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 423                 reg = <0x0 0xff190000 0x0 0x100>;
 424                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 425                 clock-names = "baudclk", "apb_pclk";
 426                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 427                 reg-shift = <2>;
 428                 reg-io-width = <4>;
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&uart1_xfer>;
 431                 status = "disabled";
 432         };
 433
 434         uart2: serial@ff1a0000 {
 435                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 436                 reg = <0x0 0xff1a0000 0x0 0x100>;
 437                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 438                 clock-names = "baudclk", "apb_pclk";
 439                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 440                 reg-shift = <2>;
 441                 reg-io-width = <4>;
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&uart2c_xfer>;
 444                 status = "disabled";
 445         };
 446
 447         uart3: serial@ff1b0000 {
 448                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 449                 reg = <0x0 0xff1b0000 0x0 0x100>;
 450                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 451                 clock-names = "baudclk", "apb_pclk";
 452                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 453                 reg-shift = <2>;
 454                 reg-io-width = <4>;
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&uart3_xfer>;
 457                 status = "disabled";
 458         };
 459
 460         spi0: spi@ff1c0000 {
 461                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 462                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 463                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 464                 clock-names = "spiclk", "apb_pclk";
 465                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 466                 pinctrl-names = "default";
 467                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 468                 #address-cells = <1>;
 469                 #size-cells = <0>;
 470                 status = "disabled";
 471         };
 472
 473         spi1: spi@ff1d0000 {
 474                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 475                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 476                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 477                 clock-names = "spiclk", "apb_pclk";
 478                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 479                 pinctrl-names = "default";
 480                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 481                 #address-cells = <1>;
 482                 #size-cells = <0>;
 483                 status = "disabled";
 484         };
 485
 486         spi2: spi@ff1e0000 {
 487                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 488                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 489                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 490                 clock-names = "spiclk", "apb_pclk";
 491                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 494                 #address-cells = <1>;
 495                 #size-cells = <0>;
 496                 status = "disabled";
 497         };
 498
 499         spi4: spi@ff1f0000 {
 500                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 501                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 502                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 503                 clock-names = "spiclk", "apb_pclk";
 504                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 505                 pinctrl-names = "default";
 506                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 507                 #address-cells = <1>;
 508                 #size-cells = <0>;
 509                 status = "disabled";
 510         };
 511
 512         spi5: spi@ff200000 {
 513                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 514                 reg = <0x0 0xff200000 0x0 0x1000>;
 515                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 516                 clock-names = "spiclk", "apb_pclk";
 517                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 518                 pinctrl-names = "default";
 519                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 status = "disabled";
 523         };
 524
 525         thermal-zones {
 526                 cpu_thermal: cpu {
 527                         polling-delay-passive = <100>;
 528                         polling-delay = <1000>;
 529
 530                         thermal-sensors = <&tsadc 0>;
 531
 532                         trips {
 533                                 cpu_alert0: cpu_alert0 {
 534                                         temperature = <70000>;
 535                                         hysteresis = <2000>;
 536                                         type = "passive";
 537                                 };
 538                                 cpu_alert1: cpu_alert1 {
 539                                         temperature = <75000>;
 540                                         hysteresis = <2000>;
 541                                         type = "passive";
 542                                 };
 543                                 cpu_crit: cpu_crit {
 544                                         temperature = <95000>;
 545                                         hysteresis = <2000>;
 546                                         type = "critical";
 547                                 };
 548                         };
 549
 550                         cooling-maps {
 551                                 map0 {
 552                                         trip = <&cpu_alert0>;
 553                                         cooling-device =
 554                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 555                                 };
 556                                 map1 {
 557                                         trip = <&cpu_alert1>;
 558                                         cooling-device =
 559                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 560                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 561                                 };
 562                         };
 563                 };
 564
 565                 gpu_thermal: gpu {
 566                         polling-delay-passive = <100>;
 567                         polling-delay = <1000>;
 568
 569                         thermal-sensors = <&tsadc 1>;
 570
 571                         trips {
 572                                 gpu_alert0: gpu_alert0 {
 573                                         temperature = <75000>;
 574                                         hysteresis = <2000>;
 575                                         type = "passive";
 576                                 };
 577                                 gpu_crit: gpu_crit {
 578                                         temperature = <95000>;
 579                                         hysteresis = <2000>;
 580                                         type = "critical";
 581                                 };
 582                         };
 583
 584                         cooling-maps {
 585                                 map0 {
 586                                         trip = <&gpu_alert0>;
 587                                         cooling-device =
 588                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 589                                 };
 590                         };
 591                 };
 592         };
 593
 594         tsadc: tsadc@ff260000 {
 595                 compatible = "rockchip,rk3399-tsadc";
 596                 reg = <0x0 0xff260000 0x0 0x100>;
 597                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 598                 assigned-clocks = <&cru SCLK_TSADC>;
 599                 assigned-clock-rates = <750000>;
 600                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 601                 clock-names = "tsadc", "apb_pclk";
 602                 resets = <&cru SRST_TSADC>;
 603                 reset-names = "tsadc-apb";
 604                 rockchip,grf = <&grf>;
 605                 rockchip,hw-tshut-temp = <95000>;
 606                 pinctrl-names = "init", "default", "sleep";
 607                 pinctrl-0 = <&otp_gpio>;
 608                 pinctrl-1 = <&otp_out>;
 609                 pinctrl-2 = <&otp_gpio>;
 610                 #thermal-sensor-cells = <1>;
 611                 status = "disabled";
 612         };
 613
 614         qos_hdcp: qos@ffa90000 {
 615                 compatible = "syscon";
 616                 reg = <0x0 0xffa90000 0x0 0x20>;
 617         };
 618
 619         qos_iep: qos@ffa98000 {
 620                 compatible = "syscon";
 621                 reg = <0x0 0xffa98000 0x0 0x20>;
 622         };
 623
 624         qos_isp0_m0: qos@ffaa0000 {
 625                 compatible = "syscon";
 626                 reg = <0x0 0xffaa0000 0x0 0x20>;
 627         };
 628
 629         qos_isp0_m1: qos@ffaa0080 {
 630                 compatible = "syscon";
 631                 reg = <0x0 0xffaa0080 0x0 0x20>;
 632         };
 633
 634         qos_isp1_m0: qos@ffaa8000 {
 635                 compatible = "syscon";
 636                 reg = <0x0 0xffaa8000 0x0 0x20>;
 637         };
 638
 639         qos_isp1_m1: qos@ffaa8080 {
 640                 compatible = "syscon";
 641                 reg = <0x0 0xffaa8080 0x0 0x20>;
 642         };
 643
 644         qos_rga_r: qos@ffab0000 {
 645                 compatible = "syscon";
 646                 reg = <0x0 0xffab0000 0x0 0x20>;
 647         };
 648
 649         qos_rga_w: qos@ffab0080 {
 650                 compatible = "syscon";
 651                 reg = <0x0 0xffab0080 0x0 0x20>;
 652         };
 653
 654         qos_video_m0: qos@ffab8000 {
 655                 compatible = "syscon";
 656                 reg = <0x0 0xffab8000 0x0 0x20>;
 657         };
 658
 659         qos_video_m1_r: qos@ffac0000 {
 660                 compatible = "syscon";
 661                 reg = <0x0 0xffac0000 0x0 0x20>;
 662         };
 663
 664         qos_video_m1_w: qos@ffac0080 {
 665                 compatible = "syscon";
 666                 reg = <0x0 0xffac0080 0x0 0x20>;
 667         };
 668
 669         qos_vop_big_r: qos@ffac8000 {
 670                 compatible = "syscon";
 671                 reg = <0x0 0xffac8000 0x0 0x20>;
 672         };
 673
 674         qos_vop_big_w: qos@ffac8080 {
 675                 compatible = "syscon";
 676                 reg = <0x0 0xffac8080 0x0 0x20>;
 677         };
 678
 679         qos_vop_little: qos@ffad0000 {
 680                 compatible = "syscon";
 681                 reg = <0x0 0xffad0000 0x0 0x20>;
 682         };
 683
 684         qos_gpu: qos@ffae0000 {
 685                 compatible = "syscon";
 686                 reg = <0x0 0xffae0000 0x0 0x20>;
 687         };
 688
 689         pmu: power-management@ff310000 {
 690                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 691                 reg = <0x0 0xff310000 0x0 0x1000>;
 692
 693                 /*
 694                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 695                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 696                  * Some of the power domains are grouped together for every
 697                  * voltage domain.
 698                  * The detail contents as below.
 699                  */
 700                 power: power-controller {
 701                         compatible = "rockchip,rk3399-power-controller";
 702                         #power-domain-cells = <1>;
 703                         #address-cells = <1>;
 704                         #size-cells = <0>;
 705
 706                         /* These power domains are grouped by VD_CENTER */
 707                         pd_iep@RK3399_PD_IEP {
 708                                 reg = <RK3399_PD_IEP>;
 709                                 clocks = <&cru ACLK_IEP>,
 710                                          <&cru HCLK_IEP>;
 711                                 pm_qos = <&qos_iep>;
 712                         };
 713                         pd_rga@RK3399_PD_RGA {
 714                                 reg = <RK3399_PD_RGA>;
 715                                 clocks = <&cru ACLK_RGA>,
 716                                          <&cru HCLK_RGA>;
 717                                 pm_qos = <&qos_rga_r>,
 718                                          <&qos_rga_w>;
 719                         };
 720                         pd_vcodec@RK3399_PD_VCODEC {
 721                                 reg = <RK3399_PD_VCODEC>;
 722                                 clocks = <&cru ACLK_VCODEC>,
 723                                          <&cru HCLK_VCODEC>;
 724                                 pm_qos = <&qos_video_m0>;
 725                         };
 726                         pd_vdu@RK3399_PD_VDU {
 727                                 reg = <RK3399_PD_VDU>;
 728                                 clocks = <&cru ACLK_VDU>,
 729                                          <&cru HCLK_VDU>;
 730                                 pm_qos = <&qos_video_m1_r>,
 731                                          <&qos_video_m1_w>;
 732                         };
 733
 734                         /* These power domains are grouped by VD_GPU */
 735                         pd_gpu@RK3399_PD_GPU {
 736                                 reg = <RK3399_PD_GPU>;
 737                                 clocks = <&cru ACLK_GPU>;
 738                                 pm_qos = <&qos_gpu>;
 739                         };
 740
 741                         /* These power domains are grouped by VD_LOGIC */
 742                         pd_vio@RK3399_PD_VIO {
 743                                 reg = <RK3399_PD_VIO>;
 744                                 #address-cells = <1>;
 745                                 #size-cells = <0>;
 746
 747                                 pd_hdcp@RK3399_PD_HDCP {
 748                                         reg = <RK3399_PD_HDCP>;
 749                                         clocks = <&cru ACLK_HDCP>,
 750                                                  <&cru HCLK_HDCP>,
 751                                                  <&cru PCLK_HDCP>;
 752                                         pm_qos = <&qos_hdcp>;
 753                                 };
 754                                 pd_isp0@RK3399_PD_ISP0 {
 755                                         reg = <RK3399_PD_ISP0>;
 756                                         clocks = <&cru ACLK_ISP0>,
 757                                                  <&cru HCLK_ISP0>;
 758                                         pm_qos = <&qos_isp0_m0>,
 759                                                  <&qos_isp0_m1>;
 760                                 };
 761                                 pd_isp1@RK3399_PD_ISP1 {
 762                                         reg = <RK3399_PD_ISP1>;
 763                                         clocks = <&cru ACLK_ISP1>,
 764                                                  <&cru HCLK_ISP1>;
 765                                         pm_qos = <&qos_isp1_m0>,
 766                                                  <&qos_isp1_m1>;
 767                                 };
 768                                 pd_vo@RK3399_PD_VO {
 769                                         reg = <RK3399_PD_VO>;
 770                                         #address-cells = <1>;
 771                                         #size-cells = <0>;
 772
 773                                         pd_vopb@RK3399_PD_VOPB {
 774                                                 reg = <RK3399_PD_VOPB>;
 775                                                 clocks = <&cru ACLK_VOP0>,
 776                                                          <&cru HCLK_VOP0>;
 777                                                 pm_qos = <&qos_vop_big_r>,
 778                                                          <&qos_vop_big_w>;
 779                                         };
 780                                         pd_vopl@RK3399_PD_VOPL {
 781                                                 reg = <RK3399_PD_VOPL>;
 782                                                 clocks = <&cru ACLK_VOP1>,
 783                                                          <&cru HCLK_VOP1>;
 784                                                 pm_qos = <&qos_vop_little>;
 785                                         };
 786                                 };
 787                         };
 788                 };
 789         };
 790
 791         pmugrf: syscon@ff320000 {
 792                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 793                 reg = <0x0 0xff320000 0x0 0x1000>;
 794                 #address-cells = <1>;
 795                 #size-cells = <1>;
 796
 797                 pmu_io_domains: io-domains {
 798                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 799                         status = "disabled";
 800                 };
 801         };
 802
 803         spi3: spi@ff350000 {
 804                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 805                 reg = <0x0 0xff350000 0x0 0x1000>;
 806                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 807                 clock-names = "spiclk", "apb_pclk";
 808                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 809                 pinctrl-names = "default";
 810                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 811                 #address-cells = <1>;
 812                 #size-cells = <0>;
 813                 status = "disabled";
 814         };
 815
 816         uart4: serial@ff370000 {
 817                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 818                 reg = <0x0 0xff370000 0x0 0x100>;
 819                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 820                 clock-names = "baudclk", "apb_pclk";
 821                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 822                 reg-shift = <2>;
 823                 reg-io-width = <4>;
 824                 pinctrl-names = "default";
 825                 pinctrl-0 = <&uart4_xfer>;
 826                 status = "disabled";
 827         };
 828
 829         i2c0: i2c@ff3c0000 {
 830                 compatible = "rockchip,rk3399-i2c";
 831                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 832                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
 833                 assigned-clock-rates = <200000000>;
 834                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 835                 clock-names = "i2c", "pclk";
 836                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 837                 pinctrl-names = "default";
 838                 pinctrl-0 = <&i2c0_xfer>;
 839                 #address-cells = <1>;
 840                 #size-cells = <0>;
 841                 status = "disabled";
 842         };
 843
 844         i2c4: i2c@ff3d0000 {
 845                 compatible = "rockchip,rk3399-i2c";
 846                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 847                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
 848                 assigned-clock-rates = <200000000>;
 849                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 850                 clock-names = "i2c", "pclk";
 851                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 852                 pinctrl-names = "default";
 853                 pinctrl-0 = <&i2c4_xfer>;
 854                 #address-cells = <1>;
 855                 #size-cells = <0>;
 856                 status = "disabled";
 857         };
 858
 859         i2c8: i2c@ff3e0000 {
 860                 compatible = "rockchip,rk3399-i2c";
 861                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 862                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
 863                 assigned-clock-rates = <200000000>;
 864                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 865                 clock-names = "i2c", "pclk";
 866                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 867                 pinctrl-names = "default";
 868                 pinctrl-0 = <&i2c8_xfer>;
 869                 #address-cells = <1>;
 870                 #size-cells = <0>;
 871                 status = "disabled";
 872         };
 873
 874         pwm0: pwm@ff420000 {
 875                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 876                 reg = <0x0 0xff420000 0x0 0x10>;
 877                 #pwm-cells = <3>;
 878                 pinctrl-names = "default";
 879                 pinctrl-0 = <&pwm0_pin>;
 880                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 881                 clock-names = "pwm";
 882                 status = "disabled";
 883         };
 884
 885         pwm1: pwm@ff420010 {
 886                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 887                 reg = <0x0 0xff420010 0x0 0x10>;
 888                 #pwm-cells = <3>;
 889                 pinctrl-names = "default";
 890                 pinctrl-0 = <&pwm1_pin>;
 891                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 892                 clock-names = "pwm";
 893                 status = "disabled";
 894         };
 895
 896         pwm2: pwm@ff420020 {
 897                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 898                 reg = <0x0 0xff420020 0x0 0x10>;
 899                 #pwm-cells = <3>;
 900                 pinctrl-names = "default";
 901                 pinctrl-0 = <&pwm2_pin>;
 902                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 903                 clock-names = "pwm";
 904                 status = "disabled";
 905         };
 906
 907         pwm3: pwm@ff420030 {
 908                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 909                 reg = <0x0 0xff420030 0x0 0x10>;
 910                 #pwm-cells = <3>;
 911                 pinctrl-names = "default";
 912                 pinctrl-0 = <&pwm3a_pin>;
 913                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 914                 clock-names = "pwm";
 915                 status = "disabled";
 916         };
 917
 918         pmucru: pmu-clock-controller@ff750000 {
 919                 compatible = "rockchip,rk3399-pmucru";
 920                 reg = <0x0 0xff750000 0x0 0x1000>;
 921                 #clock-cells = <1>;
 922                 #reset-cells = <1>;
 923                 assigned-clocks = <&pmucru PLL_PPLL>;
 924                 assigned-clock-rates = <676000000>;
 925         };
 926
 927         cru: clock-controller@ff760000 {
 928                 compatible = "rockchip,rk3399-cru";
 929                 reg = <0x0 0xff760000 0x0 0x1000>;
 930                 #clock-cells = <1>;
 931                 #reset-cells = <1>;
 932                 assigned-clocks =
 933                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 934                         <&cru PLL_NPLL>,
 935                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 936                         <&cru PCLK_PERIHP>,
 937                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 938                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
 939                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 940                 assigned-clock-rates =
 941                          <594000000>,  <800000000>,
 942                         <1000000000>,
 943                          <150000000>,   <75000000>,
 944                           <37500000>,
 945                          <100000000>,  <100000000>,
 946                           <50000000>, <600000000>,
 947                          <100000000>,   <50000000>;
 948         };
 949
 950         grf: syscon@ff770000 {
 951                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
 952                 reg = <0x0 0xff770000 0x0 0x10000>;
 953                 #address-cells = <1>;
 954                 #size-cells = <1>;
 955
 956                 io_domains: io-domains {
 957                         compatible = "rockchip,rk3399-io-voltage-domain";
 958                         status = "disabled";
 959                 };
 960
 961                 u2phy0: usb2-phy@e450 {
 962                         compatible = "rockchip,rk3399-usb2phy";
 963                         reg = <0xe450 0x10>;
 964                         clocks = <&cru SCLK_USB2PHY0_REF>;
 965                         clock-names = "phyclk";
 966                         #clock-cells = <0>;
 967                         clock-output-names = "clk_usbphy0_480m";
 968                         status = "disabled";
 969
 970                         u2phy0_host: host-port {
 971                                 #phy-cells = <0>;
 972                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 973                                 interrupt-names = "linestate";
 974                                 status = "disabled";
 975                         };
 976                 };
 977
 978                 u2phy1: usb2-phy@e460 {
 979                         compatible = "rockchip,rk3399-usb2phy";
 980                         reg = <0xe460 0x10>;
 981                         clocks = <&cru SCLK_USB2PHY1_REF>;
 982                         clock-names = "phyclk";
 983                         #clock-cells = <0>;
 984                         clock-output-names = "clk_usbphy1_480m";
 985                         status = "disabled";
 986
 987                         u2phy1_host: host-port {
 988                                 #phy-cells = <0>;
 989                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 990                                 interrupt-names = "linestate";
 991                                 status = "disabled";
 992                         };
 993                 };
 994
 995                 emmc_phy: phy@f780 {
 996                         compatible = "rockchip,rk3399-emmc-phy";
 997                         reg = <0xf780 0x24>;
 998                         clocks = <&sdhci>;
 999                         clock-names = "emmcclk";
1000                         #phy-cells = <0>;
1001                         status = "disabled";
1002                 };
1003         };
1004
1005         watchdog@ff848000 {
1006                 compatible = "snps,dw-wdt";
1007                 reg = <0x0 0xff848000 0x0 0x100>;
1008                 clocks = <&cru PCLK_WDT>;
1009                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1010         };
1011
1012         rktimer: rktimer@ff850000 {
1013                 compatible = "rockchip,rk3399-timer";
1014                 reg = <0x0 0xff850000 0x0 0x1000>;
1015                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1016                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1017                 clock-names = "pclk", "timer";
1018         };
1019
1020         spdif: spdif@ff870000 {
1021                 compatible = "rockchip,rk3399-spdif";
1022                 reg = <0x0 0xff870000 0x0 0x1000>;
1023                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1024                 dmas = <&dmac_bus 7>;
1025                 dma-names = "tx";
1026                 clock-names = "mclk", "hclk";
1027                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1028                 pinctrl-names = "default";
1029                 pinctrl-0 = <&spdif_bus>;
1030                 status = "disabled";
1031         };
1032
1033         i2s0: i2s@ff880000 {
1034                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1035                 reg = <0x0 0xff880000 0x0 0x1000>;
1036                 rockchip,grf = <&grf>;
1037                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1038                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1039                 dma-names = "tx", "rx";
1040                 clock-names = "i2s_clk", "i2s_hclk";
1041                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1042                 pinctrl-names = "default";
1043                 pinctrl-0 = <&i2s0_8ch_bus>;
1044                 status = "disabled";
1045         };
1046
1047         i2s1: i2s@ff890000 {
1048                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1049                 reg = <0x0 0xff890000 0x0 0x1000>;
1050                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1051                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1052                 dma-names = "tx", "rx";
1053                 clock-names = "i2s_clk", "i2s_hclk";
1054                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1055                 pinctrl-names = "default";
1056                 pinctrl-0 = <&i2s1_2ch_bus>;
1057                 status = "disabled";
1058         };
1059
1060         i2s2: i2s@ff8a0000 {
1061                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1062                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1063                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1064                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1065                 dma-names = "tx", "rx";
1066                 clock-names = "i2s_clk", "i2s_hclk";
1067                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1068                 status = "disabled";
1069         };
1070
1071         pinctrl: pinctrl {
1072                 compatible = "rockchip,rk3399-pinctrl";
1073                 rockchip,grf = <&grf>;
1074                 rockchip,pmu = <&pmugrf>;
1075                 #address-cells = <2>;
1076                 #size-cells = <2>;
1077                 ranges;
1078
1079                 gpio0: gpio0@ff720000 {
1080                         compatible = "rockchip,gpio-bank";
1081                         reg = <0x0 0xff720000 0x0 0x100>;
1082                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1083                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1084
1085                         gpio-controller;
1086                         #gpio-cells = <0x2>;
1087
1088                         interrupt-controller;
1089                         #interrupt-cells = <0x2>;
1090                 };
1091
1092                 gpio1: gpio1@ff730000 {
1093                         compatible = "rockchip,gpio-bank";
1094                         reg = <0x0 0xff730000 0x0 0x100>;
1095                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1096                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1097
1098                         gpio-controller;
1099                         #gpio-cells = <0x2>;
1100
1101                         interrupt-controller;
1102                         #interrupt-cells = <0x2>;
1103                 };
1104
1105                 gpio2: gpio2@ff780000 {
1106                         compatible = "rockchip,gpio-bank";
1107                         reg = <0x0 0xff780000 0x0 0x100>;
1108                         clocks = <&cru PCLK_GPIO2>;
1109                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1110
1111                         gpio-controller;
1112                         #gpio-cells = <0x2>;
1113
1114                         interrupt-controller;
1115                         #interrupt-cells = <0x2>;
1116                 };
1117
1118                 gpio3: gpio3@ff788000 {
1119                         compatible = "rockchip,gpio-bank";
1120                         reg = <0x0 0xff788000 0x0 0x100>;
1121                         clocks = <&cru PCLK_GPIO3>;
1122                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1123
1124                         gpio-controller;
1125                         #gpio-cells = <0x2>;
1126
1127                         interrupt-controller;
1128                         #interrupt-cells = <0x2>;
1129                 };
1130
1131                 gpio4: gpio4@ff790000 {
1132                         compatible = "rockchip,gpio-bank";
1133                         reg = <0x0 0xff790000 0x0 0x100>;
1134                         clocks = <&cru PCLK_GPIO4>;
1135                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1136
1137                         gpio-controller;
1138                         #gpio-cells = <0x2>;
1139
1140                         interrupt-controller;
1141                         #interrupt-cells = <0x2>;
1142                 };
1143
1144                 pcfg_pull_up: pcfg-pull-up {
1145                         bias-pull-up;
1146                 };
1147
1148                 pcfg_pull_down: pcfg-pull-down {
1149                         bias-pull-down;
1150                 };
1151
1152                 pcfg_pull_none: pcfg-pull-none {
1153                         bias-disable;
1154                 };
1155
1156                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1157                         bias-disable;
1158                         drive-strength = <12>;
1159                 };
1160
1161                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1162                         bias-pull-up;
1163                         drive-strength = <8>;
1164                 };
1165
1166                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1167                         bias-pull-down;
1168                         drive-strength = <4>;
1169                 };
1170
1171                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1172                         bias-pull-up;
1173                         drive-strength = <2>;
1174                 };
1175
1176                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1177                         bias-pull-down;
1178                         drive-strength = <12>;
1179                 };
1180
1181                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1182                         bias-disable;
1183                         drive-strength = <13>;
1184                 };
1185
1186                 i2c0 {
1187                         i2c0_xfer: i2c0-xfer {
1188                                 rockchip,pins =
1189                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1190                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1191                         };
1192                 };
1193
1194                 i2c1 {
1195                         i2c1_xfer: i2c1-xfer {
1196                                 rockchip,pins =
1197                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1198                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1199                         };
1200                 };
1201
1202                 i2c2 {
1203                         i2c2_xfer: i2c2-xfer {
1204                                 rockchip,pins =
1205                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1206                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1207                         };
1208                 };
1209
1210                 i2c3 {
1211                         i2c3_xfer: i2c3-xfer {
1212                                 rockchip,pins =
1213                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1214                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1215                         };
1216                 };
1217
1218                 i2c4 {
1219                         i2c4_xfer: i2c4-xfer {
1220                                 rockchip,pins =
1221                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1222                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1223                         };
1224                 };
1225
1226                 i2c5 {
1227                         i2c5_xfer: i2c5-xfer {
1228                                 rockchip,pins =
1229                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1230                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1231                         };
1232                 };
1233
1234                 i2c6 {
1235                         i2c6_xfer: i2c6-xfer {
1236                                 rockchip,pins =
1237                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1238                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1239                         };
1240                 };
1241
1242                 i2c7 {
1243                         i2c7_xfer: i2c7-xfer {
1244                                 rockchip,pins =
1245                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1246                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1247                         };
1248                 };
1249
1250                 i2c8 {
1251                         i2c8_xfer: i2c8-xfer {
1252                                 rockchip,pins =
1253                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1254                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1255                         };
1256                 };
1257
1258                 i2s0 {
1259                         i2s0_8ch_bus: i2s0-8ch-bus {
1260                                 rockchip,pins =
1261                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1262                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1263                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1264                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1265                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1266                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1267                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1268                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1269                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1270                         };
1271                 };
1272
1273                 i2s1 {
1274                         i2s1_2ch_bus: i2s1-2ch-bus {
1275                                 rockchip,pins =
1276                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1277                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1278                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1279                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1280                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1281                         };
1282                 };
1283
1284                 sleep {
1285                         ap_pwroff: ap-pwroff {
1286                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1287                         };
1288
1289                         ddrio_pwroff: ddrio-pwroff {
1290                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1291                         };
1292                 };
1293
1294                 spdif {
1295                         spdif_bus: spdif-bus {
1296                                 rockchip,pins =
1297                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1298                         };
1299                 };
1300
1301                 spi0 {
1302                         spi0_clk: spi0-clk {
1303                                 rockchip,pins =
1304                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1305                         };
1306                         spi0_cs0: spi0-cs0 {
1307                                 rockchip,pins =
1308                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1309                         };
1310                         spi0_cs1: spi0-cs1 {
1311                                 rockchip,pins =
1312                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1313                         };
1314                         spi0_tx: spi0-tx {
1315                                 rockchip,pins =
1316                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1317                         };
1318                         spi0_rx: spi0-rx {
1319                                 rockchip,pins =
1320                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1321                         };
1322                 };
1323
1324                 spi1 {
1325                         spi1_clk: spi1-clk {
1326                                 rockchip,pins =
1327                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1328                         };
1329                         spi1_cs0: spi1-cs0 {
1330                                 rockchip,pins =
1331                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1332                         };
1333                         spi1_rx: spi1-rx {
1334                                 rockchip,pins =
1335                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1336                         };
1337                         spi1_tx: spi1-tx {
1338                                 rockchip,pins =
1339                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1340                         };
1341                 };
1342
1343                 spi2 {
1344                         spi2_clk: spi2-clk {
1345                                 rockchip,pins =
1346                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1347                         };
1348                         spi2_cs0: spi2-cs0 {
1349                                 rockchip,pins =
1350                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1351                         };
1352                         spi2_rx: spi2-rx {
1353                                 rockchip,pins =
1354                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1355                         };
1356                         spi2_tx: spi2-tx {
1357                                 rockchip,pins =
1358                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1359                         };
1360                 };
1361
1362                 spi3 {
1363                         spi3_clk: spi3-clk {
1364                                 rockchip,pins =
1365                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1366                         };
1367                         spi3_cs0: spi3-cs0 {
1368                                 rockchip,pins =
1369                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1370                         };
1371                         spi3_rx: spi3-rx {
1372                                 rockchip,pins =
1373                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1374                         };
1375                         spi3_tx: spi3-tx {
1376                                 rockchip,pins =
1377                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1378                         };
1379                 };
1380
1381                 spi4 {
1382                         spi4_clk: spi4-clk {
1383                                 rockchip,pins =
1384                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1385                         };
1386                         spi4_cs0: spi4-cs0 {
1387                                 rockchip,pins =
1388                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1389                         };
1390                         spi4_rx: spi4-rx {
1391                                 rockchip,pins =
1392                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1393                         };
1394                         spi4_tx: spi4-tx {
1395                                 rockchip,pins =
1396                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1397                         };
1398                 };
1399
1400                 spi5 {
1401                         spi5_clk: spi5-clk {
1402                                 rockchip,pins =
1403                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1404                         };
1405                         spi5_cs0: spi5-cs0 {
1406                                 rockchip,pins =
1407                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1408                         };
1409                         spi5_rx: spi5-rx {
1410                                 rockchip,pins =
1411                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1412                         };
1413                         spi5_tx: spi5-tx {
1414                                 rockchip,pins =
1415                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1416                         };
1417                 };
1418
1419                 tsadc {
1420                         otp_gpio: otp-gpio {
1421                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1422                         };
1423
1424                         otp_out: otp-out {
1425                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1426                         };
1427                 };
1428
1429                 uart0 {
1430                         uart0_xfer: uart0-xfer {
1431                                 rockchip,pins =
1432                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1433                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1434                         };
1435
1436                         uart0_cts: uart0-cts {
1437                                 rockchip,pins =
1438                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1439                         };
1440
1441                         uart0_rts: uart0-rts {
1442                                 rockchip,pins =
1443                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1444                         };
1445                 };
1446
1447                 uart1 {
1448                         uart1_xfer: uart1-xfer {
1449                                 rockchip,pins =
1450                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1451                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1452                         };
1453                 };
1454
1455                 uart2a {
1456                         uart2a_xfer: uart2a-xfer {
1457                                 rockchip,pins =
1458                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1459                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1460                         };
1461                 };
1462
1463                 uart2b {
1464                         uart2b_xfer: uart2b-xfer {
1465                                 rockchip,pins =
1466                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1467                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1468                         };
1469                 };
1470
1471                 uart2c {
1472                         uart2c_xfer: uart2c-xfer {
1473                                 rockchip,pins =
1474                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1475                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1476                         };
1477                 };
1478
1479                 uart3 {
1480                         uart3_xfer: uart3-xfer {
1481                                 rockchip,pins =
1482                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1483                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1484                         };
1485
1486                         uart3_cts: uart3-cts {
1487                                 rockchip,pins =
1488                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1489                         };
1490
1491                         uart3_rts: uart3-rts {
1492                                 rockchip,pins =
1493                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1494                         };
1495                 };
1496
1497                 uart4 {
1498                         uart4_xfer: uart4-xfer {
1499                                 rockchip,pins =
1500                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1501                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1502                         };
1503                 };
1504
1505                 uarthdcp {
1506                         uarthdcp_xfer: uarthdcp-xfer {
1507                                 rockchip,pins =
1508                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1509                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1510                         };
1511                 };
1512
1513                 pwm0 {
1514                         pwm0_pin: pwm0-pin {
1515                                 rockchip,pins =
1516                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1517                         };
1518
1519                         vop0_pwm_pin: vop0-pwm-pin {
1520                                 rockchip,pins =
1521                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1522                         };
1523                 };
1524
1525                 pwm1 {
1526                         pwm1_pin: pwm1-pin {
1527                                 rockchip,pins =
1528                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1529                         };
1530
1531                         vop1_pwm_pin: vop1-pwm-pin {
1532                                 rockchip,pins =
1533                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1534                         };
1535                 };
1536
1537                 pwm2 {
1538                         pwm2_pin: pwm2-pin {
1539                                 rockchip,pins =
1540                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1541                         };
1542                 };
1543
1544                 pwm3a {
1545                         pwm3a_pin: pwm3a-pin {
1546                                 rockchip,pins =
1547                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1548                         };
1549                 };
1550
1551                 pwm3b {
1552                         pwm3b_pin: pwm3b-pin {
1553                                 rockchip,pins =
1554                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1555                         };
1556                 };
1557         };
1558 };